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* Move physreg dependency generation into aptly named addPhysRegDeps.Andrew Trick2012-01-142-155/+182
| | | | llvm-svn: 148173
* misched: Added ScheduleDAGInstrs::IsPostRAAndrew Trick2012-01-144-11/+17
| | | | llvm-svn: 148172
* misched: Invoke the DAG builder on each sequence of schedulable instructions.Andrew Trick2012-01-141-6/+31
| | | | llvm-svn: 148171
* Move things around to make the file navigable, even though it will probably ↵Andrew Trick2012-01-141-19/+32
| | | | | | be split up later. llvm-svn: 148170
* After r147827 and r147902, it's now possible for unallocatable registers to beEvan Cheng2012-01-142-6/+27
| | | | | | | | | | | | | | | | | | | live across BBs before register allocation. This miscompiled 197.parser when a cmp + b are optimized to a cbnz instruction even though the CPSR def is live-in a successor. cbnz r6, LBB89_12 ... LBB89_12: ble LBB89_1 The fix consists of two parts. 1) Teach LiveVariables that some unallocatable registers might be liveouts so don't mark their last use as kill if they are. 2) ARM constantpool island pass shouldn't form cbz / cbnz if the conditional branch does not kill CPSR. rdar://10676853 llvm-svn: 148168
* Fix pasto from r146196.Chad Rosier2012-01-141-2/+2
| | | | llvm-svn: 148167
* Fix an unused variable warning that Chad noticed.Dan Gohman2012-01-141-1/+1
| | | | llvm-svn: 148164
* Remove previous commit while I debug the bot failures.Rafael Espindola2012-01-131-0/+3
| | | | llvm-svn: 148156
* Use RegisterTuples to generate pseudo-registers.Jakob Stoklund Olesen2012-01-134-45/+51
| | | | | | | | | | The QQ and QQQQ registers are not 'real', they are pseudo-registers used to model some vld and vst instructions. This makes the call clobber lists longer, but I intend to get rid of those soon. llvm-svn: 148151
* Remove label that is not used anymore.Rafael Espindola2012-01-131-3/+0
| | | | llvm-svn: 148150
* Speculatively revert r148132+r148133 to try and fix a buildbot failure.Eli Friedman2012-01-131-166/+115
| | | | llvm-svn: 148149
* Remove pointless mode line in .cpp file.Andrew Trick2012-01-131-1/+1
| | | | llvm-svn: 148143
* Revert r148131, it was committed before it was ready.Devang Patel2012-01-131-46/+40
| | | | llvm-svn: 148134
* Cosmetic patch for r148132.Stepan Dyatkovskiy2012-01-131-13/+1
| | | | llvm-svn: 148133
* LoopUnswitch: All helper data that is collected during loop-unswitch ↵Stepan Dyatkovskiy2012-01-131-112/+175
| | | | | | iterations was moved to separated class (LUAnalysisCache). llvm-svn: 148132
* Refactor.Devang Patel2012-01-131-40/+46
| | | | llvm-svn: 148131
* Convert SHUFPD with the same register for both sources to PSHUFD if it would ↵Craig Topper2012-01-132-1/+20
| | | | | | prevent a register copy. Similar to SHUFPS, but requires the mask to be converted. llvm-svn: 148112
* use v8i32 as optimal mem type over v8f32 if AVX2 is enabled. Similar to SSE2 ↵Craig Topper2012-01-131-3/+6
| | | | | | vs SSE1. llvm-svn: 148109
* Make X86 instruction selection use 256-bit VPXOR for build_vector of all ↵Craig Topper2012-01-134-37/+62
| | | | | | ones if AVX2 is enabled. This gives the ExeDepsFix pass a chance to choose FP vs int as appropriate. Also use v8i32 as the type for getZeroVector if AVX2 is enabled. This is consistent with SSE2 using prefering v4i32. llvm-svn: 148108
* Add patterns for v16i16 and v32i8 immAllZerosV to select VPXOR to match ↵Craig Topper2012-01-131-0/+8
| | | | | | v4i64 and v8i32. llvm-svn: 148106
* Added the MachineSchedulerPass skeleton.Andrew Trick2012-01-136-1/+251
| | | | llvm-svn: 148105
* wrong filenameAndrew Trick2012-01-131-1/+1
| | | | llvm-svn: 148103
* 80-col violationAndrew Trick2012-01-131-3/+3
| | | | llvm-svn: 148102
* Use 8i32 constant pool entry for converting AVX2_SETALLONES. Possibly fixes ↵Craig Topper2012-01-131-0/+2
| | | | | | PR11750. llvm-svn: 148101
* Fix typo in PerformAddCombine that caused any vector type to be checked for ↵Craig Topper2012-01-131-1/+1
| | | | | | horizontal add/sub if AVX2 is enabled. This caused an assert to fail for non 128/256-bit vectors when done before type legalizing. Fixes PR11749. llvm-svn: 148096
* Delete CodeInit and CodeRecTy from TableGen.Jakob Stoklund Olesen2012-01-132-33/+3
| | | | | | | The code type was always identical to a string anyway. Now it is simply a synonym. The code literal syntax [{...}] is still valid. llvm-svn: 148092
* Use uniqued StringInit pointers for lookups.Jakob Stoklund Olesen2012-01-132-21/+9
| | | | | | | This avoids a gazillion StringMap and dynamic_cast calls, making TableGen run 3x faster. llvm-svn: 148091
* DAGCombine's logic for forming pre- and post- indexed loads / stores were beingEvan Cheng2012-01-131-9/+44
| | | | | | | | | | | | | | | | overly conservative. It was concerned about cases where it would prohibit folding simple [r, c] addressing modes. e.g. ldr r0, [r2] ldr r1, [r2, #4] => ldr r0, [r2], #4 ldr r1, [r2] Change the logic to look for such cases which allows it to form indexed memory ops more aggressively. rdar://10674430 llvm-svn: 148086
* Fix off-by-one error.Bill Wendling2012-01-131-1/+1
| | | | llvm-svn: 148077
* Implement proper ObjC ARC objc_retainBlock "escape" analysis, so thatDan Gohman2012-01-131-45/+63
| | | | | | | | the optimizer doesn't eliminate objc_retainBlock calls which are needed for their side effect of copying blocks onto the heap. This implements rdar://10361249. llvm-svn: 148076
* Added MVT::v2f16Pete Cooper2012-01-121-0/+2
| | | | llvm-svn: 148067
* Revert accidental commit.Bill Wendling2012-01-121-65/+0
| | | | llvm-svn: 148065
* Fix the code that was WRONG.Bill Wendling2012-01-122-13/+71
| | | | | | | The registers are placed into the saved registers list in the reverse order, which is why the original loop was written to loop backwards. llvm-svn: 148064
* Added FPOW, FEXP, FLOG to PromoteNode so that custom actions can be set to ↵Pete Cooper2012-01-121-0/+18
| | | | | | | | Promote for those operations. Sorry, no test case yet llvm-svn: 148050
* Fixed a bug in LowerVECTOR_SHUFFLE caused assertion failureElena Demikhovsky2012-01-121-1/+5
| | | | | | | lc: X86ISelLowering.cpp:6480: llvm::SDValue llvm::X86TargetLowering::LowerVECTOR_SHUFFLE(llvm::SDValue, llvm::SelectionDAG&) const: Assertion `V1.getOpcode() != ISD::UNDEF&& "Op 1 of shuffle should not be undef"' failed. Added a test. llvm-svn: 148044
* When hoisting common code, watch out for uses which are marked "kill". If theEvan Cheng2012-01-121-0/+5
| | | | | | | | | | | killed registers are needed below the insertion point, then unset the kill marker. Sorry I'm not able to find a reduced test case. rdar://10660944 llvm-svn: 148043
* Support segmented stacks on 64-bit FreeBSD.Rafael Espindola2012-01-121-2/+8
| | | | | | | This patch uses tcb_spare field in the tcb structure to store info. Patch by Jyun-Yan You. llvm-svn: 148041
* Support segmented stacks on win32.Rafael Espindola2012-01-121-7/+17
| | | | | | | Uses the pvArbitrary slot of the TIB, which is reserved for applications. We only support frames with a static size. llvm-svn: 148040
* Allow targets to select source order pre-RA scheduler.Evan Cheng2012-01-121-1/+2
| | | | llvm-svn: 148033
* Rename X86ATTAsmParser -> X86AsmParserDevang Patel2012-01-122-19/+18
| | | | | | We are using one parser to parse att as well as intel style syntax. llvm-svn: 148032
* Make SplitAnalysis::UseSlots private.Jakob Stoklund Olesen2012-01-122-6/+10
| | | | llvm-svn: 148031
* After Jakob's r147938 exception handling on i386 was completely broken.Benjamin Kramer2012-01-121-0/+7
| | | | | | | | | Restore the (obviously wrong) behavior from before r147938 without relying on undefined behavior. Add a fat FIXME note. This should fix nightly tester failures. llvm-svn: 148030
* Fix a bug in the AVX 256-bit shuffle code in cases where the splat element ↵Nadav Rotem2012-01-121-1/+1
| | | | | | | | is on the boundary of two 128-bit vectors. The attached testcase was stuck in an endless loop. llvm-svn: 148027
* X86: Generalize the x << (y & const) optimization to also catch masks with ↵Benjamin Kramer2012-01-121-21/+25
| | | | | | more set bits set than 31 or 63. llvm-svn: 148024
* Add predicate method check match memory operand size, if available.Devang Patel2012-01-122-17/+96
| | | | | | In att style asm syntax memory operand size is derived from suffix attached with mnemonic. In intel style asm syntax it is part of memory operand hence predicate method check is required to select appropriate instruction. llvm-svn: 148006
* A DenseMap of a std::map isn't a very good idea because the "grow()" method willBill Wendling2012-01-121-2/+2
| | | | | | | need to make a deep copy of each of the std::maps. Use a std::map of the std::map instead. This improves the compile time of sqlite3 by ~2%. llvm-svn: 148003
* Add intel style operand parser skeleton. Devang Patel2012-01-121-1/+97
| | | | | | This is a work in progress. llvm-svn: 148002
* Switch all of the uses of my InsertDAGNode helper to follow the exactChandler Carruth2012-01-121-8/+22
| | | | | | | | | | | | | | | | | | | | same pattern. We already had this pattern is a few places, but others tried to make a rough approximation of an actual DAG structure. As not everywhere went to this trouble, nothing could rely on this being done. In fact, I've checked all references to these node Ids, and the ones that are using the topo-sort properties are actually satisfied with a strict-weak-ordering. The requirement appears to be that Use >= Def. I've added a big blurb of comments to this bit of the transform to clarify why the order is so important for the next reader of the code. I'm starting with this change as it is very small, and trivially reverted if something breaks or the >= above really does need to be >. If that proves the case, we can hide the problem by reverting this patch, but the problem exists elsewhere as well, and so a more comprehensive solution will be needed. llvm-svn: 148001
* Revert r147978. A DenseMap's iterators may become invalidated here.Bill Wendling2012-01-111-1/+2
| | | | llvm-svn: 147980
* Make data structures private.Jakob Stoklund Olesen2012-01-113-11/+17
| | | | llvm-svn: 147979
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