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* CodeView symbol dumper: use symbolic names for registersHans Wennborg2017-10-021-4/+7
| | | | | | https://reviews.llvm.org/D38469 llvm-svn: 314690
* Eliminate ftrunc if source is know to be roundedStanislav Mekhanoshin2017-10-021-0/+13
| | | | | | Differential Revision: https://reviews.llvm.org/D38421 llvm-svn: 314688
* [dwarfdump] Add -show-formJonas Devlieghere2017-10-021-1/+1
| | | | | | | | | This enables printing of DWARF form types after the DWARF attribute types. Differential revision: https://reviews.llvm.org/D38459 llvm-svn: 314685
* use range-for-loops; NFCISanjay Patel2017-10-021-9/+8
| | | | llvm-svn: 314676
* [AsmParser] Support GAS's .print directiveCoby Tayree2017-10-021-0/+18
| | | | | | Differential Revision: https://reviews.llvm.org/D38448 llvm-svn: 314674
* remove duplicate comments, reposition related functions; NFCSanjay Patel2017-10-021-56/+49
| | | | llvm-svn: 314669
* [X86][SSE] Fix -Wsign-compare problems introduced in r314658Bjorn Pettersson2017-10-021-4/+4
| | | | | | | | | | | The refactoring in "[X86][SSE] Add createPackShuffleMask helper function. NFCI." resulted in warning when compiling the code (seen in build bots). This patch restores some types from int to unsigned to avoid those warnings. llvm-svn: 314667
* [Debug info] Handle endianness when moving debug info for split integer valuesBjorn Pettersson2017-10-021-2/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | Summary: Take the target's endianness into account when splitting the debug information in DAGTypeLegalizer::SetExpandedInteger. This patch fixes so that, for big-endian targets, the fragment expression corresponding to the high part of a split integer value is placed at offset 0, in order to correctly represent the memory address order. I have attached a PPC32 reproducer where the resulting DWARF pieces for a 64-bit integer were incorrectly reversed. Patch by: dstenb Reviewers: JDevlieghere, aprantl, dblaikie Reviewed By: JDevlieghere, aprantl, dblaikie Subscribers: nemanjai Differential Revision: https://reviews.llvm.org/D38172 llvm-svn: 314666
* [X86][SSE] Add createPackShuffleMask helper function. NFCI.Simon Pilgrim2017-10-021-10/+19
| | | | llvm-svn: 314658
* [X86][SSE] matchBinaryVectorShuffle - add support for different src/dst ↵Simon Pilgrim2017-10-021-12/+12
| | | | | | | | value shuffle types Preparation for support for combining to PACKSS/PACKUS llvm-svn: 314656
* [PowerPC] support ZERO_EXTEND in tryBitPermutationHiroshi Inoue2017-10-021-17/+64
| | | | | | | | | | | | | | | | | | | This patch add a support of ISD::ZERO_EXTEND in PPCDAGToDAGISel::tryBitPermutation to increase the opportunity to use rotate-and-mask by reordering ZEXT and ANDI. Since tryBitPermutation stops analyzing nodes if it hits a ZEXT node while traversing SDNodes, we want to avoid ZEXT between two nodes that can be folded into a rotate-and-mask instruction. For example, we allow these nodes t9: i32 = add t7, Constant:i32<1> t11: i32 = and t9, Constant:i32<255> t12: i64 = zero_extend t11 t14: i64 = shl t12, Constant:i64<2> to be folded into a rotate-and-mask instruction. Such case often happens in array accesses with logical AND operation in the index, e.g. array[i & 0xFF]; Differential Revision: https://reviews.llvm.org/D37514 llvm-svn: 314655
* Fix typo in comment. NFCI.Simon Pilgrim2017-10-021-1/+1
| | | | llvm-svn: 314653
* [X86] Cleanup uses of computeKnownBits by using MaskedValueIsZero helper ↵Simon Pilgrim2017-10-021-6/+3
| | | | | | instead. NFCI. llvm-svn: 314652
* [X86][LLVM]Expanding Supports lowerInterleaved{store|load}() in ↵Michael Zuckerman2017-10-021-109/+169
| | | | | | | | | | | | | | | | | | | X86InterleavedAccess (VF64 stride 3-4) I continue to support different VF interleaved and in this pass for this patch, I added the vf64 stride3 support for both load and store. I also added support fot the stride4 store. Reviewers: 1. zvi 2. dorit 3. igorb 4. guyblank Differential Revision: https://reviews.llvm.org/D37687 Change-Id: I3d238efedf217d1768b348d710de1efa2f19d27b llvm-svn: 314651
* [X86] Fix copy pasto in X86FastISel::fastEmitInst_rrrr.Craig Topper2017-10-021-1/+1
| | | | | | The 4th operand was not being constrained and the third operand was being constrained twice. llvm-svn: 314648
* [X86] Use a bool flag instead of assigning an unsigned to two different ↵Craig Topper2017-10-021-9/+8
| | | | | | values that we only use in an equality comparison. llvm-svn: 314647
* [X86] Use _NOREX MOVZX instructions for some patterns even in 32-bit mode.Craig Topper2017-10-021-32/+6
| | | | | | This unifies the patterns between both modes. This should be effectively NFC since all the available registers in 32-bit mode statisfy this constraint. llvm-svn: 314643
* [Hexagon] Check vector elements for equivalence in the ↵Ron Lieberman2017-10-021-1/+16
| | | | | | | | | | | | | HexagonVectorLoopCarriedReuse pass If the two instructions being compared for equivalence have corresponding operands that are integer constants, then check their values to determine equivalence. Patch by Suyog Sarda! llvm-svn: 314642
* [Hexagon] Patch to Extract i1 element from vector of i1Ron Lieberman2017-10-021-1/+7
| | | | | | | This patch extracts 1 element from vector consisting of elements of size 1 bit at given index. llvm-svn: 314641
* [InstCombine] Use APInt for all the math in foldICmpDivConstantCraig Topper2017-10-011-95/+46
| | | | | | | | | | | | | | Summary: This currently uses ConstantExpr to do its math, but as noted in a TODO it can all be done directly on APInt. Reviewers: spatel, majnemer Reviewed By: majnemer Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D38440 llvm-svn: 314640
* [X86] Change register&memory TEST instructions from MRMSrcMem to MRMDstMemCraig Topper2017-10-018-34/+33
| | | | | | | | | | | | | | | | | | | Summary: Intel documentation shows the memory operand as the first operand. But we currently treat it as the second operand. Conceptually the order doesn't matter since it doesn't write memory. We have aliases to parse with the operands in either order and the isel matching is commutable. For the register&register form order does matter for the assembly parser. PR22995 was previously filed and fixed by changing the register&register form from MRMSrcReg to MRMDestReg to match gas. Ideally the memory form should match by using MRMDestMem. I believe this supercedes D38025 which was trying to switch the register&register form back to pre-PR22995. Reviewers: aymanmus, RKSimon, zvi Reviewed By: aymanmus Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D38120 llvm-svn: 314639
* [X86] Remove a couple unnecessary COPY_TO_REGCLASS from some output patterns ↵Craig Topper2017-10-011-9/+7
| | | | | | where the instruction already produces the correct register class. llvm-svn: 314638
* [X86][SSE] Add faux shuffle combining support for PACKUSSimon Pilgrim2017-10-011-4/+15
| | | | llvm-svn: 314631
* [X86][SSE] Improve shuffle combining of PACKSS instructions.Simon Pilgrim2017-10-011-6/+24
| | | | | | Support unary packing and fix the faux shuffle mask for vectors larger than 128 bits. llvm-svn: 314629
* [x86] formatting; NFCSanjay Patel2017-10-011-4/+2
| | | | llvm-svn: 314627
* Revert r314579: "Recommi r314561 after fixing over-debug assertion".Daniel Jasper2017-10-012-225/+0
| | | | | | | | | | | | And follow-up r314585. Leads to segfaults. I'll forward reproduction instructions to the patch author. Also, for a recommit, still add the original patch description. Otherwise, it becomes really tedious to find out what a patch actually does. The fact that it is a recommit with a fix is somewhat secondary. llvm-svn: 314622
* Separate the logic when handling indirect calls in SamplePGO ThinLTO compile ↵Dehao Chen2017-10-012-13/+28
| | | | | | | | | | | | | | | | phase and other phases. Summary: In SamplePGO ThinLTO compile phase, we will not invoke ICP as it may introduce confusion to the 2nd annotation. This patch extracted that logic and makes it clearer before profile annotation. In the mean time, we need to make function importing process both inlined callsites as well as not promoted indirect callsites. Reviewers: tejohnson Reviewed By: tejohnson Subscribers: sanjoy, mehdi_amini, llvm-commits, inglorion Differential Revision: https://reviews.llvm.org/D38094 llvm-svn: 314619
* Revert "Fix typo [NFC]"Xin Tong2017-10-011-6/+3
| | | | | | | | This reverts commit e60b5028619be1c81bd039d63a0627dac32d38f9. Incorrectly include changes that are not typo fix. llvm-svn: 314614
* Fix typo [NFC]Xin Tong2017-10-011-3/+6
| | | | llvm-svn: 314613
* NewGVN: Fix PR 34473, by not using ExactlyEqualsExpression for findingDaniel Berlin2017-09-301-6/+6
| | | | | | phi of ops users. llvm-svn: 314612
* NewGVN: Evaluate phi of ops expressions before creating phi nodeDaniel Berlin2017-09-301-48/+72
| | | | llvm-svn: 314611
* NewGVN: Allow dependent PHI of opsDaniel Berlin2017-09-301-57/+100
| | | | llvm-svn: 314610
* NewGVN: Make OpIsSafeForPhiOfOps non-recursiveDaniel Berlin2017-09-301-7/+38
| | | | llvm-svn: 314609
* Refactor the SamplePGO profile annotation logic to extract ↵Dehao Chen2017-09-301-58/+65
| | | | | | inlineCallInstruction. (NFC) llvm-svn: 314601
* [X86][SSE] Fold (VSRAI (VSHLI X, C1), C1) --> X iff NumSignBits(X) > C1Simon Pilgrim2017-09-301-0/+9
| | | | | | Remove sign extend in register style pattern if the sign is already extended enough llvm-svn: 314599
* [AVX-512] Add patterns to make fp compare instructions commutable during isel.Craig Topper2017-09-302-1/+90
| | | | llvm-svn: 314598
* Code refactoring for the interleaved code <NFC>Michael Zuckerman2017-09-301-28/+18
| | | | | Change-Id: I7831c9febad8e14278a5bc87584a0053dc837be1 llvm-svn: 314596
* Revert r314435: "[JumpThreading] Preserve DT and LVI across the pass"Daniel Jasper2017-09-303-253/+65
| | | | | | | Causes a segfault on a builtbot (and in our internal bootstrapping of Clang). See Eli's response on the commit thread. llvm-svn: 314589
* Fix buildbot failure -- tighten type check for matching phiXinliang David Li2017-09-301-1/+1
| | | | llvm-svn: 314585
* [X86] Support v64i8 mulhu/mulhsCraig Topper2017-09-301-1/+9
| | | | | | | | Implemented by splitting into two v32i8 mulhu/mulhs and concatenating the results. Differential Revision: https://reviews.llvm.org/D38307 llvm-svn: 314584
* Recommi r314561 after fixing over-debug assertionXinliang David Li2017-09-302-0/+225
| | | | llvm-svn: 314579
* [AMDGPU] Set fast-math flags on functions given the optionsStanislav Mekhanoshin2017-09-293-7/+36
| | | | | | | | | | | | | | | | We have a single library build without relaxation options. When inlined library functions remove fast math attributes from the functions they are integrated into. This patch sets relaxation attributes on the functions after linking provided corresponding relaxation options are given. Math instructions inside the inlined functions remain to have no fast flags, but inlining does not prevent fast math transformations of a surrounding caller code anymore. Differential Revision: https://reviews.llvm.org/D38325 llvm-svn: 314568
* CodeGen: Fix pointer info in expandUnalignedLoad/StoreYaxun Liu2017-09-291-12/+21
| | | | | | | | | | | | Currently expandUnalignedLoad/Store uses place holder pointer info for temporary memory operand in stack, which does not have correct address space. This causes unaligned private double16 load/store to be lowered to flat_load instead of buffer_load for amdgcn target. This fixes failures of OpenCL conformance test basic/vload_private/vstore_private on target amdgcn---amdgizcl. Differential Revision: https://reviews.llvm.org/D35361 llvm-svn: 314566
* Revert 314561 due to debug build assertion failureXinliang David Li2017-09-292-223/+0
| | | | llvm-svn: 314563
* Eliminate PHI (int typed) which has only one use by intptrXinliang David Li2017-09-292-0/+223
| | | | | | | | | | This patch will eliminate redundant intptr/ptrtoint that pessimizes analyses such as SCEV, AA and will make optimization passes such as auto-vectorization more powerful. Differential revision: http://reviews.llvm.org/D37832 llvm-svn: 314561
* Revert "Use the basic cost if a GEP is not used as addressing mode"Alex Shlyapnikov2017-09-293-7/+2
| | | | | | | | | | | | | | | | | | | | | | | This reverts commit r314517. This commit crashes sanitizer bots, for example: http://lab.llvm.org:8011/builders/sanitizer-x86_64-linux/builds/4167 Stack snippet: ... /mnt/b/sanitizer-buildbot1/sanitizer-x86_64-linux/build/llvm/include/llvm/Support/Casting.h:255:0 llvm::TargetTransformInfoImplCRTPBase<llvm::X86TTIImpl>::getGEPCost(llvm::GEPOperator const*, llvm::ArrayRef<llvm::Value const*>) /mnt/b/sanitizer-buildbot1/sanitizer-x86_64-linux/build/llvm/include/llvm/Analysis/TargetTransformInfoImpl.h:742:0 llvm::TargetTransformInfoImplCRTPBase<llvm::X86TTIImpl>::getUserCost(llvm::User const*, llvm::ArrayRef<llvm::Value const*>) /mnt/b/sanitizer-buildbot1/sanitizer-x86_64-linux/build/llvm/include/llvm/Analysis/TargetTransformInfoImpl.h:782:0 /mnt/b/sanitizer-buildbot1/sanitizer-x86_64-linux/build/llvm/lib/Analysis/TargetTransformInfo.cpp:116:0 /mnt/b/sanitizer-buildbot1/sanitizer-x86_64-linux/build/llvm/include/llvm/ADT/SmallVector.h:116:0 /mnt/b/sanitizer-buildbot1/sanitizer-x86_64-linux/build/llvm/include/llvm/ADT/SmallVector.h:343:0 /mnt/b/sanitizer-buildbot1/sanitizer-x86_64-linux/build/llvm/include/llvm/ADT/SmallVector.h:864:0 /mnt/b/sanitizer-buildbot1/sanitizer-x86_64-linux/build/llvm/include/llvm/Analysis/TargetTransformInfo.h:285:0 ... llvm-svn: 314560
* [CodeGen] Fix some Clang-tidy modernize-use-using and Include What You Use ↵Eugene Zelenko2017-09-2910-137/+204
| | | | | | warnings; other minor fixes (NFC). llvm-svn: 314559
* [LV] Use correct insertion point when type shrinking reductionsMatthew Simpson2017-09-291-1/+2
| | | | | | | | | | | | | When type shrinking reductions, we should insert the truncations and extends at the end of the loop latch block. Previously, these instructions were inserted at the end of the loop header block. The difference is only a problem for loops with predicated instructions (e.g., conditional stores and instructions that may divide by zero). For these instructions, we create new basic blocks inside the vectorized loop, which cause the loop header and latch to no longer be the same block. This should fix PR34687. Reference: https://bugs.llvm.org/show_bug.cgi?id=34687 llvm-svn: 314542
* [WebAssembly] Allow each data segment to specify its own alignmentSam Clegg2017-09-293-23/+31
| | | | | | | | | Also, add a flags field as we will almost certainly be needing that soon too. Differential Revision: https://reviews.llvm.org/D38296 llvm-svn: 314534
* [SimplifyIndVar] Do not fail when we constant fold an IV user to ↵Hongbin Zheng2017-09-291-10/+17
| | | | | | | | | | ConstantPointerNull The type of a SCEVConstant may not match the corresponding LLVM Value. In this case, we skip the constant folding for now. TODO: Replace ConstantInt Zero by ConstantPointerNull llvm-svn: 314531
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