summaryrefslogtreecommitdiffstats
path: root/llvm/lib
Commit message (Collapse)AuthorAgeFilesLines
...
* fall back to explicit list of allowed linkages when instrumenting globals in ↵Kostya Serebryany2011-11-171-2/+5
| | | | | | asan; add a test check that asan does not touch linkonce_odr llvm-svn: 144933
* Add TODO comment.Chad Rosier2011-11-171-0/+2
| | | | llvm-svn: 144920
* Fix SSE/AVX integer comparison patterns to understand that all integer ↵Craig Topper2011-11-171-24/+42
| | | | | | vector loads are promoted to i64 vector loads so patterns need a bitconvert. Also slightly simplify the AVX2 variable shift patterns by using the predefined bitconvert pattern fragments. llvm-svn: 144896
* Dead code.Chad Rosier2011-11-171-14/+0
| | | | llvm-svn: 144888
* When fast iseling a GEP, accumulate the offset rather than emitting a series ofChad Rosier2011-11-171-11/+35
| | | | | | | | | | | | | ADDs. MaxOffs is used as a threshold to limit the size of the offset. Tradeoffs being: (1) If we can't materialize the large constant then we'll cause fast-isel to bail. (2) Too large of an offset can't be directly encoded in the ADD resulting in a MOV+ADD. Generally not a bad thing because otherwise we would have had ADD+ADD, but on Thumb this turns into a MOVS+MOVT+ADD. Working on a fix for that. (3) Conversely, too low of a threshold we'll miss opportunities to coalesce ADDs. rdar://10412592 llvm-svn: 144886
* Remove seemingly unnecessary duplicate VROUND definitions.Craig Topper2011-11-171-80/+4
| | | | llvm-svn: 144885
* Add support for custom names for library functions in TargetLibraryInfo. ↵Eli Friedman2011-11-173-13/+50
| | | | | | | | | | Add a custom name for fwrite and fputs on x86-32 OSX. Make SimplifyLibCalls honor the custom names for fwrite and fputs. Fixes <rdar://problem/9815881>. llvm-svn: 144876
* Don't unconditionally set the kill flag.Chad Rosier2011-11-171-1/+1
| | | | | | rdar://10456186 llvm-svn: 144872
* Turn on vzeroupper insertion on call boundaries for AVX; it works as far as ↵Eli Friedman2011-11-171-1/+1
| | | | | | I know, and I'd like to see wider testing. llvm-svn: 144867
* Make sure to replace the chain properly when DAGCombining a ↵Eli Friedman2011-11-161-4/+17
| | | | | | LOAD+EXTRACT_VECTOR_ELT into a single LOAD. Fixes PR10747/PR11393. llvm-svn: 144863
* Object/COFF: Support common symbols.Michael J. Spencer2011-11-161-1/+3
| | | | llvm-svn: 144861
* Generalize the fixup info for ARM mode.Jim Grosbach2011-11-161-2/+2
| | | | | | | We don't (yet) have the granularity in the fixups to be specific about which bitranges are affected. That's a future cleanup, but we're not there yet. llvm-svn: 144852
* Lower 64-bit constant pool node.Akira Hatanaka2011-11-161-8/+12
| | | | llvm-svn: 144849
* Lower 64-bit block address.Akira Hatanaka2011-11-161-9/+11
| | | | llvm-svn: 144847
* Fix encoding of NOP used for padding in ARM mode .align.Jim Grosbach2011-11-161-1/+1
| | | | llvm-svn: 144842
* Add patterns for 64-bit tglobaladdr, tblockaddress, tjumptable and tconstpoolAkira Hatanaka2011-11-162-7/+24
| | | | | | nodes. llvm-svn: 144841
* 64-bit jump register instruction.Akira Hatanaka2011-11-162-6/+7
| | | | llvm-svn: 144840
* Another missing X86ISD::MOVLPD pattern. rdar://10450317Evan Cheng2011-11-161-0/+2
| | | | llvm-svn: 144839
* ARM assembly parsing for shifted register operands for MOV instruction.Jim Grosbach2011-11-161-0/+2
| | | | llvm-svn: 144837
* Clean up debug printing of ARM shifted operands.Jim Grosbach2011-11-161-9/+6
| | | | llvm-svn: 144836
* Add fast-isel stats to determine who's doing all the work, the Chad Rosier2011-11-161-0/+7
| | | | | | target-independent selector or the target-specific selector. llvm-svn: 144833
* Fix the stats collection for fast-isel. The failed count was only accountingChad Rosier2011-11-161-5/+18
| | | | | | | | | for a single miss and not all predecessor instructions that get selected by the selection DAG instruction selector. This is still not exact (e.g., over states misses when folded/dead instructions are present), but it is a step in the right direction. llvm-svn: 144832
* ARM assmebly two operand forms for LSR, ASR, LSL, ROR register.Jim Grosbach2011-11-161-0/+12
| | | | llvm-svn: 144814
* ARM assembly parsing for RRX mnemonic.Jim Grosbach2011-11-162-1/+16
| | | | | | rdar://9704684 llvm-svn: 144812
* Added missing comment about new custom lowering of DEC64Pete Cooper2011-11-161-0/+12
| | | | llvm-svn: 144811
* Disable expensive two-address optimizations at -O0. rdar://10453055Evan Cheng2011-11-161-0/+8
| | | | llvm-svn: 144806
* Check to make sure we can select the instruction before trying to put theChad Rosier2011-11-161-6/+6
| | | | | | operands into a register. Otherwise, we may materialize dead code. llvm-svn: 144805
* Disable the assertion again. Looks like fastisel is still generating bad ↵Evan Cheng2011-11-161-1/+2
| | | | | | kill markers. llvm-svn: 144804
* ARM mode aliases for bitwise instructions w/ register operands.Jim Grosbach2011-11-162-0/+38
| | | | | | rdar://9704684 llvm-svn: 144803
* Fix tablegen warning: hasSideEffects is inferred for eh_sjlj_dispatchsetup.Bob Wilson2011-11-161-1/+1
| | | | llvm-svn: 144798
* lib/Target/ARM/CMakeLists.txt: Disable optimization in ARMISelLowering.cpp ↵NAKAMURA Takumi2011-11-161-2/+2
| | | | | | also on MSC15(aka VS9). Seems miscompiled. llvm-svn: 144794
* Sink codegen optimization level into MCCodeGenInfo along side relocation modelEvan Cheng2011-11-1640-253/+277
| | | | | | | and code model. This eliminates the need to pass OptLevel flag all over the place and makes it possible for any codegen pass to use this information. llvm-svn: 144788
* Record landing pads with a SmallSetVector to avoid multiple entries.Bob Wilson2011-11-161-3/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There may be many invokes that share one landing pad, and the previous code would record the landing pad once for each invoke. Besides the wasted effort, a pair of volatile loads gets inserted every time the landing pad is processed. The rest of the code can get optimized away when a landing pad is processed repeatedly, but the volatile loads remain, resulting in code like: LBB35_18: Ltmp483: ldr r2, [r7, #-72] ldr r2, [r7, #-68] ldr r2, [r7, #-72] ldr r2, [r7, #-68] ldr r2, [r7, #-72] ldr r2, [r7, #-68] ldr r2, [r7, #-72] ldr r2, [r7, #-68] ldr r2, [r7, #-72] ldr r2, [r7, #-68] ldr r2, [r7, #-72] ldr r2, [r7, #-68] ldr r2, [r7, #-72] ldr r2, [r7, #-68] ldr r2, [r7, #-72] ldr r2, [r7, #-68] ldr r4, [r7, #-72] ldr r2, [r7, #-68] llvm-svn: 144787
* Fix the execution domain on a bunch of SSE/AVX instructions.Craig Topper2011-11-161-91/+157
| | | | llvm-svn: 144784
* Update the SP in the SjLj jmpbuf whenever it changes. <rdar://problem/10444602>Bob Wilson2011-11-161-3/+21
| | | | | | | This same basic code was in the older version of the SjLj exception handling, but it was removed in the recent revisions to that code. It needs to be there. llvm-svn: 144782
* Fix ARM SjLj-EH dispatch setup code. <rdar://problem/10444602>Bob Wilson2011-11-164-74/+4
| | | | | | | | | | | | | | | | | The EmitBasePointerRecalculation function has 2 problems, one minor and one fatal. The minor problem is that it inserts the code at the setjmp instead of in the dispatch block. The fatal problem is that at the point where this code runs, we don't know whether there will be a base pointer, so the entire function is a no-op. The base pointer recalculation needs to be handled as it was before, by inserting a pseudo instruction that gets expanded late. Most of the support for the old approach is still here, but it no longer has any connection to the eh_sjlj_dispatchsetup intrinsic. Clean up the parts related to the intrinsic and just generate the pseudo instruction directly. llvm-svn: 144781
* Remove code to enable execution dependency fix pass on VR256. VR128 is ↵Craig Topper2011-11-161-9/+3
| | | | | | sufficient after r144636. llvm-svn: 144777
* Revert r144568 now that r144730 has fixed the fast-isel kill marker bug.Evan Cheng2011-11-161-2/+1
| | | | llvm-svn: 144776
* Merge isObjectPointerWithTrustworthySize with getPointerSize. Use it whenNick Lewycky2011-11-161-30/+20
| | | | | | looking at the size of the pointee. Fixes PR11390! llvm-svn: 144773
* If the 2addr instruction has other kills, don't move it below any other uses ↵Evan Cheng2011-11-161-2/+7
| | | | | | since we don't want to extend other live ranges. llvm-svn: 144772
* RescheduleKillAboveMI() must backtrack to before the rescheduled DBG_VALUE ↵Evan Cheng2011-11-161-1/+1
| | | | | | instructions. rdar://10451185 llvm-svn: 144771
* Process all uses first before defs to accurately capture register liveness. ↵Evan Cheng2011-11-161-7/+13
| | | | | | rdar://10449480 llvm-svn: 144770
* CONCAT_VECTORS can have more than two operands. PR11389.Eli Friedman2011-11-161-22/+12
| | | | llvm-svn: 144768
* Add a couple asserts so it will be easier to debug if we accidentally pass ↵Eli Friedman2011-11-161-0/+4
| | | | | | indexed loads/stores to the legalizer. llvm-svn: 144767
* AddressSanitizer, first commit (compiler module only)Kostya Serebryany2011-11-163-0/+967
| | | | llvm-svn: 144758
* test commit to verify that commit access works (added blank line)Kostya Serebryany2011-11-161-0/+1
| | | | llvm-svn: 144748
* Rename MVT::untyped to MVT::Untyped to match similar nomenclature.Owen Anderson2011-11-163-4/+4
| | | | llvm-svn: 144747
* Fix SCEV overly optimistic back edge taken count for multi-exit loops.Andrew Trick2011-11-161-9/+22
| | | | | | Fixes PR11375: Different results for 'clang++ huh.cpp'... llvm-svn: 144746
* Add FIXME comment.Chad Rosier2011-11-161-0/+2
| | | | llvm-svn: 144743
* Enable -widen-vmovs by default.Jakob Stoklund Olesen2011-11-151-1/+1
| | | | | | | | | | | This will widen 32-bit register vmov instructions to 64-bit when possible. The 64-bit vmovd instructions can then be translated to NEON vorr instructions by the execution dependency fix pass. The copies are only widened if they are marked as clobbering the whole D-register. llvm-svn: 144734
OpenPOWER on IntegriCloud