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* [WebAssembly] clang-format (NFC)Heejin Ahn2018-09-0542-632/+734
| | | | | | | | | | | | Summary: This patch runs clang-format on all wasm-only files. Reviewers: aardappel, dschuff, sunfish, tlively Subscribers: MatzeB, sbc100, jgravelle-google, llvm-commits Differential Revision: https://reviews.llvm.org/D51447 llvm-svn: 341439
* [Windows] Convert from UTF-8 to UTF-16 when writing to a Windows consoleReid Kleckner2018-09-053-25/+86
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: Calling WriteConsoleW is the most reliable way to print Unicode characters to a Windows console. If binary data gets printed to the console, attempting to re-encode it shouldn't be a problem, since garbage in can produce garbage out. This breaks printing strings in the local codepage, which WriteConsoleA knows how to handle. For example, this can happen when user source code is encoded with the local codepage, and an LLVM tool quotes it while emitting a caret diagnostic. This is unfortunate, but well-behaved tools should validate that their input is UTF-8 and escape non-UTF-8 characters before sending them to raw_fd_ostream. Clang already does this, but not all LLVM tools do this. One drawback to the current implementation is printing a string a byte at a time doesn't work. Consider this LLVM code: for (char C : MyStr) outs() << C; Because outs() is now unbuffered, we wil try to convert each byte to UTF-16, which will fail. However, this already didn't work, so I think we may as well update callers that do that as we find them to print complete portions of strings. You can see a real example of this in my patch to SourceMgr.cpp Fixes PR38669 and PR36267. Reviewers: zturner, efriedma Subscribers: llvm-commits, hiraditya Differential Revision: https://reviews.llvm.org/D51558 llvm-svn: 341433
* [InstCombine] fix xor-or-xor fold to check uses and handle commutesSanjay Patel2018-09-041-32/+21
| | | | | | | | | | | | I'm probably missing some way to use m_Deferred to remove the code duplication, but that can be a follow-up. The improvement in demand_shrink_nsw.ll is an example of missing the fold because the pattern matching was deficient. I didn't try to follow the bits in that test, but Alive says it's correct: https://rise4fun.com/Alive/ugc llvm-svn: 341426
* [WebAssembly] Fixed stale assert message in WebAssemblyMCInstLowerWouter van Oortmerssen2018-09-041-1/+1
| | | | llvm-svn: 341423
* [ThinLTO] Fix memory corruption in ThinLTOCodeGenerator when CodeGenOnly was ↵Steven Wu2018-09-041-9/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | specified Summary: Issue occurs when doing ThinLTO with CodeGenOnly flag. TMBuilder.TheTriple is assigned to by multiple threads in an unsafe way resulting in double-free of std::string memory. Pseudocode: if (CodeGenOnly) { // Perform only parallel codegen and return. ThreadPool Pool; int count = 0; for (auto &ModuleBuffer : Modules) { Pool.async([&](int count) { ... /// Now call OutputBuffer = codegen(*TheModule); /// Which turns into initTMBuilder(moduleTMBuilder, Triple(TheModule.getTargetTriple())); /// Which turns into TMBuilder.TheTriple = std::move(TheTriple); // std::string = "....." /// So, basically std::string assignment to same string on multiple threads = memory corruption } return; } Patch by Alex Borcan Reviewers: llvm-commits, steven_wu Reviewed By: steven_wu Subscribers: mehdi_amini, inglorion, eraman, steven_wu, dexonsmith, llvm-commits Differential Revision: https://reviews.llvm.org/D51651 llvm-svn: 341422
* Revert "Revert r341269: [Constant Hoisting] Hoisting Constant GEP Expressions"Zhaoshi Zheng2018-09-041-37/+137
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Reland r341269. Use std::stable_sort when sorting constant condidates. Reverting commit, r341365: Revert r341269: [Constant Hoisting] Hoisting Constant GEP Expressions One of the tests is failing 50% of the time when expensive checks are enabled. Not sure how deep the problem is so just reverting while the author can investigate so that the bots stop repeatedly failing and blaming things incorrectly. Will respond with details on the original commit. Original commit, r341269: [Constant Hoisting] Hoisting Constant GEP Expressions Leverage existing logic in constant hoisting pass to transform constant GEP expressions sharing the same base global variable. Multi-dimensional GEPs are rewritten into single-dimensional GEPs. https://reviews.llvm.org/D51396 Differential Revision: https://reviews.llvm.org/D51654 llvm-svn: 341417
* [LV] First order recurrence phis should not be treated as uniformAnna Thomas2018-09-041-0/+5
| | | | | | | | | | | | | | This is fix for PR38786. First order recurrence phis were incorrectly treated as uniform, which caused them to be vectorized as uniform instructions. Patch by Ayal Zaks and Orivej Desh! Reviewed by: Anna Differential Revision: https://reviews.llvm.org/D51639 llvm-svn: 341416
* [AMDGPU] Legalize VGPR Rsrc operands for MUBUF instructionsScott Linder2018-09-043-67/+232
| | | | | | | | | Emit a waterfall loop in the general case for a potentially-divergent Rsrc operand. When practical, avoid this by using Addr64 instructions. Differential Revision: https://reviews.llvm.org/D50982 llvm-svn: 341413
* Fix a memory leak after rL341386.Hiroshi Yamauchi2018-09-041-1/+1
| | | | | | | | | | | | Reviewers: davidxl Reviewed By: davidxl Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D51658 llvm-svn: 341412
* [WebAssembly][NFC] Fix formatting and testsThomas Lively2018-09-041-1/+1
| | | | | | | | | | | | Summary: Small fixes Reviewers: aheejin, dschuff Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D51656 llvm-svn: 341411
* [InstCombine] make ((X & C) ^ C) form consistent for vectorsSanjay Patel2018-09-041-4/+2
| | | | | | It would be better to create a 'not' here, but that's not possible yet. llvm-svn: 341410
* [Hexagon] Don't packetize new-value stores with any other storesKrzysztof Parzyszek2018-09-041-0/+7
| | | | llvm-svn: 341409
* [NFC] Improve clarity in emitInstrCountChangedRemarkJessica Paquette2018-09-041-1/+4
| | | | | | | | | Add a "CouldOnlyImpactOneFunction" bool that's true when we pass in a function. Just cleaning up a little bit, since I'm going to add in the per-function remarks soon from D51467. llvm-svn: 341407
* [InstCombine] simplify code for xor folds; NFCISanjay Patel2018-09-041-40/+23
| | | | | | | | | This is just a cleanup step. The TODO comments show what is wrong with the 'and' version of the fold. Fixing this should be part of recommitting: rL300977 llvm-svn: 341405
* [MinGW] Move code for indicating "potentially not DSO local" into ↵Martin Storsjo2018-09-044-25/+25
| | | | | | | | | | | | | | | shouldAssumeDSOLocal. NFC. On Windows, if shouldAssumeDSOLocal returns false, it's either a dllimport reference, or a reference that we should treat as non-local and create a stub for. Clean up AArch64Subtarget::ClassifyGlobalReference a little while touching the flag handling relating to dllimport. Differential Revision: https://reviews.llvm.org/D51590 llvm-svn: 341402
* [MinGW] [AArch64] Add stubs for potential automatic dllimported variablesMartin Storsjo2018-09-045-8/+35
| | | | | | | | | | | The runtime pseudo relocations can't handle the AArch64 format PC relative addressing in adrp+add/ldr pairs. By using stubs, the potentially dllimported addresses can be touched up by the runtime pseudo relocation framework. Differential Revision: https://reviews.llvm.org/D51452 llvm-svn: 341401
* Fix unused variable warningReid Kleckner2018-09-041-2/+2
| | | | llvm-svn: 341400
* [SimpleLoopUnswitch] remove a chain of dead blocks at onceFedor Sergeev2018-09-041-19/+19
| | | | | | | | | | | | | | | | | | | | | | Recent change to deleteDeadBlocksFromLoop was not enough to fix all the problems related to dead blocks after nontrivial unswitching of switches. We need to delete all the dead blocks that were created during unswitching, otherwise we will keep having problems with phi's or dead blocks. This change removes all the dead blocks that are reachable from the loop, not trying to track whether these blocks are newly created by unswitching or not. While not completely correct, we are unlikely to get loose but reachable dead blocks that do not belong to our loop nest. It does fix all the failures currently known, in particular PR38778. Reviewed By: asbirlea Differential Revision: https://reviews.llvm.org/D51519 llvm-svn: 341398
* Set console mode when -fansi-escape-codes is enabled David Bolvansky2018-09-041-0/+9
| | | | | | | | | | | | | | | | | | | | | Summary: Windows console now supports supports ANSI escape codes, but we need to enable it using SetConsoleMode with ENABLE_VIRTUAL_TERMINAL_PROCESSING flag. Fixes https://bugs.llvm.org/show_bug.cgi?id=38817 Tested on Windows 10, screenshot: https://i.imgur.com/bqYq0Uy.png Reviewers: zturner, chandlerc Reviewed By: zturner Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D51611 llvm-svn: 341396
* AMDGPU: Fix DAG divergence not reporting flat loadsMatt Arsenault2018-09-041-4/+4
| | | | | | Match behavior in DAG of r340343 llvm-svn: 341393
* DAG: Factor out helper function for odd vector sizesMatt Arsenault2018-09-041-22/+28
| | | | llvm-svn: 341392
* Fix build failures after rL341386.Hiroshi Yamauchi2018-09-041-0/+8
| | | | | | | | | | | | Reviewers: davidxl Reviewed By: davidxl Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D51647 llvm-svn: 341391
* [WebAssembly] Fix operand rewriting in inline asm lowering.Dan Gohman2018-09-041-4/+2
| | | | | | | | | | | Use MachineOperand::ChangeToImmediate rather than reassigning MachineOperands to new values created from MachineOperand::CreateImm, so that their parent pointers are preserved. This fixes "Instruction has operand with wrong parent set" errors reported by the MachineVerifier. llvm-svn: 341389
* [PGO] Control Height ReductionHiroshi Yamauchi2018-09-046-0/+2030
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: Control height reduction merges conditional blocks of code and reduces the number of conditional branches in the hot path based on profiles. if (hot_cond1) { // Likely true. do_stg_hot1(); } if (hot_cond2) { // Likely true. do_stg_hot2(); } -> if (hot_cond1 && hot_cond2) { // Hot path. do_stg_hot1(); do_stg_hot2(); } else { // Cold path. if (hot_cond1) { do_stg_hot1(); } if (hot_cond2) { do_stg_hot2(); } } This speeds up some internal benchmarks up to ~30%. Reviewers: davidxl Reviewed By: davidxl Subscribers: xbolva00, dmgreen, mehdi_amini, llvm-commits, mgorny Differential Revision: https://reviews.llvm.org/D50591 llvm-svn: 341386
* [CodeGen] Fix remaining zext() assertions in SelectionDAGScott Linder2018-09-042-16/+14
| | | | | | | | Fix remaining cases not committed in https://reviews.llvm.org/D49574 Differential Revision: https://reviews.llvm.org/D50659 llvm-svn: 341380
* [MachO] Fix inconsistency between error messages when validating LC_DYSYMTABFrancis Visoiu Mistrih2018-09-041-2/+2
| | | | llvm-svn: 341379
* [MachO] Fix LC_DYSYMTAB validation for external symbolsFrancis Visoiu Mistrih2018-09-041-1/+1
| | | | | | | We were validating the same index (ilocalsym) twice, while iextdefsym was never validated. llvm-svn: 341378
* [dwarfdump] Improve -diff option by hiding more data.Jonas Devlieghere2018-09-042-9/+12
| | | | | | | | | | The -diff option makes it easy to diff dwarf by hiding addresses and offsets. However not all of them were hidden, which should be fixed by this patch. Differential revision: https://reviews.llvm.org/D51593 llvm-svn: 341377
* Revert r341269: [Constant Hoisting] Hoisting Constant GEP ExpressionsChandler Carruth2018-09-041-136/+36
| | | | | | | | | | One of the tests is failing 50% of the time when expensive checks are enabled. Not sure how deep the problem is so just reverting while the author can investigate so that the bots stop repeatedly failing and blaming things incorrectly. Will respond with details on the original commit. llvm-svn: 341365
* [x86/SLH] Add a real Clang flag and LLVM IR attribute for SpeculativeChandler Carruth2018-09-0411-7/+30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Load Hardening. Wires up the existing pass to work with a proper IR attribute rather than just a hidden/internal flag. The internal flag continues to work for now, but I'll likely remove it soon. Most of the churn here is adding the IR attribute. I talked about this Kristof Beyls and he seemed at least initially OK with this direction. The idea of using a full attribute here is that we *do* expect at least some forms of this for other architectures. There isn't anything *inherently* x86-specific about this technique, just that we only have an implementation for x86 at the moment. While we could potentially expose this as a Clang-level attribute as well, that seems like a good question to defer for the moment as it isn't 100% clear whether that or some other programmer interface (or both?) would be best. We'll defer the programmer interface side of this for now, but at least get to the point where the feature can be enabled without relying on implementation details. This also allows us to do something that was really hard before: we can enable *just* the indirect call retpolines when using SLH. For x86, we don't have any other way to mitigate indirect calls. Other architectures may take a different approach of course, and none of this is surfaced to user-level flags. Differential Revision: https://reviews.llvm.org/D51157 llvm-svn: 341363
* [x86/SLH] Teach SLH to harden against the "ret2spec" attack byChandler Carruth2018-09-041-32/+151
| | | | | | | | | | | | | | | | | | | | | | | | | | | | implementing the proposed mitigation technique described in the original design document. The idea is to check after calls that the return address used to arrive at that location is in fact the correct address. In the event of a mis-predicted return which reaches a *valid* return but not the *correct* return, this will detect the mismatch much like it would a mispredicted conditional branch. This is the last published attack vector that I am aware of in the Spectre v1 space which is not mitigated by SLH+retpolines. However, don't read *too* much into that: this is an area of ongoing research where we expect more issues to be discovered in the future, and it also makes no attempt to mitigate Spectre v4. Still, this is an important completeness bar for SLH. The change here is of course delightfully simple. It was predicated on cutting support for post-instruction symbols into LLVM which was not at all simple. Many thanks to Hal Finkel, Reid Kleckner, and Justin Bogner who helped me figure out how to do a bunch of the complex changes involved there. Differential Revision: https://reviews.llvm.org/D50837 llvm-svn: 341358
* Do not leak the Mach host port in sys::getHostCPUName()Kristina Brooks2018-09-041-1/+3
| | | | | | Patch by rsesek (Robert Sesek) llvm-svn: 341357
* [x86/SLH] Teach SLH to harden indirect branches and switches withoutChandler Carruth2018-09-041-3/+268
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | retpolines. This implements the core design of tracing the intended target into the target, checking it, and using that to update the predicate state. It takes advantage of a few interesting aspects of SLH to make it a bit easier to implement: - We already split critical edges with conditional branches, so we can assume those are gone. - We already unfolded any memory access in the indirect branch instruction itself. I've left hard errors in place to catch if any of these somewhat subtle invariants get violated. There is some code that I can factor out and share with D50837 when it lands, but I didn't want to couple landing the two patches, so I'll do that in a follow-up cleanup commit if alright. Factoring out the code to handle different scenarios of materializing an address remains frustratingly hard. In a bunch of cases you want to fold one of the cases into an immediate operand of some other instruction, and you also have both symbols and basic blocks being used which require different methods on the MI builder (and different operand kinds). Still, I'll take a stab at sharing at least some of this code in a follow-up if I can figure out how. Differential Revision: https://reviews.llvm.org/D51083 llvm-svn: 341356
* [InstCombine] Fold icmp ugt/ult (add nuw X, C2), C --> icmp ugt/ult X, (C - C2)Nicola Zaghen2018-09-041-5/+8
| | | | | | | | | | Support for sgt/slt was added in rL294898, this adds the same cases also for unsigned compares. This is the Alive proof: https://rise4fun.com/Alive/nyY Differential Revision: https://reviews.llvm.org/D50972 llvm-svn: 341353
* [NFC] Add assert to detect LCSSA breaches earlyMax Kazantsev2018-09-041-0/+10
| | | | llvm-svn: 341347
* [PassTiming] reporting time-passes separately for multiple pass instances of ↵Fedor Sergeev2018-09-041-12/+30
| | | | | | | | | | | | | | | | | | | | | | | | | | the same pass Summary: Refactoring done by rL340872 accidentally appeared to be non-NFC, changing the way how multiple instances of the same pass are handled - aggregation of results by PassName forced data for multiple instances to be merged together and reported as one line. Getting back to creating/reporting timers per pass instance. Reporting was a bit enhanced by counting pass instances and adding #<num> suffix to the pass description. Note that it is instances that are being counted, not invocations of them. time-passes test updated to account for multiple passes being run. Reviewers: paquette, jhenderson, MatzeB, skatkov Reviewed By: skatkov Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D51535 llvm-svn: 341346
* [IndVars] Fix usage of SCEVExpander to not mess with SCEVConstant. PR38674Max Kazantsev2018-09-041-18/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch removes the function `expandSCEVIfNeeded` which behaves not as it was intended. This function tries to make a lookup for exact existing expansion and only goes to normal expansion via `expandCodeFor` if this lookup hasn't found anything. As a result of this, if some instruction above the loop has a `SCEVConstant` SCEV, this logic will return this instruction when asked for this `SCEVConstant` rather than return a constant value. This is both non-profitable and in some cases leads to breach of LCSSA form (as in PR38674). Whether or not it is possible to break LCSSA with this algorithm and with some non-constant SCEVs is still in question, this is still being investigated. I wasn't able to construct such a test so far, so maybe this situation is impossible. If it is, it will go as a separate fix. Rather than do it, it is always correct to just invoke `expandCodeFor` unconditionally: it behaves smarter about insertion points, and as side effect of this it will choose a constant value for SCEVConstants. For other SCEVs it may end up finding a better insertion point. So it should not be worse in any case. NOTE: So far the only known case for which this transform may break LCSSA is mapping of SCEVConstant to an instruction. However there is a suspicion that the entire algorithm can compromise LCSSA form for other cases as well (yet not proved). Differential Revision: https://reviews.llvm.org/D51286 Reviewed By: etherzhhb llvm-svn: 341345
* [mips] Disable the selection of mixed microMIPS/MIPS codeSimon Atanasyan2018-09-034-8/+40
| | | | | | | | | | | | | This patch modifies hasStandardEncoding() / inMicroMipsMode() / inMips16Mode() methods of the MipsSubtarget class so only one can be true at any one time. That prevents the selection of microMIPS and MIPS instructions and patterns that are defined in TableGen files at the same time. A few new patterns and instruction definitions hae been added to keep test cases passed. Differential revision: https://reviews.llvm.org/D51483 llvm-svn: 341338
* [InstCombine] simplify xor/not folds; NFCISanjay Patel2018-09-031-22/+16
| | | | llvm-svn: 341336
* [InstCombine] allow add+not --> sub for arbitrary vector constants.Sanjay Patel2018-09-031-5/+4
| | | | llvm-svn: 341335
* Revert r341329 due to MSAN errorBrian Gesiak2018-09-031-24/+24
| | | | | | | Pushing https://reviews.llvm.org/rL341329 revealed an MSAN error. Revert it so that we can fix the error. llvm-svn: 341333
* Revert [Hexagon] Add support for getRegisterByName.Sid Manning2018-09-032-49/+0
| | | | | | Support required to build the Hexagon Linux kernel. llvm-svn: 341331
* [SLC] Support expanding pow(x, n+0.5) to x * x * ... * sqrt(x)Florian Hahn2018-09-031-14/+52
| | | | | | | | | | Reviewers: evandro, efriedma, spatel Reviewed By: spatel Differential Revision: https://reviews.llvm.org/D51435 llvm-svn: 341330
* Re-push "[Option] Fix PR37006 prefix choice in findNearest"Brian Gesiak2018-09-031-24/+24
| | | | | | | | | | | | | | | | | | | | Summary: Original changeset (https://reviews.llvm.org/D46776) by @modocache. It was reverted after the PS4 bot failed. The issue has been determined to be with the way the PS4 SDK handles this particular option. https://reviews.llvm.org/D50410 removes this test, so we can push this again. Patch by Arnaud Coomans! Reviewers: cfe-commits, modocache Reviewed By: modocache Differential Revision: https://reviews.llvm.org/D50515 llvm-svn: 341329
* [X86] Remove wrong ReadAdvance from multiclass sse_fp_unop_s.Andrea Di Biagio2018-09-031-1/+1
| | | | | | | | | | | | | | | | | | | | | | A ReadAdvance was incorrectly added to the SchedReadWrite list associated with the following SSE instructions: sqrtss sqrtsd rsqrtss rcpss As a consequence, a wrong operand latency was computed for the register operand used as the base address of the folded load operand. This patch removes the wrong ReadAdvance, and updates the llvm-mca test cases. There is still a problem with correctly modeling partial register writes on XMM registers This other problem is currently tracked here: https://bugs.llvm.org/show_bug.cgi?id=38813 Differential Revision: https://reviews.llvm.org/D51542 llvm-svn: 341326
* Add header guards to some headers that are missing themArgyrios Kyrtzidis2018-09-033-0/+15
| | | | | | | Also adjust some of dsymutil's headers to put the header guards at the top, otherwise the compiler will not recognize them as header guards. llvm-svn: 341323
* DAG: Handle extract_vector_elt in isKnownNeverNaNMatt Arsenault2018-09-031-0/+3
| | | | llvm-svn: 341317
* [DebugInfo] Have the verifier accept missing linkage names.Jonas Devlieghere2018-09-031-5/+10
| | | | | | | | | | | | | | | | | | According to the standard, for the .debug_names (the "dwarf accelerator tables"): > If a subprogram or inlined subroutine is included, and has a > DW_AT_linkage_name attribute, there will be an additional index entry > for the linkage name. For Swift we generate DW_structure_types with a linkage name and the verifier was incorrectly rejecting this. This patch fixes that by only considering the linkage name in those particular cases. The test is the "reduced" debug info of the failing swift test on swift.org. Differential revision: https://reviews.llvm.org/D51420 llvm-svn: 341311
* [AArch64] Simplify code in LowerGlobalAddress. NFCI.Martin Storsjo2018-09-031-7/+4
| | | | | | | | | When initial support for dllimport was added for aarch64 in SVN r316555, ClassifyGlobalReference didn't set the MO_DLLIMPORT flag - that was only completed in SVN r323810. Reuse the return value from ClassifyGlobalReference for this purpose as well. llvm-svn: 341310
* [Sparc] allow tls_add/tls_call syntax in assembler parserDaniel Cederman2018-09-032-2/+2
| | | | | | | | | | | | | | | | | Summary: Removing unneeded isCodeGenOnly from tls-specific instructions - TLS_ADD/TLS_LD/TLS_LDX/TLS_CALL. Author: fedor.sergeev Reviewers: jyknight, fedor.sergeev Reviewed By: jyknight Subscribers: dcederman, brad, llvm-commits Differential Revision: https://reviews.llvm.org/D36463 llvm-svn: 341308
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