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* [PowerPC] Add support for TLS data relocationsUlrich Weigand2013-07-013-0/+13
| | | | | | | | | | This adds support for TLS data relocations and modifiers: .quad target@dtpmod .quad target@tprel .quad target@dtprel Currently exploited by the asm parser only. llvm-svn: 185394
* Remove floating point computations form SpillPlacement.cpp.Jakob Stoklund Olesen2013-07-012-69/+67
| | | | | | | | | | | | | | | | | | Patch by Benjamin Kramer! Use the BlockFrequency class instead of floats in the Hopfield network computations. This rescales the node Bias field from a [-2;2] float range to two block frequencies BiasN and BiasP pulling in opposite directions. This construct has a more predictable behavior when block frequencies saturate. The per-node scaling factors are no longer necessary, assuming the block frequencies around a bundle are consistent. This patch can cause the register allocator to make different spilling decisions. The differences should be small. llvm-svn: 185393
* Change if (cond) ... else llvm_unreachable("text") to assert(cond && "text") ...Richard Trieu2013-07-011-7/+5
| | | | llvm-svn: 185392
* PR16493: DebugInfo with TLS on PPC crashing due to invalid relocationDavid Blaikie2013-07-013-4/+9
| | | | | | | | Restrict the current TLS support to X86 ELF for now. Test that we don't produce it on PPC & we can flesh that test case out with the right thing once someone implements it. llvm-svn: 185389
* [PowerPC] Support all condition register logical instructionsUlrich Weigand2013-07-011-5/+32
| | | | | | | This adds support for all missing condition register logical instructions and extended mnemonics to the asm parser. llvm-svn: 185387
* Add a newline.Chad Rosier2013-07-011-1/+1
| | | | llvm-svn: 185385
* Debug Info: clean up usage of Verify.Manman Ren2013-07-012-17/+19
| | | | | | | No functionality change. It should suffice to check the type of a debug info metadata, instead of calling Verify. llvm-svn: 185383
* Index: test/CodeGen/PowerPC/reloc-align.llBill Schmidt2013-07-012-0/+27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | =================================================================== --- test/CodeGen/PowerPC/reloc-align.ll (revision 0) +++ test/CodeGen/PowerPC/reloc-align.ll (revision 0) @@ -0,0 +1,34 @@ +; RUN: llc -mcpu=pwr7 -O1 < %s | FileCheck %s + +; This test verifies that the peephole optimization of address accesses +; does not produce a load or store with a relocation that can't be +; satisfied for a given instruction encoding. Reduced from a test supplied +; by Hal Finkel. + +target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64" +target triple = "powerpc64-unknown-linux-gnu" + +%struct.S1 = type { [8 x i8] } + +@main.l_1554 = internal global { i8, i8, i8, i8, i8, i8, i8, i8 } { i8 -1, i8 -6, i8 57, i8 62, i8 -48, i8 0, i8 58, i8 80 }, align 1 + +; Function Attrs: nounwind readonly +define signext i32 @main() #0 { +entry: + %call = tail call fastcc signext i32 @func_90(%struct.S1* byval bitcast ({ i8, i8, i8, i8, i8, i8, i8, i8 }* @main.l_1554 to %struct.S1*)) +; CHECK-NOT: ld {{[0-9]+}}, main.l_1554@toc@l + ret i32 %call +} + +; Function Attrs: nounwind readonly +define internal fastcc signext i32 @func_90(%struct.S1* byval nocapture %p_91) #0 { +entry: + %0 = bitcast %struct.S1* %p_91 to i64* + %bf.load = load i64* %0, align 1 + %bf.shl = shl i64 %bf.load, 26 + %bf.ashr = ashr i64 %bf.shl, 54 + %bf.cast = trunc i64 %bf.ashr to i32 + ret i32 %bf.cast +} + +attributes #0 = { nounwind readonly "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf"="true" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-float"="false" } Index: lib/Target/PowerPC/PPCAsmPrinter.cpp =================================================================== --- lib/Target/PowerPC/PPCAsmPrinter.cpp (revision 185327) +++ lib/Target/PowerPC/PPCAsmPrinter.cpp (working copy) @@ -679,7 +679,26 @@ void PPCAsmPrinter::EmitInstruction(const MachineI OutStreamer.EmitRawText(StringRef("\tmsync")); return; } + break; + case PPC::LD: + case PPC::STD: + case PPC::LWA: { + // Verify alignment is legal, so we don't create relocations + // that can't be supported. + // FIXME: This test is currently disabled for Darwin. The test + // suite shows a handful of test cases that fail this check for + // Darwin. Those need to be investigated before this sanity test + // can be enabled for those subtargets. + if (!Subtarget.isDarwin()) { + unsigned OpNum = (MI->getOpcode() == PPC::STD) ? 2 : 1; + const MachineOperand &MO = MI->getOperand(OpNum); + if (MO.isGlobal() && MO.getGlobal()->getAlignment() < 4) + llvm_unreachable("Global must be word-aligned for LD, STD, LWA!"); + } + // Now process the instruction normally. + break; } + } LowerPPCMachineInstrToMCInst(MI, TmpInst, *this); OutStreamer.EmitInstruction(TmpInst); Index: lib/Target/PowerPC/PPCISelDAGToDAG.cpp =================================================================== --- lib/Target/PowerPC/PPCISelDAGToDAG.cpp (revision 185327) +++ lib/Target/PowerPC/PPCISelDAGToDAG.cpp (working copy) @@ -1530,6 +1530,14 @@ void PPCDAGToDAGISel::PostprocessISelDAG() { if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(ImmOpnd)) { SDLoc dl(GA); const GlobalValue *GV = GA->getGlobal(); + // We can't perform this optimization for data whose alignment + // is insufficient for the instruction encoding. + if (GV->getAlignment() < 4 && + (StorageOpcode == PPC::LD || StorageOpcode == PPC::STD || + StorageOpcode == PPC::LWA)) { + DEBUG(dbgs() << "Rejected this candidate for alignment.\n\n"); + continue; + } ImmOpnd = CurDAG->getTargetGlobalAddress(GV, dl, MVT::i64, 0, Flags); } else if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(ImmOpnd)) { llvm-svn: 185380
* [ARMAsmParser] Sort the ARM register lists based on the encoding value, not theChad Rosier2013-07-011-15/+23
| | | | | | tablegen enum values. This should be the last fix due to fallout from r185094. llvm-svn: 185379
* Make PBQP require/preserve MachineLoopInfo - the spiller requires it.Lang Hames2013-07-011-0/+3
| | | | llvm-svn: 185378
* [mips] Reverse the order of source operands of shift and rotate instructions ↵Akira Hatanaka2013-07-012-8/+8
| | | | | | | | | | that have three register operands. No intended functionality changes. llvm-svn: 185376
* [PowerPC] Also add "msync" aliasUlrich Weigand2013-07-011-0/+1
| | | | | | | This adds an alias for "msync" (which is used on Book E systems instead of "sync"). llvm-svn: 185375
* [mips] Increase the number of floating point control registers available to 32.Akira Hatanaka2013-07-011-4/+9
| | | | | | | Create a dedicated register class for floating point condition code registers and move FCC0 from register class CCR to the new register class. llvm-svn: 185373
* Fix the build after r185363. Use llvm::next instead of raw next.Cameron Zwarich2013-07-011-1/+1
| | | | llvm-svn: 185367
* Add jump tables handling for MSP430.Anton Korobeynikov2013-07-012-0/+11
| | | | | | Patch by Job Noorman! llvm-svn: 185364
* Fix PR16508.Cameron Zwarich2013-07-011-4/+8
| | | | | | | | | | | | When phis get lowered, destination copies are inserted using an iterator that is determined once for all phis in the block, which BuildMI interprets as a request to insert an instruction directly before the iterator. In the case of a cyclic phi, source copies may also be inserted directly before this iterator, which can cause source copies to be inserted before destination copies. The fix is to keep an iterator to the last phi and then advance it while lowering each phi in order to insert destination copies directly after the phis. llvm-svn: 185363
* Don't form PPC CTR loops for over-sized exit countsHal Finkel2013-07-011-0/+3
| | | | | | | | | | Although you can't generate this from C on PPC64, if you have a loop using a 64-bit counter on PPC32 then you can't form a CTR-based loop for it. This had been cauing the PPCCTRLoops pass to assert. Thanks to Joerg Sonnenberger for providing a test case! llvm-svn: 185361
* AArch64: correct CodeGen of MOVZ/MOVK combinations.Tim Northover2013-07-013-17/+22
| | | | | | | | | | | | According to the AArch64 ELF specification (4.6.8), it's the assembler's responsibility to make sure the shift amount is correct in relocated MOVZ/MOVK instructions. This wasn't being obeyed by either the MCJIT CodeGen or RuntimeDyldELF (which happened to work out well for JIT tests). This commit should make us compliant in this area. llvm-svn: 185360
* Revert r185339 (ARM: relax the atomic release barrier to "dmb ishst")Tim Northover2013-07-011-5/+1
| | | | | | | | | Turns out I'd misread the architecture reference manual and thought that was a load/store-store barrier, when it's not. Thanks for pointing it out Eli! llvm-svn: 185356
* Debug Info: Scope of a DebugLoc should not be null.Manman Ren2013-07-011-6/+3
| | | | | | No functionality change. Remove handling for the null case. llvm-svn: 185354
* [PowerPC] Fix @got references to local symbolsUlrich Weigand2013-07-011-0/+34
| | | | | | | | | | | A @got reference must always result in a relocation, so that the linker has a chance to set up the GOT entry, even if the symbol happens to be local. Add a PPCELFObjectWriter::ExplicitRelSym routine that enforces a relocation to be emitted for GOT references. llvm-svn: 185353
* [PowerPC] Add "wait" instructionUlrich Weigand2013-07-011-0/+7
| | | | | | This adds the "wait" instruction and its extended mnemonics. llvm-svn: 185350
* [PowerPC] Support "eieio" instructionUlrich Weigand2013-07-012-0/+9
| | | | | | | This adds support for the "eieio" instruction to the asm parser. llvm-svn: 185349
* Added c++ mode selector to head of SelectionDAGBuilder.h so editors open it ↵Michael Gottesman2013-07-011-1/+1
| | | | | | in c++ mode instead of c mode. llvm-svn: 185348
* [PowerPC] Add variants of "sync" instructionUlrich Weigand2013-07-012-5/+12
| | | | | | | This adds support for the "sync $L" instruction with operand, and provides aliases for "lwsync" and "ptesync". llvm-svn: 185344
* ARM: relax the atomic release barrier to "dmb ishst"Tim Northover2013-07-011-1/+5
| | | | | | | | | | | I believe the full "dmb ish" barrier is not required to guarantee release semantics for atomic operations. The weaker "dmb ishst" prevents previous operations being reordered with a store executed afterwards, which is enough. A key point to note (fortunately already correct) is that this barrier alone is *insufficient* for sequential consistency, no matter how liberally placed. llvm-svn: 185339
* [NVPTX] Add support for module-scope inline asmJustin Holewinski2013-07-011-0/+10
| | | | | | | Since we were explicitly not calling AsmPrinter::doInitialization, any module-scope inline asm was not being printed. llvm-svn: 185336
* [NVPTX] We dont use NVBuiltin anymoreJustin Holewinski2013-07-012-3/+0
| | | | llvm-svn: 185335
* [NVPTX] Cut down on physical register defsJustin Holewinski2013-07-013-28/+13
| | | | | | | | We are using virtual registers throughout now, but we still need to keep a few physical registers per class around to keep the infrastructure happy. llvm-svn: 185334
* [NVPTX] 64-bit ADDC/ADDE are not legalJustin Holewinski2013-07-011-0/+3
| | | | llvm-svn: 185333
* [NVPTX] Fix vector loads from parameters that span multiple loads, and fix ↵Justin Holewinski2013-07-012-156/+9
| | | | | | some typos llvm-svn: 185332
* [NVPTX] Handle signext/zeroext attributes properlyJustin Holewinski2013-07-011-19/+25
| | | | | | | | Fix a case where we were incorrectly sign-extending a value when we should have been zero-extending the value. Also change some SIGN_EXTEND to ANY_EXTEND because we really dont care and may have more opportunity to fold subexpressions llvm-svn: 185331
* [NVPTX] Add support for native SIGN_EXTEND_INREG where availableJustin Holewinski2013-07-012-4/+32
| | | | llvm-svn: 185330
* [NVPTX] Add isel patterns for [reg+offset] form of ldg/ldu.Justin Holewinski2013-07-012-112/+430
| | | | llvm-svn: 185329
* [NVPTX] Make sure we zero out high-order 24 bits for 8-bit load into 32-bit ↵Justin Holewinski2013-07-011-1/+2
| | | | | | value llvm-svn: 185328
* LoopVectorize: Math functions only read rounding modeArnold Schwaighofer2013-07-011-0/+7
| | | | | | | | Math functions are mark as readonly because they read the floating point rounding mode. Because we don't vectorize loops that would contain function calls that set the rounding mode it is safe to ignore this memory read. llvm-svn: 185299
* R600: Fix an unitialized variable in R600InstrInfo.cppVincent Lejeune2013-06-301-1/+1
| | | | llvm-svn: 185294
* X86: POP*rmm: move address operand to (ins) from (outs).Ahmed Bougacha2013-06-301-3/+3
| | | | llvm-svn: 185292
* DeadArgumentElimination: keep return value on functions that have a live ↵Stephen Lin2013-06-301-28/+60
| | | | | | argument with the 'returned' attribute (rather than generate invalid IR); however, if both can be eliminated, both will be llvm-svn: 185290
* ConstantFold: Check that truncating the other side is safe under a sext when ↵Benjamin Kramer2013-06-301-2/+2
| | | | | | | | trying to remove a sext from a compare. Fixes PR16462. llvm-svn: 185284
* ValueTracking: Teach isKnownToBeAPowerOfTwo about (ADD X, (XOR X, Y)) where ↵David Majnemer2013-06-291-10/+18
| | | | | | | | | X is a power of two This allows us to simplify urem instructions involving the add+xor to turn into simpler math. llvm-svn: 185272
* NVPTX: Fold otherwise unused variable into assert.Benjamin Kramer2013-06-291-2/+2
| | | | | | Avoids unused variable warnings in release builds. llvm-svn: 185271
* InstCombine: Also turn selects fed by an and into arithmetic when the types ↵Benjamin Kramer2013-06-291-4/+9
| | | | | | | | | don't match. Inserting a zext or trunc is sufficient. This pattern is somewhat common in LLVM's pointer mangling code. llvm-svn: 185270
* R600: Unbreak GCC build.Benjamin Kramer2013-06-291-1/+2
| | | | | | | operator++ on an enum is not legal. clang happens to accept it anyways, I think that's a known bug. llvm-svn: 185269
* R600: Support schedule and packetization of trans-only instVincent Lejeune2013-06-297-90/+246
| | | | llvm-svn: 185268
* R600: Bank Swizzle now display SCL equivalentVincent Lejeune2013-06-293-12/+12
| | | | llvm-svn: 185267
* misched: Compress pairs returned by getUnderlyingObjectsForInstr.Benjamin Kramer2013-06-291-12/+15
| | | | llvm-svn: 185266
* LoopVectorizer: Pack MemAccessInfo pairs.Benjamin Kramer2013-06-291-25/+22
| | | | llvm-svn: 185263
* Move helper classes into anonymous namespaces.Benjamin Kramer2013-06-291-0/+6
| | | | llvm-svn: 185262
* InstCombine: FoldGEPICmp shouldn't change sign of base pointer comparisonDavid Majnemer2013-06-291-2/+1
| | | | | | | | | | | | | | | | | | | | | | | | Changing the sign when comparing the base pointer would introduce all sorts of unexpected things like: %gep.i = getelementptr inbounds [1 x i8]* %a, i32 0, i32 0 %gep2.i = getelementptr inbounds [1 x i8]* %b, i32 0, i32 0 %cmp.i = icmp ult i8* %gep.i, %gep2.i %cmp.i1 = icmp ult [1 x i8]* %a, %b %cmp = icmp ne i1 %cmp.i, %cmp.i1 ret i1 %cmp into: %cmp.i = icmp slt [1 x i8]* %a, %b %cmp.i1 = icmp ult [1 x i8]* %a, %b %cmp = xor i1 %cmp.i, %cmp.i1 ret i1 %cmp By preserving the original sign, we now get: ret i1 false This fixes PR16483. llvm-svn: 185259
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