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* Add braces to the case statement.Chad Rosier2012-09-031-1/+2
| | | | llvm-svn: 163116
* IRBuilderify the SjlLjEHPrepare pass.Benjamin Kramer2012-09-031-57/+25
| | | | | | No functionality change. llvm-svn: 163115
* When updating live range endpoints, make sure to preserve the early clobber bit.Lang Hames2012-09-031-2/+2
| | | | | | Fixs PR13719. llvm-svn: 163107
* Fix more fallout from r158919, similar to PR13547.Bob Wilson2012-09-031-2/+7
| | | | | | | | | This code used to only handle malloc-like calls, which do not read memory. r158919 changed it to check isNoAliasFn(), which includes strdup-like and realloc-like calls, but it was not checking for dependencies on the memory read by those calls. llvm-svn: 163106
* Removed unused argument.Chad Rosier2012-09-033-18/+15
| | | | llvm-svn: 163104
* some peepholes that should match horizontal add/sub operations.Chris Lattner2012-09-031-0/+12
| | | | llvm-svn: 163103
* [ms-inline asm] Expose the Kind and Opcode variables from theChad Rosier2012-09-033-11/+25
| | | | | | | | | | MatchInstructionImpl() function. These values are used by the ConvertToMCInst() function to index into the ConversionTable. The values are also needed to call the GetMCInstOperandNum() function. llvm-svn: 163101
* Move ErrorLoc decl into the scope where it's actually used.Chad Rosier2012-09-031-2/+1
| | | | llvm-svn: 163100
* Fix a typo.Nadav Rotem2012-09-021-1/+1
| | | | llvm-svn: 163094
* Not all targets have efficient ISel code generation for select instructions.Nadav Rotem2012-09-022-7/+27
| | | | | | | | | For example, the ARM target does not have efficient ISel handling for vector selects with scalar conditions. This patch adds a TLI hook which allows the different targets to report which selects are supported well and which selects should be converted to CF duting codegen prepare. llvm-svn: 163093
* LoopRotation: Make the brute force DomTree update more brute force.Benjamin Kramer2012-09-021-32/+21
| | | | | | | | | | | | | | We update until we hit a fixpoint. This is probably slow but also slightly simplifies the code. It should also fix the occasional invalid domtrees observed when building with expensive checking. I couldn't find a case where this had a measurable slowdown, but if someone finds a pathological case where it does we may have to find a cleverer way of updating dominators here. Thanks to Duncan for the test case. llvm-svn: 163091
* Rename ANDROIDEABI to Android.Logan Chien2012-09-022-3/+3
| | | | | | | | | | | | | Most of the code guarded with ANDROIDEABI are not ARM-specific, and having no relation with arm-eabi. Thus, it will be more natural to call this environment "Android" instead of "ANDROIDEABI". Note: We are not using ANDROID because several projects are using "-DANDROID" as the conditional compilation flag. llvm-svn: 163087
* Generate better select code by allowing the target to use scalar select, and ↵Nadav Rotem2012-09-021-4/+3
| | | | | | not sign-extend. llvm-svn: 163086
* Only legalise a VSELECT in to bitwise operations if the vector mask bool is ↵Pete Cooper2012-09-011-1/+6
| | | | | | | | | zeros or all ones. A vector bool with just ones isn't suitable for masking with. No test case unfortunately as i couldn't find a target which fit all the conditions needed to hit this code. llvm-svn: 163075
* Limit domain conversion to cases where it won't break dep chains.Tim Northover2012-09-011-12/+48
| | | | | | | | NEON domain conversion was too heavy-handed with its widened registers, which could have stripped existing instructions of their dependency, leaving them vulnerable to scheduling errors. llvm-svn: 163070
* Revert "Take account of boolean vector contents when promoting a build ↵Pete Cooper2012-09-011-17/+1
| | | | | | | | | | | | | | vector from i1 to some other type. rdar://problem/12210060" This reverts commit 5dd9e214fb92847e947f9edab170f9b4e52b908f. Thanks to Duncan for explaining how this should have been done. Conflicts: test/CodeGen/X86/vec_select.ll llvm-svn: 163064
* Fix Thumb2 fixup kind in the integrated-as.Logan Chien2012-09-011-0/+4
| | | | llvm-svn: 163063
* Fix typo.Logan Chien2012-09-011-1/+1
| | | | llvm-svn: 163059
* LoopRotation: Check some invariants of the dominator updating code.Benjamin Kramer2012-09-011-0/+3
| | | | llvm-svn: 163058
* TyposCraig Topper2012-09-012-2/+2
| | | | llvm-svn: 163053
* Teach DAG combine a number of tricks to simplify FMA expressions in ↵Owen Anderson2012-09-011-0/+64
| | | | | | fast-math mode. llvm-svn: 163051
* Fix typoMichael Liao2012-09-011-1/+1
| | | | llvm-svn: 163049
* SelectionDAG: when constructing VZEXT_LOAD from other loads, make sure itsManman Ren2012-08-311-0/+12
| | | | | | | | | | | output chain is correctly setup. As an example, if the original load must happen before later stores, we need to make sure the constructed VZEXT_LOAD is constrained to be before the stores. rdar://11457792 llvm-svn: 163036
* Mark FMA4 instructions as commutable and add them to the folding tables.Craig Topper2012-08-312-0/+64
| | | | llvm-svn: 163035
* Remove an unused argument. The MCInst opcode is set in the ConvertToMCInst()Chad Rosier2012-08-311-47/+42
| | | | | | function nowadays. llvm-svn: 163030
* Add selection of RegOp2MemOpTable3 to canFoldMemoryOperandCraig Topper2012-08-311-0/+2
| | | | llvm-svn: 163029
* Add MachineInstr::tieOperands, remove setIsTied().Jakob Stoklund Olesen2012-08-312-12/+18
| | | | | | | | | | | Manage tied operands entirely internally to MachineInstr. This makes it possible to change the representation of tied operands, as I will do shortly. The constraint that tied uses and defs must be in the same order was too restrictive. llvm-svn: 163021
* Fix PR12359Michael Liao2012-08-311-3/+5
| | | | | | | | | - In addition to undefined, if V2 is zero vector, skip 2nd PSHUFB and POR as well as PSHUFB will zero elements with negative indices. Patch by Sriram Murali <sriram.murali@intel.com> llvm-svn: 163018
* The instruction DINS may be transformed into DINSU or DEXTM dependingJack Carter2012-08-314-23/+31
| | | | | | | | | | | | | | | | | | | | | on the size of the extraction and its position in the 64 bit word. This patch allows support of the dext transformations with mips64 direct object output. 0 <= msb < 32 0 <= lsb < 32 0 <= pos < 32 1 <= size <= 32 DINS The field is entirely contained in the right-most word of the doubleword 32 <= msb < 64 0 <= lsb < 32 0 <= pos < 32 2 <= size <= 64 DINSM The field straddles the words of the doubleword 32 <= msb < 64 32 <= lsb < 64 32 <= pos < 64 1 <= size <= 32 DINSU The field is entirely contained in the left-most word of the doubleword llvm-svn: 163010
* Move the GCOVFormat enums into their own namespace per the LLVM coding standard.Bill Wendling2012-08-311-10/+10
| | | | llvm-svn: 163008
* Add a comment to explain what's really going on.Chad Rosier2012-08-311-0/+6
| | | | llvm-svn: 163005
* The ConvertToMCInst() function can't fail, so remove the now dead ↵Chad Rosier2012-08-313-8/+0
| | | | | | Match_ConversionFail enum. llvm-svn: 163002
* Mark FMA3 instructions as commutable so that the operands to the multiply ↵Craig Topper2012-08-311-0/+4
| | | | | | part can be commuted. llvm-svn: 163001
* Use CloneMachineInstr to make a new MI in commuteInstruction to make the ↵Craig Topper2012-08-311-10/+1
| | | | | | code tolerant of instructions with more than two input operands. llvm-svn: 163000
* Add support for converting llvm.fma to fma4 instructions.Craig Topper2012-08-313-36/+76
| | | | llvm-svn: 162999
* Don't enforce ordered inline asm operands.Jakob Stoklund Olesen2012-08-311-10/+0
| | | | | | | | | I was too optimistic, inline asm can have tied operands that don't follow the def order. Fixes PR13742. llvm-svn: 162998
* Clean up ProfileDataLoader a bit.Benjamin Kramer2012-08-311-43/+19
| | | | | | | | | | | | - Overloading operator<< for raw_ostream and pointers is dangerous, it alters the behavior of code that includes the header. - Remove unused ID. - Use LLVM's byte swapping helpers instead of a hand-coded. - Make ReadProfilingData work directly on a pointer. No functionality change. llvm-svn: 162992
* Cleanups due to feedback. No functionality change. Patch by Alistair.Bill Wendling2012-08-312-50/+50
| | | | llvm-svn: 162979
* Clean up AddedComplexity further after adding UseSSExMichael Liao2012-08-311-17/+13
| | | | llvm-svn: 162973
* Fix a couple of typos in EmitAtomic.Jakob Stoklund Olesen2012-08-311-2/+2
| | | | | | | | | Thumb2 instructions are mostly constrained to rGPR, not tGPR which is for Thumb1. rdar://problem/12203728 llvm-svn: 162968
* X86: Fix encoding of 'movd %xmm0, %rax'Jim Grosbach2012-08-311-1/+1
| | | | | | | The assembly string for the VMOVPQIto64rr instruction incorrectly lacked the 'v' prefix, resulting in mis-assembly of the vanilla movd instruction. llvm-svn: 162963
* With the fix in r162954/162955 every cvt function returns true. Thus, haveChad Rosier2012-08-311-64/+42
| | | | | | | the ConvertToMCInst() return void, rather then a bool. Update all the cvt functions as well. llvm-svn: 162961
* Take account of boolean vector contents when promoting a build vector from ↵Pete Cooper2012-08-301-1/+17
| | | | | | i1 to some other type. rdar://problem/12210060 llvm-svn: 162960
* Teach the DAG combiner to turn chains of FADDs (x+x+x+x+...) into FMULs by ↵Owen Anderson2012-08-301-1/+122
| | | | | | constants. This is only enabled in unsafe FP math mode, since it does not preserve rounding effects for all such constants. llvm-svn: 162956
* Fix for r162954. Return the Error.Chad Rosier2012-08-301-2/+2
| | | | llvm-svn: 162955
* Move a check to the validateInstruction() function where it more properly ↵Chad Rosier2012-08-301-11/+13
| | | | | | belongs. llvm-svn: 162954
* Typo.Chad Rosier2012-08-301-1/+1
| | | | llvm-svn: 162952
* Currently targets that do not support selects with scalar conditions and ↵Nadav Rotem2012-08-301-1/+65
| | | | | | | | | | | vector operands - scalarize the code. ARM is such a target because it does not support CMOV of vectors. To implement this efficientlyi, we broadcast the condition bit and use a sequence of NAND-OR to select between the two operands. This is the same sequence we use for targets that don't have vector BLENDs (like SSE2). rdar://12201387 llvm-svn: 162926
* Introduce 'UseSSEx' to force SSE legacy encodingMichael Liao2012-08-305-122/+158
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - Add 'UseSSEx' to force SSE legacy insn not being selected when AVX is enabled. As the penalty of inter-mixing SSE and AVX instructions, we need prevent SSE legacy insn from being generated except explicitly specified through some intrinsics. For patterns supported by both SSE and AVX, so far, we force AVX insn will be tried first relying on AddedComplexity or position in td file. It's error-prone and introduces bugs accidentally. 'UseSSEx' is disabled when AVX is turned on. For SSE insns inherited by AVX, we need this predicate to force VEX encoding or SSE legacy encoding only. For insns not inherited by AVX, we still use the previous predicates, i.e. 'HasSSEx'. So far, these insns fall into the following categories: * SSE insns with MMX operands * SSE insns with GPR/MEM operands only (xFENCE, PREFETCH, CLFLUSH, CRC, and etc.) * SSE4A insns. * MMX insns. * x87 insns added by SSE. 2 test cases are modified: - test/CodeGen/X86/fast-isel-x86-64.ll AVX code generation is different from SSE one. 'vcvtsi2sdq' cannot be selected by fast-isel due to complicated pattern and fast-isel fallback to materialize it from constant pool. - test/CodeGen/X86/widen_load-1.ll AVX code generation is different from SSE one after fixing SSE/AVX inter-mixing. Exec-domain fixing prefers 'vmovapd' instead of 'vmovaps'. llvm-svn: 162919
* Apply "/Og-" also to MSC15(aka VS9) on VMCore/Function.cpp.NAKAMURA Takumi2012-08-301-1/+1
| | | | llvm-svn: 162917
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