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* Revert "Masked Vector Load and Store Intrinsics."Duncan P. N. Exon Smith2014-11-2817-745/+21
| | | | | | | | | | | This reverts commit r222632 (and follow-up r222636), which caused a host of LNT failures on an internal bot. I'll respond to the commit on the list with a reproduction of one of the failures. Conflicts: lib/Target/X86/X86TargetTransformInfo.cpp llvm-svn: 222936
* InstCombine: FoldOrOfICmps harderDavid Majnemer2014-11-281-2/+25
| | | | | | | | | | | | We may be in a situation where the icmps might not be near each other in a tree of or instructions. Try to dig out related compare instructions and see if they combine. N.B. This won't fire on deep trees of compares because rewritting the tree might end up creating a net increase of IR. We may have to resort to something more sophisticated if this is a real problem. llvm-svn: 222928
* [LICM] Store sink and indirectbr instructionsBruno Cardoso Lopes2014-11-281-0/+6
| | | | | | | | | | | | | | Loop simplify skips exit-block insertion when exits contain indirectbr instructions. This leads to an assertion in LICM when trying to sink stores out of non-dedicated loop exits containing indirectbr instructions. This patch fix this issue by re-checking for dedicated exits in LICM prior to store sink attempts. Differential Revision: http://reviews.llvm.org/D6414 rdar://problem/18943047 llvm-svn: 222927
* [SwitchLowering] Handle multiple destinations on condensed case stmtsBruno Cardoso Lopes2014-11-281-12/+29
| | | | | | | | | | | | | | Switch cases statements with sequential values that branch to the same destination BB may often be handled together in a single new source BB. In this scenario we need to remove remaining incoming values from PHI instructions in the destination BB, as to match the number of source branches. Differential Revision: http://reviews.llvm.org/D6415 rdar://problem/19040894 llvm-svn: 222926
* Enable FeatureFastUAMem for btver2Sanjay Patel2014-11-281-2/+8
| | | | | | | | | | | | | Allow unaligned 16-byte memop codegen for btver2. No functional changes for any other subtargets. Replace the existing supposed small memcpy test with an actual test of a small memcpy. The previous test wasn't using FileCheck either. This patch should allow us to close PR21541 ( http://llvm.org/bugs/show_bug.cgi?id=21541 ). Differential Revision: http://reviews.llvm.org/D6360 llvm-svn: 222925
* Add back r222727 with a fix.Rafael Espindola2014-11-281-3/+13
| | | | | | | | | | | | | | | | | | | | | The original patch would fail when: * A dst opaque type (%A) is matched with a src type (%A). * A src opaque (%E) type is then speculatively matched with %A and the speculation fails afterward. * When rolling back the speculation we would cancel the source %A to dest %A mapping. The fix is to keep an explicit list of which resolutions are speculative. Original message: Fix overly aggressive type merging. If we find out that two types are *not* isomorphic, we learn nothing about opaque sub types in both the source and destination. llvm-svn: 222923
* Add an assert and use a range loop. NFC.Rafael Espindola2014-11-281-2/+4
| | | | llvm-svn: 222922
* Fix wrong encoding of MRSBanked.Charlie Turner2014-11-281-1/+1
| | | | | | | Patch by Matthew Wahab. Change-Id: Ia2a001ca2760028ea360fe77b56f203a219eefbc llvm-svn: 222920
* [msan] Fix origin propagation for select of floats.Evgeniy Stepanov2014-11-281-3/+4
| | | | | | | | | | MSan does not assign origin for instrumentation temps (i.e. the ones that do not come from the application code), but "select" instrumentation erroneously tried to use one of those. https://code.google.com/p/memory-sanitizer/issues/detail?id=78 llvm-svn: 222918
* Removed extra line from a comment to test first commit. NFC.Ankur Garg2014-11-281-1/+0
| | | | llvm-svn: 222916
* Add missing 'override' keyword.Craig Topper2014-11-281-1/+1
| | | | llvm-svn: 222911
* Stop using ArrayRef of a const type.Tim Northover2014-11-272-2/+2
| | | | | | I *think* this is what the GCC bots are complaining about. llvm-svn: 222905
* AArch64: treat [N x Ty] as a block during procedure calls.Tim Northover2014-11-276-6/+155
| | | | | | | | | | | | | | The AAPCS treats small structs and homogeneous floating (or vector) aggregates specially, and guarantees they either get passed as a contiguous block of registers, or prevent any future use of those registers and get passed on the stack. This concept can fit quite neatly into LLVM's own type system, mapping an HFA to [N x float] and so on, and small structs to [N x i64]. Doing so allows front-ends to emit AAPCS compliant code without having to duplicate the register counting logic. llvm-svn: 222903
* [mips][microMIPS] Implement SWM16 and LWM16 instructionsZoran Jovanovic2014-11-277-0/+147
| | | | | | Differential Revision: http://reviews.llvm.org/D5579 llvm-svn: 222901
* [mips][microMIPS] Implement BREAK16 and SDBBP16 instructionsJozef Kolek2014-11-272-0/+17
| | | | | | | | Patch by Radovan Obradovic. Differential Revision: http://reviews.llvm.org/D5048 llvm-svn: 222900
* [mips] Add synci instruction.Daniel Sanders2014-11-273-1/+56
| | | | | | | | | | | | | | Patch by Amaury Pouly Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D6421 llvm-svn: 222899
* Commit back the correct bits of r222760 (was r222538).Rafael Espindola2014-11-271-0/+6
| | | | | | | | | | | | | | | | | I also added a test. Original message: Allow FDE references outside the +/-2GB range supported by PC relative offsets for code models other than small/medium. For JIT application, memory layout is less controlled and can result in truncations otherwise. Patch from Akos Kiss. Differential Revision: http://reviews.llvm.org/D6079 llvm-svn: 222897
* Revert "Reapply 222538 and update tests to explicitly request small code ↵Rafael Espindola2014-11-271-11/+0
| | | | | | | | | | | | | | | | model and PIC:" This reverts commit r222760. It changed our behaviour on PIC so we don't match gas anymore. It also included lots of unnecessary changes to tests. If those changes are desirable, there should be an independent discussion as they are out of scope for that patch. I will recommit the other bits. llvm-svn: 222896
* Revert "Fix overly aggressive type merging."Duncan P. N. Exon Smith2014-11-271-19/+8
| | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit r222727, which causes LTO bootstrap failures. Last passing @ r222698: http://lab.llvm.org:8080/green/job/clang-Rlto_master_build/532/ First failing @ r222843: http://lab.llvm.org:8080/green/job/clang-Rlto_master_build/533/ Internal bootstraps pointed at a much narrower range: r222725 is passing, and r222731 is failing. LTO crashes while handling libclang.dylib: http://lab.llvm.org:8080/green/job/clang-Rlto_master_build/533/consoleFull#-158682280549ba4694-19c4-4d7e-bec5-911270d8a58c GEP is not of right type for indices! %InfoObj.i.i = getelementptr inbounds %"class.llvm::OnDiskIterableChainedHashTable"* %.lcssa, i64 0, i32 0, i32 4, !dbg !123627 %"class.clang::serialization::reader::ASTIdentifierLookupTrait" = type { %"class.clang::ASTReader.31859"*, %"class.clang::serialization::ModuleFile.31870"*, %"class.clang::IdentifierInfo"* }LLVM ERROR: Broken function found, compilation aborted! clang: error: linker command failed with exit code 1 (use -v to see invocation) Looks like the new algorithm doesn't merge types aggressively enough. llvm-svn: 222895
* reinstate r222872: Peephole optimization in switch table lookup: reuse the ↵Erik Eckstein2014-11-271-7/+100
| | | | | | | | | | | | | | | | | | | | | | | | | | | guarding table comparison if possible. Fixed missing dominance check. Original commit message: This optimization tries to reuse the generated compare instruction, if there is a comparison against the default value after the switch. Example: if (idx < tablesize) r = table[idx]; // table does not contain default_value else r = default_value; if (r != default_value) ... Is optimized to: cond = idx < tablesize; if (cond) r = table[idx]; else r = default_value; if (cond) ... Jump threading will then eliminate the second if(cond). llvm-svn: 222891
* [msan] Remove indirect call wrapping code.Evgeniy Stepanov2014-11-271-89/+1
| | | | | | This functionality was only used in MSanDR, which is deprecated. llvm-svn: 222889
* [mips][microMIPS] Implement disassembler support for 16-bit instructions ↵Jozef Kolek2014-11-272-3/+69
| | | | | | | | LI16, ADDIUR1SP, ADDIUR2 and ADDIUS5 Differential Revision: http://reviews.llvm.org/D6419 llvm-svn: 222887
* Stop uppercasing build attribute data.Charlie Turner2014-11-271-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | The string data for string-valued build attributes were being unconditionally uppercased. There is no mention in the ARM ABI addenda about case conventions, so it's technically implementation defined as to whether the data are capitialised in some way or not. However, there are good reasons not to captialise the data. * It's less work. * Some vendors may legitimately have case-sensitive checks for these attributes which would fail on LLVM generated object files. * There could be locale issues with uppercasing. The original reasons for uppercasing appear to have stemmed from an old codesourcery toolchain behaviour, see http://comments.gmane.org/gmane.comp.compilers.llvm.cvs/87133 This patch makes the object file emitted no longer captialise string data, it encodes as seen in the assembly source. Change-Id: Ibe20dd6e60d2773d57ff72a78470839033aa5538 llvm-svn: 222882
* Revert "Peephole optimization in switch table lookup: reuse the guarding ↵Erik Eckstein2014-11-271-89/+7
| | | | | | | | table comparison if possible." It is breaking the clang bootstrag. llvm-svn: 222877
* Peephole optimization in switch table lookup: reuse the guarding table ↵Erik Eckstein2014-11-271-7/+89
| | | | | | | | | | | | | | | | | | | | | | | | | comparison if possible. This optimization tries to reuse the generated compare instruction, if there is a comparison against the default value after the switch. Example: if (idx < tablesize) r = table[idx]; // table does not contain default_value else r = default_value; if (r != default_value) ... Is optimized to: cond = idx < tablesize; if (cond) r = table[idx]; else r = default_value; if (cond) ... \endcode Jump threading will then eliminate the second if(cond). llvm-svn: 222872
* InstCombine: Restore optimizations lost in r210006David Majnemer2014-11-271-0/+28
| | | | | | | | This restores our ability to optimize: (X & C) == 0 ? X ^ C : X into X | C (X & C) != 0 ? X ^ C : X into X & ~C llvm-svn: 222871
* Add LLVMObject to LLVMExecutionEngine.NAKAMURA Takumi2014-11-271-1/+1
| | | | llvm-svn: 222869
* InstSimplify: Restore optimizations lost in r210006David Majnemer2014-11-271-0/+34
| | | | | | | | | | This restores our ability to optimize: (X & C) ? X & ~C : X into X & ~C (X & C) ? X : X & ~C into X (X & C) ? X | C : X into X (X & C) ? X : X | C into X | C llvm-svn: 222868
* [MCJIT] Remove the local symbol table from RuntimeDlyd - it's not needed.Lang Hames2014-11-2710-77/+59
| | | | | | | | All symbols have to be stored in the global symbol to enable cross-rtdyld-instance linking, so the local symbol table content is redundant. llvm-svn: 222867
* [MCJIT] Replace JITEventListener::anchor (temporarily removed in r222861), andLang Hames2014-11-274-1/+3
| | | | | | move GDBRegistrationListener into ExecutionEngine to avoid layering violation. llvm-svn: 222864
* [MCJIT] Remove JITEventListener's anchor until I can determine the right placeLang Hames2014-11-271-3/+0
| | | | | | to put it. This should unbreak the Mips bots. llvm-svn: 222861
* [MCJIT] Move get-any-symbol-load-address logic out of RuntimeDyld and intoLang Hames2014-11-272-9/+3
| | | | | | | | | RuntimeDyldChecker. RuntimeDyld instances should only provide lookup for locally defined symbols. llvm-svn: 222859
* Revert "Added inst combine transforms for single bit tests from Chris's note"David Majnemer2014-11-261-28/+1
| | | | | | | | | | | This reverts commit r210006, it miscompiled libapr which is used in who knows how many projects. A test has been added to ensure that we don't regress again. I'll work on a rewrite of what the optimization was trying to do later. llvm-svn: 222856
* Object/COFF: Fix off-by-one error for object having lots of relocationsRui Ueyama2014-11-261-1/+2
| | | | | | | | | llvm-objdump printed out an error message for this off-by-one error, but because it always exits with 0 whether or not it found an error, the test (llvm-objdump/coff-many-relocs.test) succeeded. I made llvm-objdump exit with EXIT_FAILURE when an error is found. llvm-svn: 222852
* R600/SI: Use ZeroOrNegativeOneBooleanContentMatt Arsenault2014-11-262-2/+3
| | | | | | | | | | | | | | This sort of doesn't matter since the setcc type is i1, but this previously was using the default UndefinedBooleanContent. This makes it more consistent with R600. This enables more optimizations which typically give up on UndefinedBooleanContent. For example, there is already a special case target DAG combine for setcc + sext which can be eliminated in favor of what the generic DAG combiner can do if it assumes boolean values are sign extended. Since -1 is an inline immediate, using it is basically free and the backend already uses it when a boolean value is needed in a wider type. llvm-svn: 222850
* [Hexagon] Adding cmp* immediate form instructions.Colin LeMahieu2014-11-264-62/+68
| | | | llvm-svn: 222849
* [mips][microMIPS] Implement disassembler support for 16-bit instructions ↵Jozef Kolek2014-11-263-4/+67
| | | | | | | | LBU16, LHU16, LW16, SB16, SH16 and SW16 Differential Revision: http://reviews.llvm.org/D6405 llvm-svn: 222847
* [Hexagon] Adding and64, or64, and xor64 instructions.Colin LeMahieu2014-11-261-0/+13
| | | | llvm-svn: 222846
* R600/SI: Create e64 versions of and/or/xor in SILowerI1CopiesMatt Arsenault2014-11-261-3/+3
| | | | | | | | | This fixes moving boolean constants into registers before operating on them. They get permuted and shrunk down to e32 anyway later. This is a temporary fix until the patch that removes these pseudos is committed. llvm-svn: 222844
* [MCJIT] Fix missing return statement.Lang Hames2014-11-261-0/+1
| | | | llvm-svn: 222841
* [MCJIT] Reapply r222828 and r222810-r222812 with fix for MSVC move-op issues.Lang Hames2014-11-2622-675/+558
| | | | llvm-svn: 222840
* Reverting r222828 and r222810-r222812 as they broke the build on Windows.Aaron Ballman2014-11-2622-549/+675
| | | | | | http://bb.pgr.jp/builders/ninja-clang-i686-msc17-R/builds/11753 llvm-svn: 222833
* Removing a spurious semicolon; NFCAaron Ballman2014-11-261-1/+1
| | | | llvm-svn: 222830
* Add missing "override".Evgeniy Stepanov2014-11-261-1/+1
| | | | | | Fixes compilation failure in r222810. llvm-svn: 222828
* Update AArch64 ELF relocations to ABI 1.0Will Newton2014-11-261-1/+1
| | | | | | | | | | | | | | | | | | | | This mostly entails adding relocations, however there are a couple of changes to existing relocations: 1. R_AARCH64_NONE is defined to be zero rather than 256 R_AARCH64_NONE has been defined to be zero for a long time elsewhere e.g. binutils and glibc since the submission of the AArch64 port in 2012 so this is required for compatibility. 2. R_AARCH64_TLSDESC_ADR_PAGE renamed to R_AARCH64_TLSDESC_ADR_PAGE21 I don't think there is any way for relocation names to leak out of LLVM so this should not break anything. Tested with check-all with no regressions. llvm-svn: 222821
* AVX-512: Scalar ERI intrinsicsElena Demikhovsky2014-11-264-60/+103
| | | | | | | | | | | | including SAE mode and memory operand. Added AVX512_maskable_scalar template, that should cover all scalar instructions in the future. The main difference between AVX512_maskable_scalar<> and AVX512_maskable<> is using X86select instead of vselect. I need it, because I can't create vselect node for MVT::i1 mask for scalar instruction. http://reviews.llvm.org/D6378 llvm-svn: 222820
* [MCJIT] Re-enable GDB registration (temporarily disabled in r222811), but checkLang Hames2014-11-262-0/+6
| | | | | | | | | | that we actually have an object to register first. For MachO objects, RuntimeDyld::LoadedObjectInfo::getObjectForDebug returns an empty OwningBinary<ObjectFile> which was causing crashes in the GDB registration code. llvm-svn: 222812
* [MCJIT] Temporarily disable automatic JIT debugger registration.Lang Hames2014-11-261-1/+0
| | | | | | | | | The RuntimeDyld cleanup patch r222810 turned on GDB registration for MachO objects. I expected this to be harmless, but it seems to have broken on MacsOS. Temporarily disabling debugger registration while I dig in to what's gone wrong. llvm-svn: 222811
* [MCJIT] Clean up RuntimeDyld's quirky object-ownership/modification scheme.Lang Hames2014-11-2622-675/+544
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Previously, when loading an object file, RuntimeDyld (1) took ownership of the ObjectFile instance (and associated MemoryBuffer), (2) potentially modified the object in-place, and (3) returned an ObjectImage that managed ownership of the now-modified object and provided some convenience methods. This scheme accreted over several years as features were tacked on to RuntimeDyld, and was both unintuitive and unsafe (See e.g. http://llvm.org/PR20722). This patch fixes the issue by removing all ownership and in-place modification of object files from RuntimeDyld. Existing behavior, including debugger registration, is preserved. Noteworthy changes include: (1) ObjectFile instances are now passed to RuntimeDyld by const-ref. (2) The ObjectImage and ObjectBuffer classes have been removed entirely, they existed to model ownership within RuntimeDyld, and so are no longer needed. (3) RuntimeDyld::loadObject now returns an instance of a new class, RuntimeDyld::LoadedObjectInfo, which can be used to construct a modified object suitable for registration with the debugger, following the existing debugger registration scheme. (4) The JITRegistrar class has been removed, and the GDBRegistrar class has been re-written as a JITEventListener. This should fix http://llvm.org/PR20722 . llvm-svn: 222810
* Replace neverHasSideEffects=1 with hasSideEffects=0 in all .td files.Craig Topper2014-11-2634-298/+298
| | | | llvm-svn: 222801
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