summaryrefslogtreecommitdiffstats
path: root/llvm/lib
Commit message (Collapse)AuthorAgeFilesLines
* [PowerPC] Fix some Include What You Use warnings; other minor fixes (NFC).Eugene Zelenko2017-02-071-3/+11
| | | | | | This is preparation to reduce MC headers dependencies. llvm-svn: 294368
* [libFuzzer] replace std::random_shuffle with std::shuffle as ↵Kostya Serebryany2017-02-074-10/+7
| | | | | | std::random_shuffle is being deprecated in C++17. Also simplify fuzzer::Random. NFC llvm-svn: 294366
* PredicateInfo: Some compilers are unhappy with naming Use *'s Use. Change ↵Daniel Berlin2017-02-071-13/+13
| | | | | | the name. llvm-svn: 294364
* DebugInfo: Track spilled variables in LiveDebugValuesWolfgang Pieb2017-02-071-7/+137
| | | | | | | | | | | | | When variables are spilled to the stack by the register allocator, keep track of their debug locations in LiveDebugValues and insert DBG_VALUE instructions at the appropriate place. Ensure that the locations are propagated down the dominator tree via the existing mechanisms. Reviewer: aprantl Differential Revision: https://reviews.llvm.org/D29500 llvm-svn: 294356
* Fix a typo in an error message for a check of invalid Mach-O files whereKevin Enderby2017-02-071-1/+1
| | | | | | | | | | | | it was printing the field name fileoff instead of filesize. The original check was added in r278557. This was found in tracking down the problem that lead to the fix in r293842 - [dsymutil] Fix __LINKEDIT vmsize in dsymutil upgrade path rdar://30386075 llvm-svn: 294354
* Add PredicateInfo utility and printing passDaniel Berlin2017-02-074-0/+643
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: This patch adds a utility to build extended SSA (see "ABCD: eliminating array bounds checks on demand"), and an intrinsic to support it. This is then used to get functionality equivalent to propagateEquality in GVN, in NewGVN (without having to replace instructions as we go). It would work similarly in SCCP or other passes. This has been talked about a few times, so i built a real implementation and tried to productionize it. Copies are inserted for operands used in assumes and conditional branches that are based on comparisons (see below for more) Every use affected by the predicate is renamed to the appropriate intrinsic result. E.g. %cmp = icmp eq i32 %x, 50 br i1 %cmp, label %true, label %false true: ret i32 %x false: ret i32 1 will become %cmp = icmp eq i32, %x, 50 br i1 %cmp, label %true, label %false true: ; Has predicate info ; branch predicate info { TrueEdge: 1 Comparison: %cmp = icmp eq i32 %x, 50 } %x.0 = call @llvm.ssa_copy.i32(i32 %x) ret i32 %x.0 false: ret i23 1 (you can use -print-predicateinfo to get an annotated-with-predicateinfo dump) This enables us to easily determine what operations are affected by a given predicate, and how operations affected by a chain of predicates. Reviewers: davide, sanjoy Subscribers: mgorny, llvm-commits, Prazek Differential Revision: https://reviews.llvm.org/D29519 Update for review comments Fix a bug Nuno noticed where we are giving information about and/or on edges where the info is not useful and easy to use wrong Update for review comments llvm-svn: 294351
* [X86] Disable conditional tail calls (PR31257)Hans Wennborg2017-02-076-182/+2
| | | | | | | | | They are currently modelled incorrectly (as calls, which clobber registers, confusing e.g. Machine Copy Propagation). Reverting until we figure out the proper solution. llvm-svn: 294348
* GlobalISel: translate @llvm.va_end intrinsic.Tim Northover2017-02-071-0/+4
| | | | | | | Turns out no-one actually cares about this one (at least) in tree so we can just drop it entirely. llvm-svn: 294345
* [x86] improve comments for SHRUNKBLEND node creation; NFCSanjay Patel2017-02-072-28/+27
| | | | llvm-svn: 294344
* [ImplicitNullCheck] Extend Implicit Null Check scope by using storesSanjoy Das2017-02-074-67/+102
| | | | | | | | | | | | | | | | | | | | | Summary: This change allows usage of store instruction for implicit null check. Memory Aliasing Analisys is not used and change conservatively supposes that any store and load may access the same memory. As a result re-ordering of store-store, store-load and load-store is prohibited. Patch by Serguei Katkov! Reviewers: reames, sanjoy Reviewed By: sanjoy Subscribers: atrick, llvm-commits Differential Revision: https://reviews.llvm.org/D29400 llvm-svn: 294338
* [x86] use range-for loops; NFCISanjay Patel2017-02-071-8/+6
| | | | llvm-svn: 294337
* [x86] use getSignBit() for clarity; NFCISanjay Patel2017-02-071-4/+3
| | | | llvm-svn: 294333
* Fix the -Werror build for some sign-comparisonsDavid Blaikie2017-02-071-1/+1
| | | | llvm-svn: 294331
* [PowerPC][Altivec] Add vnot extended mnemonicNemanja Ivanovic2017-02-071-0/+1
| | | | | | | | | | Adds the vnot extended mnemonic for the vnor instruction. Committing on behalf of brunoalr (Bruno Rosa). Differential Revision: https://reviews.llvm.org/D29225 llvm-svn: 294330
* [SDAGISel] Simplify some SDAGISel code, NFCReid Kleckner2017-02-072-81/+84
| | | | | | | | | | | | Hoist entry block code for arguments and swift error values out of the basic block instruction selection loop. Lowering arguments once up front seems much more readable than doing it conditionally inside the loop. It also makes it clear that argument lowering can update StaticAllocaMap because no instructions have been selected yet. Also use range-based for loops where possible. llvm-svn: 294329
* Attempt to fix MSVC build broken by r294326Pavel Labath2017-02-071-6/+6
| | | | | | MSVC does not think that `char []` can be constexpr. Switch to regular const. llvm-svn: 294327
* [Support] Add FormatVariadic support for chrono typesPavel Labath2017-02-071-0/+7
| | | | | | | | | | | | | | | | Summary: The formatter has three knobs: - the user can choose which time unit to use for formatting (default: whatever is the unit of the input) - he can choose whether the unit gets displayed (default: yes) - he can affect the way the number itself is formatted via standard number formatting options (default:default) Reviewers: zturner, inglorion Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D29481 llvm-svn: 294326
* [TargetLowering] fix formatting and comments for ShrinkDemandedConstant; NFCSanjay Patel2017-02-071-19/+20
| | | | llvm-svn: 294325
* [AMDGPU] Fix for SIMachineScheduler crash. SI Scheduler should trackAlexander Timofeev2017-02-072-4/+3
| | | | | | | | lane masks. Differential revision: https://reviews.llvm.org/D29442 llvm-svn: 294324
* [InstCombine] Make max size array combine a tunable.Davide Italiano2017-02-074-3/+13
| | | | | | | Requested by Sanjoy/Hal a while ago, and forgotten by me (r283612). llvm-svn: 294323
* [Hexagon] Update instruction typesKrzysztof Parzyszek2017-02-077-31/+77
| | | | | | | | | Remove TypeXTYPE, TypeALU32, TypeSYSTEM, TypeJR, and instead use their architecture counterparts. Patch by Colin LeMahieu. llvm-svn: 294321
* [Hexagon] Remove encoding bits from mapped instructionsKrzysztof Parzyszek2017-02-074-18/+48
| | | | | | | | | | - Map A2_zxtb to A2_andir. - Map PS_call_nr J2_call. - Map A2_tfr[t|f][new] to A2_padd[t|f][new]. Patch by Colin LeMahieu. llvm-svn: 294320
* Fix the bitcode upgrade for DIGlobalVariable in a DIImportedEntity context.Adrian Prantl2017-02-071-5/+51
| | | | | | | | | | | | | | | The bitcode upgrade for DIGlobalVariable unconditionally wrapped DIGlobalVariables in a DIGlobalVariableExpression. When a DIGlobalVariable is referenced by a DIImportedEntity, however, this is wrong. This patch fixes the bitcode upgrade by deferring the creation of DIGlobalVariableExpressions until we know the context of the DIGlobalVariable. <rdar://problem/30134279> Differential Revision: https://reviews.llvm.org/D29349 llvm-svn: 294318
* Revert "[GVNHoist] Merge DebugLoc metadata on hoisted instructions"Reid Kleckner2017-02-071-7/+0
| | | | | | | | | This reverts commit r294250. It caused PR31891. Add a test case that shows that inlinable calls retain location information with an accurate scope. llvm-svn: 294317
* [X86][SSE] Ensure that vector shift-by-immediate inputs are correctly ↵Simon Pilgrim2017-02-071-6/+10
| | | | | | | | | | bitcast to the result type vXi8/vXi64 vector shifts are often shifted as vYi16/vYi32 types but we weren't always remembering to bitcast the input. Tested with a new assert as we don't currently manipulate these shifts enough for test cases to catch them. llvm-svn: 294308
* [CodeGenPrepare] Hoist all getSubtargetImpl calls to the beginning of the passIgor Laevsky2017-02-071-22/+30
| | | | | | Differential Revision: https://reviews.llvm.org/D29456 llvm-svn: 294301
* [ARM] Make RWPI use movw/movt when availableChristof Douma2017-02-074-14/+45
| | | | | | | | | | | | | | | | | When constructing global address literals while targeting the RWPI relocation model. LLVM currently only uses literal pools. If MOVW/MOVT instructions are available we can use these instead. Beside being more efficient it allows -arm-execute-only to work with -relocation-model=RWPI as well. When we generate MOVW/MOVT for global addresses when targeting the RWPI relocation model, we need to use base relative relocations. This patch does the needed plumbing in MC to generate these for MOVW/MOVT. Differential Revision: https://reviews.llvm.org/D29487 Change-Id: I446786e43a6f5aa9b6a5bb2cd216d60d41c7755d llvm-svn: 294298
* [APInt] Fix rotl/rotr when the shift amount is greater than the total bit width.Joey Gouly2017-02-071-2/+15
| | | | | Review: https://reviews.llvm.org/D27749 llvm-svn: 294295
* Revert "[DAGCombiner] (add X, (adde Y, 0, Carry)) -> (adde X, Y, Carry)"Daniel Jasper2017-02-071-6/+0
| | | | | | | | | | | | | This reverts commit r294186. On an internal test, this triggers an out-of-memory error on PPC, presumably because there is another dagcombine that does the exact opposite triggering and endless loop consuming more and more memory. Chandler has started at creating a reduced test case and we'll attach it as soon as possible. llvm-svn: 294288
* [AVX-512] Add masked and unmasked shift by immediate instructions to load ↵Craig Topper2017-02-071-0/+81
| | | | | | folding tables. llvm-svn: 294287
* [AVX-512] Add masked shift instructions to load folding tables.Craig Topper2017-02-071-0/+108
| | | | | | This adds the masked versions of everything, but the shift by immediate instructions. llvm-svn: 294286
* [AVX-512] Add some of the shift instructions to the load folding tables.Craig Topper2017-02-071-0/+49
| | | | | | | | This includes unmasked forms of variable shift and shifting by the lower element of a register. Still need to do shift by immediate which was not foldable prior to avx512 and all the masked forms. llvm-svn: 294285
* AMDGPU: Fix missing staticMatt Arsenault2017-02-071-3/+4
| | | | llvm-svn: 294281
* [X86] Change the Defs list for VZEROALL/VZEROUPPER back to not including ↵Craig Topper2017-02-071-3/+2
| | | | | | YMM16-31. llvm-svn: 294277
* LowerTypeTests: Simplify. NFC.Peter Collingbourne2017-02-071-5/+3
| | | | llvm-svn: 294273
* [Hexagon] Address ASAN and UBSAN failures after r294226Krzysztof Parzyszek2017-02-074-16/+18
| | | | | | Reinstate r294256 with a fix. llvm-svn: 294269
* RegisterCoalescer: Fix joinReservedPhysReg()Matthias Braun2017-02-071-0/+5
| | | | | | | | | | | joinReservedPhysReg() can only deal with a liverange in a single basic block when copying from a vreg into a physreg. See also rdar://30306405 Differential Revision: https://reviews.llvm.org/D29436 llvm-svn: 294268
* Revert r293017 and fix the actual underlying issue.Chandler Carruth2017-02-072-2/+3
| | | | | | | | | | | | | | | | | | | | | The patch committed in r293017, as discussed on the list, doesn't really make sense but was causing an actual issue to go away. The issue turns out to be that in one place the extra template arguments were dropped from the OuterAnalysisManagerProxy. This in turn caused the types used in one set of places to access the key to be completely different from the types used in another set of places for both Loop and CGSCC cases where there are extra arguments. I have literally no idea how anything seemed to work with this bug in place. It blows my mind. But it did except for mingw64 in a DLL build. I've added a really handy static assert that helps ensure we don't break this in the future. It immediately diagnoses the issue with a compile failure and a very clear error message. Much better that staring at backtraces on a build bot. =] llvm-svn: 294267
* [AMDGPU] Lower null pointers in static variable initializerYaxun Liu2017-02-073-0/+39
| | | | | | | | | | | | For amdgcn target Clang generates addrspacecast to represent null pointers in private and local address spaces. In LLVM codegen, the static variable initializer is lowered by virtual function AsmPrinter::lowerConstant which is target generic. Since addrspacecast is target specific, AsmPrinter::lowerConst This patch overrides AsmPrinter::lowerConstant with AMDGPUAsmPrinter::lowerConstant, which is able to lower the target-specific addrspacecast in the null pointer representation so that -1 is co Differential Revision: https://reviews.llvm.org/D29284 llvm-svn: 294265
* [LVI] Switch from BFS to DFS exploration orderPhilip Reames2017-02-071-14/+16
| | | | | | | | | | | | | | This patch changes the order in which LVI explores previously unexplored paths. Previously, the code used an BFS strategy where each unexplored input was added to the search queue before any of them were explored. This has the effect of causing all inputs to be explored before returning to re-evaluate the merge point (non-local or phi node). This has the unfortunate property of doing redundant work if one of the inputs to the merge is found to be overdefined (i.e. unanalysable). If any input is overdefined, the result of the merge will be too; regardless of the values of other inputs. The new code uses a DFS strategy where we re-evaluate the merge after evaluating each input. If we discover an overdefined input, we immediately return without exploring other inputs. We have reports of large (4-10x) improvements of compile time with this patch and some reports of more precise analysis results as well. See the review discussion for details. The original motivating case was pr10584. Differential Revision: https://reviews.llvm.org/D28190 llvm-svn: 294264
* GlobalISel: legalize narrow G_SELECTS on AArch64.Tim Northover2017-02-062-1/+27
| | | | | | Otherwise there aren't any patterns to select them. llvm-svn: 294261
* Fix the samplepgo indirect call promotion bug: we should not promote a ↵Dehao Chen2017-02-061-1/+2
| | | | | | | | | | | | | | | | direct call. Summary: Checking CS.getCalledFunction() == nullptr does not necessary indicate indirect call. We also need to check if CS.getCalledValue() is not a constant. Reviewers: davidxl Reviewed By: davidxl Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D29570 llvm-svn: 294260
* Revert "[Hexagon] Address ASAN and UBSAN failures after r294226"Krzysztof Parzyszek2017-02-063-15/+13
| | | | | | | This reverts commit r294256. It seems to be causing more problems instead of solving them. llvm-svn: 294259
* [Hexagon] Adding gp+ to the syntax of gp-relative instructionsKrzysztof Parzyszek2017-02-062-9/+65
| | | | | | Patch by Colin LeMahieu. llvm-svn: 294258
* [AMDGPU] Fix GCNSchedStrategy.cpp debug outputStanislav Mekhanoshin2017-02-061-2/+2
| | | | | | | | There is typo in the debug output: top and bottom candidates are switched. Differential Revision: https://reviews.llvm.org/D29608 llvm-svn: 294257
* [Hexagon] Address ASAN and UBSAN failures after r294226Krzysztof Parzyszek2017-02-063-13/+15
| | | | llvm-svn: 294256
* Merge DebugLoc on combined stores; in this case, when combining storesPaul Robinson2017-02-061-1/+4
| | | | | | | | from the end of two blocks, merge instead of arbitrarily picking one. Differential Revision: http://reviews.llvm.org/D29504 llvm-svn: 294251
* [GVNHoist] Merge DebugLoc metadata on hoisted instructionsTaewook Oh2017-02-061-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: When instructions are hoisted, current implementation keeps DebugLoc metadata of the instruction that chosen as Repl (and its GEP operand if Repl is a load or a store). However, DebugLoc metadata should be updated to the 'merged' location across all hoisted instructions. See the following example code: ``` 1: typedef struct { 2: int a[10]; 3: } S1; 4: 5: extern S1 *s1[10]; 6: 7: void foo(int x, int y, int i) { 8: if (y) 9: s1[i]->a[i] = x + y; 10: else 11: s1[i]->a[i] = x; 12: } ``` Below is LLVM IR representation of the program before gvn-hoist: ``` %struct.S1 = type { [10 x i32] } @s1 = external local_unnamed_addr global [10 x %struct.S1*], align 16 define void @foo(i32 %x, i32 %y, i32 %i) !dbg !4 { entry: %tobool = icmp ne i32 %y, 0, !dbg !8 br i1 %tobool, label %if.then, label %if.else, !dbg !10 if.then: ; preds = %entry %add = add nsw i32 %x, %y, !dbg !11 %idxprom = sext i32 %i to i64, !dbg !12 %arrayidx = getelementptr inbounds [10 x %struct.S1*], [10 x %struct.S1*]* @s1, i64 0, i64 %idxprom, !dbg !12 %0 = load %struct.S1*, %struct.S1** %arrayidx, align 8, !dbg !12, !tbaa !13 %a = getelementptr inbounds %struct.S1, %struct.S1* %0, i32 0, i32 0, !dbg !17 br label %if.end, !dbg !12 if.else: ; preds = %entry %idxprom3 = sext i32 %i to i64, !dbg !18 %arrayidx4 = getelementptr inbounds [10 x %struct.S1*], [10 x %struct.S1*]* @s1, i64 0, i64 %idxprom3, !dbg !18 %1 = load %struct.S1*, %struct.S1** %arrayidx4, align 8, !dbg !18, !tbaa !13 %a5 = getelementptr inbounds %struct.S1, %struct.S1* %1, i32 0, i32 0, !dbg !19 br label %if.end if.end: ; preds = %if.else, %if.then %a5.sink = phi [10 x i32]* [ %a5, %if.else ], [ %a, %if.then ] %.sink = phi i32 [ %x, %if.else ], [ %add, %if.then ] %idxprom6 = sext i32 %i to i64 %arrayidx7 = getelementptr inbounds [10 x i32], [10 x i32]* %a5.sink, i64 0, i64 %idxprom6 store i32 %.sink, i32* %arrayidx7, align 4, !tbaa !20 ret void, !dbg !22 } ``` where ``` !11 = !DILocation(line: 9, column: 18, scope: !9) !12 = !DILocation(line: 9, column: 5, scope: !9) !18 = !DILocation(line: 11, column: 5, scope: !9) !19 = !DILocation(line: 11, column: 9, scope: !9) ``` . And below is after gvn-hoist: ``` define void @foo(i32 %x, i32 %y, i32 %i) !dbg !4 { entry: %tobool = icmp ne i32 %y, 0, !dbg !8 %idxprom = sext i32 %i to i64, !dbg !10 %0 = getelementptr inbounds [10 x %struct.S1*], [10 x %struct.S1*]* @s1, i64 0, i64 %idxprom, !dbg !10 %1 = load %struct.S1*, %struct.S1** %0, align 8, !dbg !10, !tbaa !11 br i1 %tobool, label %if.then, label %if.else, !dbg !15 if.then: ; preds = %entry %add = add nsw i32 %x, %y, !dbg !16 %arrayidx = getelementptr inbounds [10 x %struct.S1*], [10 x %struct.S1*]* @s1, i64 0, i64 %idxprom, !dbg !10 %a = getelementptr inbounds %struct.S1, %struct.S1* %1, i32 0, i32 0, !dbg !17 br label %if.end, !dbg !10 if.else: ; preds = %entry %arrayidx4 = getelementptr inbounds [10 x %struct.S1*], [10 x %struct.S1*]* @s1, i64 0, i64 %idxprom, !dbg !18 %a5 = getelementptr inbounds %struct.S1, %struct.S1* %1, i32 0, i32 0, !dbg !19 br label %if.end if.end: ; preds = %if.else, %if.then %a5.sink = phi [10 x i32]* [ %a5, %if.else ], [ %a, %if.then ] %.sink = phi i32 [ %x, %if.else ], [ %add, %if.then ] %arrayidx7 = getelementptr inbounds [10 x i32], [10 x i32]* %a5.sink, i64 0, i64 %idxprom store i32 %.sink, i32* %arrayidx7, align 4, !tbaa !20 ret void, !dbg !22 } ``` As you see, loads and their GEPs have been hosited from if.then/if.else block to entry block. However, DebugLoc metadata of these new instructions are still same as the instructions in if.then block, as they are moved/cloned from if.then block. This may result incorrect stepping and imprecise sample profile result. Reviewers: majnemer, pcc, sebpop Reviewed By: sebpop Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D29377 llvm-svn: 294250
* GlobalISel: fall back gracefully when we can't map an operand's size.Tim Northover2017-02-063-28/+40
| | | | | | | | AArch64 was asserting when it was asked to provide a register-bank of a size it couldn't deal with (in this case an s128 IMPLICIT_DEF). But we want a robust fallback path so this isn't allowed. llvm-svn: 294248
* GlobalISel: legalize G_INSERT instructionsTim Northover2017-02-063-0/+103
| | | | | | | We don't handle all cases yet (see arm64-fallback.ll for an example), but this is enough to cover most common C++ code so it's a good place to start. llvm-svn: 294247
OpenPOWER on IntegriCloud