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* [LV] Don't panic when encountering the IV of an outer loop.Michael Kuperstein2017-01-101-2/+7
| | | | | | | | | | | | | | | | | | Bail out instead of asserting when we encounter this situation, which can actually happen. The reason the test uses the new PM is that the "bad" phi, incidentally, gets cleaned up by LoopSimplify. But LICM can create this kind of phi and preserve loop simplify form, so the cleanup has no chance to run. This fixes PR31190. We may want to solve this in a less conservative manner, since this phi is actually uniform within the inner loop (or we may want LICM to output a cleaner promotion to begin with). Differential Revision: https://reviews.llvm.org/D28490 llvm-svn: 291589
* [PGO] Turn off comdat renaming in IR PGO by defaultRong Xu2017-01-103-15/+60
| | | | | | | | | | | | | | | | | | | | | | | Summary: In IR PGO we append the function hash to comdat functions to avoid the potential hash mismatch. This turns out not legal in some cases: if the comdat function is address-taken and used in comparison. Renaming changes the semantic. This patch turns off comdat renaming by default. To alleviate the hash mismatch issue, we now rename the profile variable for comdat functions. Profile allows co-existing multiple versions of profiles with different hash value. The inlined copy will always has the correct profile counter. The out-of-line copy might not have the correct count. But we will not have the bogus mismatch warning. Reviewers: davidxl Subscribers: llvm-commits, xur Differential Revision: https://reviews.llvm.org/D28416 llvm-svn: 291588
* [ARM] Remove rbit intrinsics and autoupgrade to generic bitreverse.Chad Rosier2017-01-102-6/+1
| | | | | | Testing already covered by CodeGen/ARM/rbit.ll llvm-svn: 291587
* AMDGPU: Add tests for HasMultipleConditionRegistersMatt Arsenault2017-01-101-0/+7
| | | | | | This was enabled without many specific tests or the comment. llvm-svn: 291586
* [X86][AVX512]Improving shuffle lowering by using AVX-512 EXPAND* instructions Michael Zuckerman2017-01-101-6/+115
| | | | | | | | | | | | | | | | | This patch fix PR31351: https://llvm.org/bugs/show_bug.cgi?id=31351 1. This patch adds new type of shuffle lowering 2. We can use the expand instruction, When the shuffle pattern is as following: { 0*a[0]0*a[1]...0*a[n] , n >=0 where a[] elements in a ascending order}. Reviewers: 1. igorb 2. guyblank 3. craig.topper 4. RKSimon Differential Revision: https://reviews.llvm.org/D28352 llvm-svn: 291584
* [SimplifyLibCalls] Propagate fast math flags while optimizing pow().Davide Italiano2017-01-101-1/+4
| | | | llvm-svn: 291577
* [AArch64] Add support for lowering bitreverse to the rbit instruction.Chad Rosier2017-01-103-4/+13
| | | | | | Differential Revision: https://reviews.llvm.org/D28379 llvm-svn: 291575
* [mips] Fix Mips MSA instrinsicsSimon Dardis2017-01-102-19/+139
| | | | | | | | | | | | | | | | The usage of some MIPS MSA instrinsics that took immediates could crash LLVM during lowering. This patch addresses that behaviour. Crucially this patch also makes the use of intrinsics with out of range immediates as producing an internal error. The ld,st instrinsics would trigger an assertion failure for MIPS64 as their lowering would attempt to add an i32 offset to a i64 pointer. Reviewers: vkalintiris, slthakur Differential Revision: https://reviews.llvm.org/D25438 llvm-svn: 291571
* [mips] Honour -mno-odd-spreg for vector splat (again)Simon Dardis2017-01-101-2/+6
| | | | | | | | | | | | | | | | | | | | Previous the lowering of FILL_FW would use the MSA128W register class when performing a vector splat. Instead it should be honouring -mno-odd-spreg and only use the even registers when performing a splat from word to vector register. Logical follow-on from r230235. This fixes PR/31369. A previous commit was missing the test case and had another differential in it. Reviewers: slthakur Differential Revision: https://reviews.llvm.org/D28373 llvm-svn: 291566
* Revert "[mips] Honour -mno-odd-spreg for vector splat"Simon Dardis2017-01-102-18/+2
| | | | | | | This reverts commit r291556. It was a mixture of two differentials and was missing a test. llvm-svn: 291562
* RuntimeDyldELF: implement R_AARCH64_PREL64 relocEugene Leviant2017-01-101-0/+3
| | | | | | Differential revision: https://reviews.llvm.org/D28122 llvm-svn: 291558
* [mips] Honour -mno-odd-spreg for vector splatSimon Dardis2017-01-102-2/+18
| | | | | | | | | | | | | | | | | Previous the lowering of FILL_FW would use the MSA128W register class when performing a vector splat. Instead it should be honouring -mno-odd-spreg and only use the even registers when performing a splat from word to vector register. Logical follow-on from r230235. This fixes PR/31369. Reviewers: slthakur Differential Revision: https://reviews.llvm.org/D28373 llvm-svn: 291556
* [DAGCombiner] Merge together duplicate checks for folding fold (select C, 1, ↵Craig Topper2017-01-101-10/+4
| | | | | | | | X) -> (or C, X) and folding (select C, X, 0) -> (and C, X). Also be consistent about checking that both the condition and the result type are i1. NFC I guess previously we just assumed if the result type was i1, then the condition type must also be i1? llvm-svn: 291548
* [ObjectYAML] Support for DWARF line tablesChris Bieneman2017-01-101-10/+57
| | | | | | | | | | | | | | One more try... relanding r291541 with a fix to properly gate MaxOpsPerInst on DWARF version. Description from r291541: This patch re-lands r291470, which failed on Linux bots. The issue (I believe) was undefined behavior because the size of llvm::dwarf::LineNumberOps was not explcitly specified or consistently respected. The updated patch adds an explcit underlying type to the enum and preserves the size more correctly. Original description: This patch adds support for the DWARF debug_lines section. The line table state machine opcodes are preserved, so this can be used to test the state machine evaluation directly. llvm-svn: 291546
* AMD family 17h (znver1) enablementCraig Topper2017-01-102-0/+55
| | | | | | | | | | | | | | | | | | | | | | | Summary: This patch enables the following 1. AMD family 17h architecture using "znver1" tune flag (-march, -mcpu). 2. ISAs that are enabled for "znver1" architecture. 3. Checks ADX isa from cpuid to identify "znver1" flag when -march=native is used. 4. ISAs FMA4, XOP are disabled as they are dropped from amdfam17. 5. For the time being, it uses the btver2 scheduler model. 6. Test file is updated to check this flag. This item is linked to clang review item https://reviews.llvm.org/D28018 Patch by Ganesh Gopalasubramanian Reviewers: RKSimon, craig.topper Subscribers: vprasad, RKSimon, ashutosh.nema, llvm-commits Differential Revision: https://reviews.llvm.org/D28017 llvm-svn: 291543
* Revert "[ObjectYAML] Support for DWARF line tables"Chris Bieneman2017-01-101-56/+10
| | | | | | | | | | This reverts commit r291541. Still failing on a bot: http://bb.pgr.jp/builders/cmake-llvm-x86_64-linux/builds/47224/steps/test_llvm/logs/stdio llvm-svn: 291542
* [ObjectYAML] Support for DWARF line tablesChris Bieneman2017-01-101-10/+56
| | | | | | | | | | This patch re-lands r291470, which failed on Linux bots. The issue (I believe) was undefined behavior because the size of llvm::dwarf::LineNumberOps was not explcitly specified or consistently respected. The updated patch adds an explcit underlying type to the enum and preserves the size more correctly. Original description: This patch adds support for the DWARF debug_lines section. The line table state machine opcodes are preserved, so this can be used to test the state machine evaluation directly. llvm-svn: 291541
* [X86] When lowering uniform shifts, use X86ISD::VZEXT instead of using a ↵Craig Topper2017-01-101-4/+4
| | | | | | | | ZERO_EXTEND_VECTOR_INREG. If we emit the ZERO_EXTEND_VECTOR_INREG too late it doesn't get lowered properly and makes it through to isel and fails. Fixes PR31593. llvm-svn: 291535
* [DAGCombiner] Remove code for optimizing select (xor Cond, 0), X, Y -> ↵Craig Topper2017-01-101-4/+0
| | | | | | select Cond, X, Y. Just let combine on the xor itself take care of it. llvm-svn: 291534
* Fix a typo and also test a new machine for commit. NFC.Xin Tong2017-01-101-1/+1
| | | | llvm-svn: 291532
* [StructurizeCfg] Update dominator info.Serge Pavlov2017-01-101-0/+1
| | | | | | | | | | | | | | In some cases StructurizeCfg updates root node, but dominator info remains unchanges, it causes crash when expensive checks are enabled. To cope with this problem a new method was added to DominatorTreeBase that allows adding new root nodes, it is called in StructurizeCfg to put dominator tree in sync. This change fixes PR27488. Differential Revision: https://reviews.llvm.org/D28114 llvm-svn: 291530
* [CodeGen] Implement the SUnit::print() methodEvandro Menezes2017-01-101-9/+9
| | | | | | | | | | This method seems to have had a troubled life. This patch proposes that it replaces the recently added helper function dumpSUIdentifier. This way, the method can be used in other files using the SUnit class. Differential revision: https://reviews.llvm.org/D28488 llvm-svn: 291520
* [ThinLTO] Hash more part of the config to build cache entriesMehdi Amini2017-01-101-2/+34
| | | | | | | This has been fixed in the "new" LTO API used by Gold/LLD, this is fixing the same issue in the libLTO API used by ld64 (amongst other) llvm-svn: 291518
* Add an assert for hasLoopInvariantOperandsXin Tong2017-01-101-0/+3
| | | | | | | | | | | | Summary: Add an assert for hasLoopInvariantOperands Reviewers: danielcdh, sanjoy Subscribers: mzolotukhin, llvm-commits Differential Revision: https://reviews.llvm.org/D28501 llvm-svn: 291516
* [WebAssembly] Add return type annotations in fast isel.Dan Gohman2017-01-091-0/+3
| | | | llvm-svn: 291498
* TarWriter: Fix a bug in Ustar header.Rui Ueyama2017-01-091-1/+1
| | | | | | | | | | If we split a filename into `Name` and `Prefix`, `Prefix` is at most 145 bytes. We had a bug that didn't split a path correctly. This bug was pointed out by Rafael in the post commit review. This patch adds a unit test for TarWriter to verify the fix. llvm-svn: 291494
* [NVPTX] Fix some Clang-tidy modernize and Include What You Use warnings; ↵Eugene Zelenko2017-01-098-167/+227
| | | | | | other minor fixes (NFC). llvm-svn: 291490
* Refactor inline threshold update code.Easwaran Raman2017-01-091-22/+19
| | | | | | | | | | Functional change: Previously, if a callee is cold, we used ColdThreshold if it minimizes the existing threshold. This was irrespective of whether we were optimizing for minsize (-Oz) or not. But -Oz uses very low threshold to begin with and the inlining with -Oz is expected to be tuned for lowering code size, so there is no good reason to set an even lower threshold for cold callees. We now lower the threshold for cold callees only when -Oz is not used. For default values of -inlinethreshold and -inlinecold-threshold, this change has no effect and this simplifies the code. NFC changes: Group all threshold updates that are guarded by !Caller->optForMinSize() and within that group threshold updates that require profile summary info. Differential revision: https://reviews.llvm.org/D28369 llvm-svn: 291487
* [SimplifyLibCalls] pow(x, -0.5) -> 1.0 / sqrt(x).Davide Italiano2017-01-091-0/+18
| | | | | | Differential Revision: https://reviews.llvm.org/D28479 llvm-svn: 291486
* Support outputting to /dev/null.Rafael Espindola2017-01-091-22/+44
| | | | | | | | When writing to a non regular file we cannot rename to it. Since we have to write, we may as well create a temporary file to avoid trying to create an unique file in /dev when trying to write to /dev/null. llvm-svn: 291485
* PeepholeOptimizer: Do not replace SubregToReg(bitcast like)Matthias Braun2017-01-091-1/+10
| | | | | | | | | | | While we can usually replace bitcast like instructions (MachineInstr::isBitcast()) with a COPY this is not legal if any of the users uses SUBREG_TO_REG to assert the upper bits of the result are zero. Differential Revision: https://reviews.llvm.org/D28474 llvm-svn: 291483
* MachineInstr: Print name for subreg index in SUBREG_TO_REGMatthias Braun2017-01-091-1/+2
| | | | | | | | SUBREG_TO_REG takes a subregister index as 3rd operand, print the name instead of a number. We already do the same for INSERT_SUBREG and REG_SEQUENCE. llvm-svn: 291481
* TarWriter: Set "00" to Ustar version field.Rui Ueyama2017-01-091-5/+10
| | | | | | | | Most (maybe all?) tar commands can handle tar archives with blank version fields, but POSIX requires "00" to be set to the field, so doing it is good for compliance. llvm-svn: 291479
* Revert r291092 because it introduces a crash.Michael Kuperstein2017-01-091-63/+0
| | | | | | See PR31589 for details. llvm-svn: 291478
* X86-specific path: Implemented the fusing of MUL+ADDSUB to FMADDSUB.Vyacheslav Klochkov2017-01-091-41/+154
| | | | | | Differential Revision: https://reviews.llvm.org/D28087 llvm-svn: 291473
* Revert "[ObjectYAML] Support for DWARF line tables"Chris Bieneman2017-01-091-56/+10
| | | | | | | | This reverts commit r291470 due to failing bots: http://bb.pgr.jp/builders/cmake-llvm-x86_64-linux/builds/47209/steps/test_llvm/logs/stdio llvm-svn: 291471
* [ObjectYAML] Support for DWARF line tablesChris Bieneman2017-01-091-10/+56
| | | | | | This patch adds support for the DWARF debug_lines section. The line table state machine opcodes are preserved, so this can be used to test the state machine evaluation directly. llvm-svn: 291470
* [LV] Fix-up external IV users after updating dominator treeMatthew Simpson2017-01-091-7/+20
| | | | | | | | | | | | | This patch delays the fix-up step for external induction variable users until after the dominator tree has been properly updated. This should fix PR30742. The SCEVExpander in InductionDescriptor::transform can generate code in the wrong location if the dominator tree is not up-to-date. We should work towards keeping the dominator tree up-to-date throughout the transformation. Reference: https://llvm.org/bugs/show_bug.cgi?id=30742 Differential Revision: https://reviews.llvm.org/D28168 llvm-svn: 291462
* AMDGPU: Add Assert[SZ]Ext during argument load creationMatt Arsenault2017-01-092-13/+17
| | | | | | | | | | | For i16 zeroext arguments when i16 was a legal type, the known bits information from the truncate was lost. Insert a zeroext so the known bits optimizations work with the 32-bit loads. Fixes code quality regressions vs. SI in min.ll test. llvm-svn: 291461
* Reapply r291025 ("AMDGPU: Remove unneccessary intermediate vector")Matt Arsenault2017-01-091-19/+33
| | | | llvm-svn: 291460
* Intrinsic::Bitreverse is safe to speculateXin Tong2017-01-091-0/+1
| | | | | | | | | | | | Summary: Intrinsic::Bitreverse is safe to speculate Reviewers: hfinkel, mkuper, arsenm, jmolloy Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D28471 llvm-svn: 291456
* In the below scenario, we must be able to skip the a DBG_VALUE instruction andSumanth Gundapaneni2017-01-091-3/+8
| | | | | | | | | | | | | | | remove the dead store. %vreg0<def> = L2_loadri_io <fi#15>, 0; mem:LD4[%dataF](align=4) DBG_VALUE %vreg0, %noreg, !"dataF", <!184>; IntRegs:%vreg0 S2_storeri_io <fi#15>, 0, %vreg0; mem:ST4[%dataF] In reality, this kind of stores are eliminated before Stack Slot Coloring pass, possibly in instruction lowering Differential Revision: https://reviews.llvm.org/D26616 llvm-svn: 291455
* [X86][AVX512] Enable v16i8/v32i8 vector shifts to use an ↵Simon Pilgrim2017-01-091-14/+17
| | | | | | | | | | extend+shift+truncate pattern. Use the existing AVX2 v8i16 vector shift lowering for v16i8 (extending to v16i32) on AVX512 targets and v32i8 (extending to v32i16) on AVX512BW targets. Cost model updates to follow. llvm-svn: 291451
* fix comment typos; NFCSanjay Patel2017-01-091-5/+5
| | | | llvm-svn: 291447
* [X86][AVX512DQ] Enable v16i16 vector shifts to use an extend+shift+truncate ↵Simon Pilgrim2017-01-091-3/+4
| | | | | | | | | | pattern. Use the existing AVX2 v8i16 vector shift lowering for v16i16 on AVX512 targets (AVX512BW will have already have lowered with vpsravw). Cost model updates to follow. llvm-svn: 291445
* Some formatting in TargetMachineC. NFCAmaury Sechet2017-01-091-2/+2
| | | | llvm-svn: 291442
* [SelectionDAG] Fix in legalization of UMAX/SMAX/UMIN/SMIN. Solves PR31486.Bjorn Pettersson2017-01-091-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | Summary: Originally i64 = umax t8, Constant:i64<4> was expanded into i32,i32 = umax Constant:i32<0>, Constant:i32<0> i32,i32 = umax t7, Constant:i32<4> Now instead the two produced umax:es return i32 instead of i32, i32. Thanks to Jan Vesely for help with the test case. Patch by mikael.holmen at ericsson.com Reviewers: bogner, jvesely, tstellarAMD, arsenm Subscribers: test, wdng, RKSimon, arsenm, nhaehnle, llvm-commits Differential Revision: https://reviews.llvm.org/D28135 llvm-svn: 291441
* Fix MSVC build failure introduced in r291431Pavel Labath2017-01-091-4/+3
| | | | | | | MSVC does not like to reinterpret_cast to a uint64_t. Use a different cast instead. llvm-svn: 291435
* RuntimeDyldELF: don't create thunk if not neededEugene Leviant2017-01-092-1/+47
| | | | | | | | | | | | | This patch doesn't create thunk for branch operation when following conditions are met: - Architecture is AArch64 - Relocation target is in the same object file - Relocation target is close enough to be encoded in immediate offset In such case we branch directly to the target instead of branching to thunk Differential revision: https://reviews.llvm.org/D28108 llvm-svn: 291431
* [PM] Teach SCEV to invalidate itself when its dependencies becomeChandler Carruth2017-01-091-0/+12
| | | | | | | | | | | | | invalid. This fixes use-after-free bugs that will arise with any interesting use of SCEV. I've added a dedicated test that works diligently to trigger these kinds of bugs in the new pass manager and also checks for them explicitly as well as triggering ASan failures when things go squirly. llvm-svn: 291426
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