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* Teach DIEInteger to emit FORM_strp and FORM_ref_addr attributes.Frederic Riss2015-03-041-0/+10
| | | | | | | | To be used/tested by llvm-dsymutil. (llvm-dsymutil does a 'static' link, no need for relocations for most things, so it'll just emit raw integers for most attributes) llvm-svn: 231298
* Expand variables when evaluating absolute expressions.Rafael Espindola2015-03-041-1/+1
| | | | | | | This allows for variables to be used in .size. This matches gnu AS functionality. llvm-svn: 231295
* Support standard DWARF TLS opcode; Darwin and PS4 use it.Paul Robinson2015-03-043-2/+17
| | | | | | Differential Revision: http://reviews.llvm.org/D8018 llvm-svn: 231286
* Add LLVM support for PPC cryptography builtinsNemanja Ivanovic2015-03-0410-1/+143
| | | | | | Review: http://reviews.llvm.org/D7955 llvm-svn: 231285
* Try to satisfy sanitizer lint checkReid Kleckner2015-03-041-1/+0
| | | | llvm-svn: 231284
* Add a lock() function in PassRegistry to speed up multi-thread synchronization.Erik Eckstein2015-03-041-2/+18
| | | | | | | | | | When calling lock() after all passes are registered, the PassRegistry doesn't need a mutex anymore to look up passes. This speeds up multithreaded llvm execution by ~5% (tested with 4 threads). In an asserts build of llvm this has an even bigger impact. Note that it's not required to use the lock function. llvm-svn: 231276
* Make DataLayout Non-Optional in the ModuleMehdi Amini2015-03-0483-466/+271
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: DataLayout keeps the string used for its creation. As a side effect it is no longer needed in the Module. This is "almost" NFC, the string is no longer canonicalized, you can't rely on two "equals" DataLayout having the same string returned by getStringRepresentation(). Get rid of DataLayoutPass: the DataLayout is in the Module The DataLayout is "per-module", let's enforce this by not duplicating it more than necessary. One more step toward non-optionality of the DataLayout in the module. Make DataLayout Non-Optional in the Module Module->getDataLayout() will never returns nullptr anymore. Reviewers: echristo Subscribers: resistor, llvm-commits, jholewinski Differential Revision: http://reviews.llvm.org/D7992 From: Mehdi Amini <mehdi.amini@apple.com> llvm-svn: 231270
* Revert "unique_ptrify ValID::ConstantStructElts"Reid Kleckner2015-03-042-17/+11
| | | | | | | | | | | | | | | | | | | | | This reverts r231200 and r231204. The second one added an explicit move ctor for MSVC. This change broke the clang-cl self-host due to weirdness in MSVC's implementation of std::map::insert. Somehow we lost our rvalue ref-ness when going through variadic placement new: template <class _Objty, class... _Types> void construct(_Objty *_Ptr, _Types &&... _Args) { // construct _Objty(_Types...) at _Ptr ::new ((void *)_Ptr) _Objty(_STD forward<_Types>(_Args)...); } For some reason, Clang decided to call the deleted std::pair copy constructor at this point. Needs further investigation, once I can build. llvm-svn: 231269
* Revert the test commit.Wei Mi2015-03-041-1/+0
| | | | llvm-svn: 231264
* Test commit. It will be reverted in the next commit.Wei Mi2015-03-041-0/+1
| | | | llvm-svn: 231262
* Fix DwarfExpression::AddMachineRegExpression so it doesn't read past theAdrian Prantl2015-03-042-13/+17
| | | | | | | end of an expression that ends with DW_OP_plus. Caught by the ASAN build bots. llvm-svn: 231260
* R600/SI: Add an intrinsic for S_FLBIT_I32 / V_FFBH_I32Marek Olsak2015-03-043-1/+5
| | | | | | Required by OpenGL (ARB_gpu_shader5). llvm-svn: 231259
* Test commit. Removed an unnecessary spaceNemanja Ivanovic2015-03-041-1/+1
| | | | llvm-svn: 231257
* Mutate TargetLowering::shouldExpandAtomicRMWInIR to specifically dictate how ↵JF Bastien2015-03-047-22/+49
| | | | | | | | | | | | | | | | | | | | | AtomicRMWInsts are expanded. Summary: In PNaCl, most atomic instructions have their own @llvm.nacl.atomic.* function, each one, with a few exceptions, represents a consistent behaviour across all NaCl-supported targets. Unfortunately, the atomic RMW operations nand, [u]min, and [u]max aren't directly represented by any such @llvm.nacl.atomic.* function. This patch refines shouldExpandAtomicRMWInIR in TargetLowering so that a future `Le32TargetLowering` class can selectively inform the caller how the target desires the atomic RMW instruction to be expanded (ie via load-linked/store-conditional for ARM/AArch64, via cmpxchg for X86/others?, or not at all for Mips) if at all. This does not represent a behavioural change and as such no tests were added. Patch by: Richard Diamond. Reviewers: jfb Reviewed By: jfb Subscribers: jfb, aemerson, t.p.northover, llvm-commits Differential Revision: http://reviews.llvm.org/D7713 llvm-svn: 231250
* [mips][microMIPS] Make usage of ADDU16 and SUBU16 by code generatorJozef Kolek2015-03-042-3/+6
| | | | | | Differential Revision: http://reviews.llvm.org/D7609 llvm-svn: 231249
* [PowerPC] Remove unnecessary and incomplete commentaryBill Schmidt2015-03-041-412/+0
| | | | | | | | | | This "itinerary class map" in PPCSchedule.td is incomplete and redundant with the actual code. As it provides no value, we've decided to remove it. No functional change. llvm-svn: 231246
* [X86][FastISel] Simplify the logic in method X86SelectSIToFP.Andrea Di Biagio2015-03-041-21/+13
| | | | | | | | | | | | | | | | The target-independent selection algorithm in FastISel already knows how to select a SINT_TO_FP if the target is SSE but not AVX. On targets that have SSE but not AVX, the tablegen'd 'fastEmit' functions for ISD::SINT_TO_FP know how to select instruction X86::CVTSI2SSrr (for an i32 to f32 conversion) and X86::CVTSI2SDrr (for an i32 to f64 conversion). This patch simplifies the logic in method X86SelectSIToFP knowing that the code would not be reachable if the subtarget doesn't have AVX. No functional change intended. llvm-svn: 231243
* asan: do not instrument direct inbounds accesses to stack variablesDmitry Vyukov2015-03-041-263/+285
| | | | | | | | | | | | | | | Do not instrument direct accesses to stack variables that can be proven to be inbounds, e.g. accesses to fields of structs on stack. But it eliminates 33% of instrumentation on webrtc/modules_unittests (number of memory accesses goes down from 290152 to 193998) and reduces binary size by 15% (from 74M to 64M) and improved compilation time by 6-12%. The optimization is guarded by asan-opt-stack flag that is off by default. http://reviews.llvm.org/D7583 llvm-svn: 231241
* [mips] Rename the LA/LI/DLI TableGen definitions and classes. NFC.Toma Tabacu2015-03-043-16/+17
| | | | | | | | | | | | | | | | Summary: Use more reasonable names for these pseudo-instructions. As there's only one definition tied to any one of these classes, I named them with abbreviated versions of their respective class' name. Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D7831 llvm-svn: 231240
* [mips] Keep the parameter list of Filler::searchRange() consistent. NFC.Vasileios Kalintiris2015-03-041-9/+9
| | | | | | | | | | | | | | Summary: Move the "Filler" parameter to the end of the parameter list as it is, conceptually, the only output parameter of that function. Reviewers: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D7726 llvm-svn: 231239
* [MBP] Fix a really horrible bug in MachineBlockPlacement, but behindChandler Carruth2015-03-041-0/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | a flag for now. First off, thanks to Daniel Jasper for really pointing out the issue here. It's been here forever (at least, I think it was there when I first wrote this code) without getting really noticed or fixed. The key problem is what happens when two reasonably common patterns happen at the same time: we outline multiple cold regions of code, and those regions in turn have diamonds or other CFGs for which we can't just topologically lay them out. Consider some C code that looks like: if (a1()) { if (b1()) c1(); else d1(); f1(); } if (a2()) { if (b2()) c2(); else d2(); f2(); } done(); Now consider the case where a1() and a2() are unlikely to be true. In that case, we might lay out the first part of the function like: a1, a2, done; And then we will be out of successors in which to build the chain. We go to find the best block to continue the chain with, which is perfectly reasonable here, and find "b1" let's say. Laying out successors gets us to: a1, a2, done; b1, c1; At this point, we will refuse to lay out the successor to c1 (f1) because there are still un-placed predecessors of f1 and we want to try to preserve the CFG structure. So we go get the next best block, d1. ... wait for it ... Except that the next best block *isn't* d1. It is b2! d1 is waaay down inside these conditionals. It is much less important than b2. Except that this is exactly what we didn't want. If we keep going we get the entire set of the rest of the CFG *interleaved*!!! a1, a2, done; b1, c1; b2, c2; d1, f1; d2, f2; So we clearly need a better strategy here. =] My current favorite strategy is to actually try to place the block whose predecessor is closest. This very simply ensures that we unwind these kinds of CFGs the way that is natural and fitting, and should minimize the number of cache lines instructions are spread across. It also happens to be *dead simple*. It's like the datastructure was specifically set up for this use case or something. We only push blocks onto the work list when the last predecessor for them is placed into the chain. So the back of the worklist *is* the nearest next block. Unfortunately, a change like this is going to cause *soooo* many benchmarks to swing wildly. So for now I'm adding this under a flag so that we and others can validate that this is fixing the problems described, that it seems possible to enable, and hopefully that it fixes more of our problems long term. llvm-svn: 231238
* [mips] Specify the correct value type when combining a CMovFP node.Vasileios Kalintiris2015-03-041-4/+2
| | | | | | | | | This commit fixes a bug introduced in r230956 where we were creating CMovFP_{T,F} nodes with multiple return value types (one for each operand). With this change the return value type of the new node is the same as the value type of the True/False operands of the original node. llvm-svn: 231237
* Add a flag to experiment with outlining optional branches.Daniel Jasper2015-03-041-2/+46
| | | | | | | | | | | | | In a CFG with the edges A->B->C and A->C, B is an optional branch. LLVM's default behavior is to lay the blocks out naturally, i.e. A, B, C, in order to improve code locality and fallthroughs. However, if a function contains many of those optional branches only a few of which are taken, this leads to a lot of unnecessary icache misses. Moving B out of line can work around this. Review: http://reviews.llvm.org/D7719 llvm-svn: 231230
* Fix PR22408 - LLVM producing AArch64 TLS relocations that GNU linkers cannot ↵Kristof Beyls2015-03-047-132/+164
| | | | | | | | | | | | | | | | | | | | | | | | | | | handle yet. As is described at http://llvm.org/bugs/show_bug.cgi?id=22408, the GNU linkers ld.bfd and ld.gold currently only support a subset of the whole range of AArch64 ELF TLS relocations. Furthermore, they assume that some of the code sequences to access thread-local variables are produced in a very specific sequence. When the sequence is not as the linker expects, it can silently mis-relaxe/mis-optimize the instructions. Even if that wouldn't be the case, it's good to produce the exact sequence, as that ensures that linkers can perform optimizing relaxations. This patch: * implements support for 16MiB TLS area size instead of 4GiB TLS area size. Ideally clang would grow an -mtls-size option to allow support for both, but that's not part of this patch. * by default doesn't produce local dynamic access patterns, as even modern ld.bfd and ld.gold linkers do not support the associated relocations. An option (-aarch64-elf-ldtls-generation) is added to enable generation of local dynamic code sequence, but is off by default. * makes sure that the exact expected code sequence for local dynamic and general dynamic accesses is produced, by making use of a new pseudo instruction. The patch also removes two (AArch64ISD::TLSDESC_BLR, AArch64ISD::TLSDESC_CALL) pre-existing AArch64-specific pseudo SDNode instructions that are superseded by the new one (TLSDESC_CALLSEQ). llvm-svn: 231227
* [DAGCombine] Fix a bug in a BUILD_VECTOR combineMichael Kuperstein2015-03-041-2/+3
| | | | | | | | | | When trying to convert a BUILD_VECTOR into a shuffle, we try to split a single source vector that is twice as wide as the destination vector. We can not do this when we also need the zero vector to create a blend. This fixes PR22774. Differential Revision: http://reviews.llvm.org/D8040 llvm-svn: 231219
* [MC][Target] Implement support for R_X86_64_SIZE{32,64}.Davide Italiano2015-03-042-0/+8
| | | | | | | Differential Revision: D7990 Reviewed by: rafael, majnemer llvm-svn: 231216
* [llvm-pdbdump] Display full enum definitions.Zachary Turner2015-03-042-2/+14
| | | | | | | | | | | This will now display enum definitions both at the global scope as well as nested inside of classes. Additionally, it will no longer display enums at the global scope if the enum is nested. Instead, it will omit the definition of the enum globally and instead emit it in the corresponding class definition. llvm-svn: 231215
* Move emitDIE and emitAbbrevs to AsmPrinter. NFC.Frederic Riss2015-03-045-68/+66
| | | | | | | | | | | | | | (They are called emitDwarfDIE and emitDwarfAbbrevs in their new home) llvm-dsymutil wants to reuse that code, but it doesn't have a DwarfUnit or a DwarfDebug object to call those. It has access to an AsmPrinter though. Having emitDIE in the AsmPrinter also removes the DwarfFile dependency on DwarfDebug, and thus the patch drops that field. Differential Revision: http://reviews.llvm.org/D8024 llvm-svn: 231210
* Constify AsmPrinter passed to DIE methods.Frederic Riss2015-03-041-22/+22
| | | | llvm-svn: 231209
* Workaround MSVC not providing implicit move membersDavid Blaikie2015-03-041-0/+8
| | | | llvm-svn: 231204
* Use report_fatal_error instead of unreachable for -fast-isel-abortMehdi Amini2015-03-041-3/+3
| | | | | | | Suggestion by Andrea Di Biagio From: Mehdi Amini <mehdi.amini@apple.com> llvm-svn: 231201
* unique_ptrify ValID::ConstantStructEltsDavid Blaikie2015-03-042-11/+9
| | | | llvm-svn: 231200
* LLParser: Avoid copying ValIDs, the copy ctor is deprecated in C++11 due to ↵David Blaikie2015-03-041-1/+6
| | | | | | the presence of a user-declared dtor llvm-svn: 231199
* Use the vanilla func_end symbol for .size.Rafael Espindola2015-03-041-7/+4
| | | | | | No need to create yet another temp symbol. llvm-svn: 231198
* Remove MCStreamer include which isn't used here. NFCPete Cooper2015-03-041-1/+0
| | | | llvm-svn: 231195
* This file should always have included MCAssembler and not MCStreamer. NFCPete Cooper2015-03-041-1/+1
| | | | llvm-svn: 231194
* Remove MCStreamer.h include from MCContext.h and explictly include it where ↵Pete Cooper2015-03-046-0/+6
| | | | | | necessary. NFC llvm-svn: 231193
* Recommit r231168: unique_ptrify LiveRange::segmentSetDavid Blaikie2015-03-042-3/+4
| | | | | | | | | | | | | | | | | | | | | | | GCC 4.7's libstdc++ doesn't have std::map::emplace, but it does have std::unordered_map::emplace, and the use case here doesn't appear to need ordering. The container has been changed in a separate/precursor patch, and now this patch should hopefully build cleanly even with GCC 4.7. & then I realized the order of the container did matter, so extra handling of ordering was added in r231189. Original commit message: This makes LiveRange non-copyable, and LiveInterval is already non-movable (due to the explicit dtor), so now it's non-copyable and non-movable. Fix the one case where we were relying on the (deprecated in C++11) implicit copy ctor of LiveInterval (which happened to work because the ctor created an object with a null segmentSet, so double-deleting the null pointer was fine). llvm-svn: 231192
* Recommit r231175: Change LiveStackAnalysis::SS2IntervalMap from std::map to ↵David Blaikie2015-03-041-2/+10
| | | | | | | | | | | | | | | | std::unordered_map The order of this container was needed at one point - so, at that point create a temporary array of pointers, sort those, then iterate them. This keeps lookup efficient (& the lesser issue, of allowing the use of emplace... ), object identity preserved, and ordered iteration in the one place that requires it. While this has no functional change, I realize it does mean allocating an extra data structure and performing a sort - so if this looks suspect to anyone regarding perf characteristics, I'm all ears. llvm-svn: 231189
* RegisterCoalescer: Gracefully continue if subrange merging fails.Matthias Braun2015-03-041-18/+48
| | | | | | | | | | | There is a known bug where the register coalescer fails to merge subranges when multiple ranges end up in the "overflow" bit 32 of the lanemasks. A proper fix for this is complicated so for now this is a workaround which lets the register coalescer drop the subregister liveness information (we just loose some precision by that) and continue. llvm-svn: 231186
* Drop the "eh_" from eh_func_begin and eh_func_end.Rafael Espindola2015-03-041-2/+2
| | | | | | They will be used for more than eh tables. llvm-svn: 231185
* Revert "unique_ptrify LiveRange::segmentSet"David Blaikie2015-03-042-4/+3
| | | | | | | | Apparently something does care about ordering of LiveIntervals... so revert all that stuff (r231175, r231176, r231177) & take some time to re-evaluate. llvm-svn: 231184
* [RewriteStatepointsForGC] Fix a relocation bug w.r.t values defined by ↵Philip Reames2015-03-041-2/+12
| | | | | | | | | | | | | | | invoke instructions RewriteStatepointsForGC pass emits an alloca for each GC pointer which will be relocated. It then inserts stores after def and all relocations, and inserts loads before each use as well. In the end, mem2reg is used to update IR with relocations in SSA form. However, there is a problem with inserting stores for values defined by invoke instructions. The code didn't expect a def was a terminator instruction, and inserting instructions after these terminators resulted in malformed IR. This patch fixes this problem by handling invoke instructions as a special case. If the def is an invoke instruction, the store will be inserted at the beginning of the normal destination block. Since return value from invoke instruction does not dominate the unwind destination block, no action is needed there. Patch by: Chen Li Differential Revision: http://reviews.llvm.org/D7923 llvm-svn: 231183
* Remove 'llvm.x86.avx2.vbroadcasti128' intrinsic.Juergen Ributzka2015-03-042-5/+12
| | | | | | | | | | | The intrinsic is no longer generated by the front-end. Remove the intrinsic and auto-upgrade it to a vector shuffle. Reviewed by Nadav This is related to rdar://problem/18742778. llvm-svn: 231182
* Recommit r231168: unique_ptrify LiveRange::segmentSetDavid Blaikie2015-03-032-3/+4
| | | | | | | | | | | | | | | | | | | | GCC 4.7's libstdc++ doesn't have std::map::emplace, but it does have std::unordered_map::emplace, and the use case here doesn't appear to need ordering. The container has been changed in a separate/precursor patch, and now this patch should hopefully build cleanly even with GCC 4.7. Original commit message: This makes LiveRange non-copyable, and LiveInterval is already non-movable (due to the explicit dtor), so now it's non-copyable and non-movable. Fix the one case where we were relying on the (deprecated in C++11) implicit copy ctor of LiveInterval (which happened to work because the ctor created an object with a null segmentSet, so double-deleting the null pointer was fine). llvm-svn: 231176
* Revert "unique_ptrify LiveRange::segmentSet"David Blaikie2015-03-032-4/+3
| | | | | | | | GCC 4.7 *shakes fist* (doesn't have std::map::emplace... ) This reverts commit r231168. llvm-svn: 231173
* Move TargetLibraryInfo data from two files into one common .def file.Jan Wen Voung2015-03-031-330/+2
| | | | | | | | | | | | | | | Summary: This makes it more obvious that the enum definition and the "StandardName" array is in sync. Mechanically refactored w/ a python script. Test Plan: still compiles Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D7845 llvm-svn: 231172
* unique_ptrify LiveRange::segmentSetDavid Blaikie2015-03-032-3/+4
| | | | | | | | | | | | | This makes LiveRange non-copyable, and LiveInterval is already non-movable (due to the explicit dtor), so now it's non-copyable and non-movable. Fix the one case where we were relying on the (deprecated in C++11) implicit copy ctor of LiveInterval (which happened to work because the ctor created an object with a null segmentSet, so double-deleting the null pointer was fine). llvm-svn: 231168
* [sanitizer/coverage] Add AFL-style coverage counters (search heuristic for ↵Kostya Serebryany2015-03-038-8/+98
| | | | | | | | | | | | | | | | | | | | | | | | | fuzzing). Introduce -mllvm -sanitizer-coverage-8bit-counters=1 which adds imprecise thread-unfriendly 8-bit coverage counters. The run-time library maps these 8-bit counters to 8-bit bitsets in the same way AFL (http://lcamtuf.coredump.cx/afl/technical_details.txt) does: counter values are divided into 8 ranges and based on the counter value one of the bits in the bitset is set. The AFL ranges are used here: 1, 2, 3, 4-7, 8-15, 16-31, 32-127, 128+. These counters provide a search heuristic for single-threaded coverage-guided fuzzers, we do not expect them to be useful for other purposes. Depending on the value of -fsanitize-coverage=[123] flag, these counters will be added to the function entry blocks (=1), every basic block (=2), or every edge (=3). Use these counters as an optional search heuristic in the Fuzzer library. Add a test where this heuristic is critical. llvm-svn: 231166
* Remove subtarget dependence in pass pipeline setup for AArch64.Eric Christopher2015-03-032-4/+6
| | | | llvm-svn: 231165
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