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* Reland "Fix miscompile of MS inline assembly with stack realignment"Reid Kleckner2013-12-105-18/+36
| | | | | | | | | | | This re-lands commit r196876, which was reverted in r196879. The tests have been fixed to pass on platforms with a stack alignment larger than 4. Update to clang side tests will land shortly. llvm-svn: 196939
* Make Triple's isOSBinFormatXXX functions partition triple-space.Tim Northover2013-12-107-22/+18
| | | | | | | | | | | Most users would be surprised if "isCOFF" and "isMachO" were simultaneously true, unless they'd put the compiler in a box with a gun attached to a photon detector. This makes sure precisely one of the three formats is true for any triple and simplifies some target logic based on that. llvm-svn: 196934
* [AArch64] Refactor the Neon vector/scalar floating-point convert intrinsics soChad Rosier2013-12-101-13/+30
| | | | | | that they use float/double rather than the vector equivalents when appropriate. llvm-svn: 196930
* [AArch64] Refactor the Neon vector/scalar floating-point convert implementation.Chad Rosier2013-12-101-16/+16
| | | | | | Specifically, reuse the ARM intrinsics when possible. llvm-svn: 196926
* Ensure that the backend no longer emits unnecessary vector insert instructionsAndrea Di Biagio2013-12-101-0/+125
| | | | | | | | | | | | | | | | | | | | | | immediately after SSE scalar fp instructions like addss or mulss. Added patterns to select SSE scalar fp arithmetic instructions from a scalar fp operation followed by a blend. For example, given the following code: __m128 foo(__m128 A, __m128 B) { A[0] += B[0]; return A; } previously we generated: addss %xmm0, %xmm1 movss %xmm1, %xmm0 now we generate: addss %xmm1, %xmm0 llvm-svn: 196925
* R600: Fix an infinite loop when trying to reorganize export/tex vector inputVincent Lejeune2013-12-101-5/+8
| | | | llvm-svn: 196923
* R600: Fix input modifiers lost for CaymanVincent Lejeune2013-12-101-0/+18
| | | | llvm-svn: 196922
* Next step in Mips16 prologue/epilogue cleanup.Reed Kotler2013-12-104-18/+56
| | | | | | | | Save S2(reg 18) only when we are calling floating point stubs that have a return value of float or complex. Some more work to make this better but this is the first step. llvm-svn: 196921
* AVX-512: changed intrinsics for mask operationsElena Demikhovsky2013-12-102-16/+28
| | | | llvm-svn: 196918
* AVX-512: Changed intrinsics of VPCONFLICT to match GCC builtin formElena Demikhovsky2013-12-102-19/+39
| | | | llvm-svn: 196914
* Darwin: update default iOS version to 5.0Tim Northover2013-12-101-3/+3
| | | | | | | | | | | | Defaulting to iOS 3.0 when LLVM has to guess the version is no longer a useful option and can give surprising results (like tail calls being disabled). 5.0 seems like a reasonable compromise as a platform that's still interesting to some people. rdar://problem/15567348 llvm-svn: 196912
* [mips][msa] Correct sld and sldi builtins.Daniel Sanders2013-12-101-13/+21
| | | | | | | | | | | | | Summary: The result register of these instructions is also the first operand. Reviewers: jacksprat, dsanders Reviewed By: dsanders Differential Revision: http://llvm-reviews.chandlerc.com/D2362 Differential Revision: http://llvm-reviews.chandlerc.com/D2363 llvm-svn: 196910
* Add TargetLowering::prepareVolatileOrAtomicLoadRichard Sandiford2013-12-103-27/+47
| | | | | | | | | | | | | | | | | One unusual feature of the z architecture is that the result of a previous load can be reused indefinitely for subsequent loads, even if a cache-coherent store to that location is performed by another CPU. A special serializing instruction must be used if you want to force a load to be reattempted. Since volatile loads are not supposed to be omitted in this way, we should insert a serializing instruction before each such load. The same goes for atomic loads. The patch implements this at the IR->DAG boundary, in a similar way to atomic fences. It is a no-op for targets other than SystemZ. llvm-svn: 196906
* Add TargetLowering::prepareVolatileOrAtomicLoadRichard Sandiford2013-12-109-4/+45
| | | | | | | | | | | | | | | | | One unusual feature of the z architecture is that the result of a previous load can be reused indefinitely for subsequent loads, even if a cache-coherent store to that location is performed by another CPU. A special serializing instruction must be used if you want to force a load to be reattempted. Since volatile loads are not supposed to be omitted in this way, we should insert a serializing instruction before each such load. The same goes for atomic loads. The patch implements this at the IR->DAG boundary, in a similar way to atomic fences. It is a no-op for targets other than SystemZ. llvm-svn: 196905
* [AArch64 NEON] Replace fpimm with fpz32 for floating compare with zero.Kevin Qin2013-12-101-3/+3
| | | | | | This is a small change to be strict. Just want get pattern safer. llvm-svn: 196889
* [AArch64 NEON] Support poly128_t and implement relevant intrinsic.Kevin Qin2013-12-101-11/+18
| | | | llvm-svn: 196887
* GCOV.cpp: Use PRIu64 instead of %lu.NAKAMURA Takumi2013-12-101-1/+1
| | | | llvm-svn: 196882
* Add proper dependencies to LLVMBuild.txt in llvm/lib.NAKAMURA Takumi2013-12-1015-15/+15
| | | | | | I'll prune redundant deps in LLVMBuild.txt, later. llvm-svn: 196881
* Whitespaces.NAKAMURA Takumi2013-12-107-7/+2
| | | | llvm-svn: 196880
* Revert "Fix miscompile of MS inline assembly with stack realignment"Reid Kleckner2013-12-105-36/+18
| | | | | | | This reverts commit r196876. Its tests failed on the bots, so I'll figure it out tomorrow. llvm-svn: 196879
* Fix miscompile of MS inline assembly with stack realignmentReid Kleckner2013-12-105-18/+36
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | For stack frames requiring realignment, three pointers may be needed: - ebp to address incoming arguments - esi (could be any callee-saved register) to address locals - esp to address outgoing arguments We would use esi unconditionally without verifying that it did not conflict with inline assembly. This change doesn't do the verification, it simply emits a fatal error on functions that use stack realignment, dynamic SP adjustments, and inline assembly. Because stack realignment is common on Windows, we also no longer assume that MS inline assembly clobbers esp. Instead, we analyze the inline instructions for implicit definitions and check if esp is there. If so, we require the use of a base pointer and consider it in the condition above. Mostly fixes PR16830, but we could try harder to find a non-conflicting base pointer. Reviewers: sunfish Differential Revision: http://llvm-reviews.chandlerc.com/D1317 llvm-svn: 196876
* Fix a crash that occurs when PWD is invalid.Andrew Trick2013-12-102-5/+8
| | | | | | | | | | | | | | | | | | | | MCJIT needs to be able to run in hostile environments, even when PWD is invalid. There's no need to crash MCJIT in this case. The obvious fix is to simply leave MCContext's CompilationDir empty when PWD can't be determined. This way, MCJIT clients, and other clients that link with LLVM don’t need a valid working directory. If we do want to guarantee valid CompilationDir, that should be done only for clients of getCompilationDir(). This is as simple as checking for an empty string. The only current use of getCompilationDir is EmitGenDwarfInfo, which won’t conceivably run with an invalid working dir. However, in the purely hypothetically and untestable case that this happens, the AT_comp_dir will be omitted from the compilation_unit DIE. llvm-svn: 196874
* whitespaceAndrew Trick2013-12-101-2/+2
| | | | llvm-svn: 196873
* Fix PR18162 - Incorrect assertion assumed that the SDValue resno is zero.Nadav Rotem2013-12-101-1/+1
| | | | llvm-svn: 196858
* llvm-cov: Added -a option for block data.Yuchen Wu2013-12-101-3/+30
| | | | | | | | | | | | | | | Similar to gcov, llvm-cov will now print out the block count at the end of each block. Multiple blocks can end on the same line. One computational difference is by using -a, llvm-cov will no longer simply add the block counts together to form a line count. Instead, it will take the maximum of the block counts on that line. This has a similar effect to what gcov does, but generates more correct counts in certain scenarios. Also updated tests. llvm-svn: 196856
* Disable emitting DW_AT_GNU_ranges_base until we actually use it.Eric Christopher2013-12-101-6/+1
| | | | llvm-svn: 196851
* Add comments documenting the ARM datalayout string.Rafael Espindola2013-12-101-0/+12
| | | | llvm-svn: 196850
* We never emit info into the macro info section, stop emitting anEric Christopher2013-12-102-15/+0
| | | | | | empty one. llvm-svn: 196849
* 80-col.Eric Christopher2013-12-101-1/+2
| | | | llvm-svn: 196848
* Simplify further.Rafael Espindola2013-12-101-12/+4
| | | | | | Thanks to Jim Grosbach for noticing it. llvm-svn: 196846
* Transforms: Don't create bad branch weights when folding a switchJustin Bogner2013-12-101-2/+4
| | | | | | | | This avoids creating branch weight metadata of length one when we fold cases into the default of a switch instruction, which was triggering an assert. llvm-svn: 196845
* Rename CompileUnit->DwarfCompileUnit and TypeUnit->DwarfTypeUnit forEric Christopher2013-12-094-93/+104
| | | | | | clarity. No functional change. llvm-svn: 196844
* Refactor the construction of the DataLayout string on ARM.Rafael Espindola2013-12-091-19/+39
| | | | llvm-svn: 196843
* Rename Unit->DwarfUnit to match the file name and make it a bit lessEric Christopher2013-12-094-203/+211
| | | | | | ambiguous. Reformat to match. llvm-svn: 196838
* [AArch64] Refactor the NEON scalar reduce pairwise intrinsics, so that they useChad Rosier2013-12-091-3/+3
| | | | | | float/double rather than the vector equivalents when appropriate. llvm-svn: 196833
* [AArch64] Refactor NEON scalar reduce pairwise front-end codegen to removeChad Rosier2013-12-091-16/+1
| | | | | | unnecessary patterns in tablegen. llvm-svn: 196832
* [AArch64] Remove q and non-q intrinsic definitions in the NEON scalar reduceChad Rosier2013-12-091-14/+13
| | | | | | pairwise implementation, using an overloaded definition instead. llvm-svn: 196831
* get rid of superfluous commentReed Kotler2013-12-091-1/+0
| | | | llvm-svn: 196829
* Delete some old code used for testing that is not needed anymore.Reed Kotler2013-12-091-87/+33
| | | | | | This is part of the mips16 epilogue/prologue cleanup. llvm-svn: 196824
* Don't add suffixes for stdcall/fastcall on 64 coff.Rafael Espindola2013-12-091-0/+2
| | | | | | This matches the behavior of both msvc and mingw. llvm-svn: 196814
* Use a more direct check for finding out the file type.Rafael Espindola2013-12-092-15/+21
| | | | | | No functionality change. llvm-svn: 196811
* Don't set a variable to its default value.Rafael Espindola2013-12-091-1/+0
| | | | llvm-svn: 196807
* Fix pattern match for movi with 0D resultAna Pazos2013-12-091-3/+2
| | | | | | | | | | | Patch by Jiangning Liu. With some test case changes: - intrinsic test added to the existing /test/CodeGen/AArch64/neon-aba-abd.ll. - New test cases to cover movi 1D scenario without using the intrinsic in test/CodeGen/AArch64/neon-mov.ll. llvm-svn: 196806
* DwarfDebug/Unit: Remove another case of label recreation by storing the ↵David Blaikie2013-12-092-6/+14
| | | | | | gnu_ranges label in the unit. llvm-svn: 196793
* Improve the detection of the pathSylvestre Ledru2013-12-091-11/+12
| | | | | | | | | | | | | | | | | | | | | | | | | Summary: When clang is used under GNU/Linux in a chroot without /proc mount, it falls back on the BSD method. However, since the buf variable is used twice and fails with snprintf to produce the correct path. When called as relatived (ie ./clang), it was failing with: "" -cc1 [...] -x c++ x.cc error: unable to execute command: Executable "" doesn't exist! I also took the opportunity to simply the code (the first arg of test_dir was useless). Reviewers: rafael Reviewed By: rafael CC: cfe-commits Differential Revision: http://llvm-reviews.chandlerc.com/D2361 llvm-svn: 196791
* [mips][msa] Fix invalid generated code when lowering FrameIndex involving ↵Daniel Sanders2013-12-091-2/+21
| | | | | | | | | | | | | | | | | | | | | | | | unaligned offsets. Summary: The MSA ld.[bhwd] and st.[bhwd] instructions scale the immediate by the element size before use as an offset. The offset must therefore be a multiple of the element size to be valid in these instructions. However, an unaligned base address is valid in MSA. This commit causes the compiler to emit valid code when the calculated offset is not a multiple of the element size by accounting for the offset using addiu and using a zero offset in the load/store. Depends on D2338 Reviewers: matheusalmeida Reviewed By: matheusalmeida Differential Revision: http://llvm-reviews.chandlerc.com/D2339 llvm-svn: 196777
* [mips][msa] Fix suboptimal FrameIndex lowering for ld.[hwd] and st.[hwd]Daniel Sanders2013-12-091-15/+20
| | | | | | | | | | | | | | Summary: The immediate in these instructions is scaled before use as an offset. They therefore have a wider reach than ld.b/st.b. Reviewers: matheusalmeida Reviewed By: matheusalmeida Differential Revision: http://llvm-reviews.chandlerc.com/D2338 llvm-svn: 196775
* Method parseSetAssignment treats every operand with '$' sign as register and ↵Vladimir Medic2013-12-091-16/+1
| | | | | | | | | the parsing is directed to set alias for register. This will result in errors reported when expressions containing label references are parsed(for example long jumps) As we can't make a complete solution now it has been decided to enable .set directive to handle long jump expressions. This will cause parser to report errors when parsing integer based register assignments, for example: .set r3, will be reported as error. Still, the need for expressions is higher priority as the integer based register assignments are Mips specific and can be avoided using register names. llvm-svn: 196773
* [SPARCV9]: Adjust the resultant pointer of DYNAMIC_STACKALLOC with the stack ↵Venkatraman Govindaraju2013-12-091-3/+5
| | | | | | BIAS on sparcV9. llvm-svn: 196755
* [Sparc]: Implement getSetCCResultType() in SparcTargetLowering so that ↵Venkatraman Govindaraju2013-12-092-0/+9
| | | | | | umulo/smulo can be lowered on sparcv9 without an assertion error. llvm-svn: 196751
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