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* [PATCH][Interpreter] Add missing FP intrinsic lowering.Josh Klontz2014-08-301-0/+16
| | | | | | | | | | | | | | | | | Summary: This extends the work done in [1], adding missing intrinsic lowering for floor, trunc, round and copysign. [1] http://comments.gmane.org/gmane.comp.compilers.llvm.cvs/199372 Test Plan: Extended `test/ExecutionEngine/Interpreter/intrinsics.ll` to test the additional missing intrinsics. All tests pass. Reviewers: dexonsmith Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D5120 llvm-svn: 216827
* Remove 'virtual' keyword from methods markedwith 'override' keyword.Craig Topper2014-08-3014-67/+64
| | | | llvm-svn: 216823
* Fix some cases where StringRef was being passed by const reference. Remove ↵Craig Topper2014-08-3015-44/+43
| | | | | | const from some other StringRefs since its implicitly const already. llvm-svn: 216820
* JIT support has been added awhile ago.Brad Smith2014-08-301-2/+0
| | | | llvm-svn: 216819
* Fix AddAliasScopeMetadata to not add scopes when deriving from unknown pointersHal Finkel2014-08-301-25/+51
| | | | | | | | | | | | | | | | | | | | | | | The previous implementation of AddAliasScopeMetadata, which adds noalias metadata to preserve noalias parameter attribute information when inlining had a flaw: it would add alias.scope metadata to accesses which might have been derived from pointers other than noalias function parameters. This was incorrect because even some access known not to alias with all noalias function parameters could easily alias with an access derived from some other pointer. Instead, when deriving from some unknown pointer, we cannot add alias.scope metadata at all. This fixes a miscompile of the test-suite's tramp3d-v4. Furthermore, we cannot add alias.scope to functions unless we know they access only argument-derived pointers (currently, we know this only for memory intrinsics). Also, we fix a theoretical problem with using the NoCapture attribute to skip the capture check. This is incorrect (as explained in the comment added), but would not matter in any code generated by Clang because we get only inferred nocapture attributes in Clang-generated IR. This functionality is not yet enabled by default. llvm-svn: 216818
* InstCombine: Respect recursion depth in visitUDivOperandDavid Majnemer2014-08-301-4/+4
| | | | llvm-svn: 216817
* InstCombine: Try harder to combine icmp instructionsDavid Majnemer2014-08-301-3/+25
| | | | | | | | | | | | | consider: (and (icmp X, Y), (and Z, (icmp A, B))) It may be possible to combine (icmp X, Y) with (icmp A, B). If we successfully combine, create an 'and' instruction with Z. This fixes PR20814. N.B. There is room for improvement after this change but I'm not convinced it's worth chasing yet. llvm-svn: 216814
* Revert r216805 "[MachineCombiner][AArch64] Use the correct register class ↵Juergen Ributzka2014-08-301-119/+73
| | | | | | | | for MADD, SUB, and OR." I think this broke the build bot. Reverting it for now until I have time to take a closer look. llvm-svn: 216813
* Fix typo and formattingNick Kledzik2014-08-301-3/+3
| | | | llvm-svn: 216809
* Object/llvm-objdump: allow dumping of mach-o exports trieNick Kledzik2014-08-301-2/+241
| | | | | | | | | | | | | | | | | | MachOObjectFile in lib/Object currently has no support for parsing the rebase, binding, and export information from the LC_DYLD_INFO load command in final linked mach-o images. This patch adds support for parsing the exports trie data structure. It also adds an option to llvm-objdump to dump that export info. I did the exports parsing first because it is the hardest. The information is encoded in a trie structure, but the standard ObjectFile way to inspect content is through iterators. So I needed to make an iterator that would do a non-recursive walk through the trie and maintain the concatenation of edges needed for the current string prefix. I plan to add similar support in MachOObjectFile and llvm-objdump to parse/display the rebasing and binding info too. llvm-svn: 216808
* [MachineCombiner][AArch64] Use the correct register class for MADD, SUB, and OR.Juergen Ributzka2014-08-291-73/+119
| | | | | | | | | | Select the correct register class for the various instructions that are generated when combining instructions and constrain the registers to the appropriate register class. This fixes rdar://problem/18183707. llvm-svn: 216805
* [FastISel][AArch64] Use the correct register class for branches.Juergen Ributzka2014-08-291-7/+9
| | | | | | | | Also constrain the register class for branches. This fixes rdar://problem/18181496. llvm-svn: 216804
* [MachineSinking] Clear kill flag of all operands at all their uses.Juergen Ributzka2014-08-291-3/+13
| | | | | | | | | | | | | | | | | | | | | | | When sinking an instruction it might be moved past the original last use of one of its operands. This last use has the kill flag set and the verifier will obviously complain about this. Before Machine Sinking (AArch64): %vreg3<def> = ASRVXr %vreg1, %vreg2<kill> %XZR<def> = SUBSXrs %vreg4, %vreg1<kill>, 160, %NZCV<imp-def> ... After Machine Sinking: %XZR<def> = SUBSXrs %vreg4, %vreg1<kill>, 160, %NZCV<imp-def> ... %vreg3<def> = ASRVXr %vreg1, %vreg2<kill> This fix clears all the kill flags in all instruction that use the same operands as the instruction that is being sunk. This fixes rdar://problem/18180996. llvm-svn: 216803
* [MCJIT] Move endian-aware read/writes from RuntimeDyldMachO intoLang Hames2014-08-298-57/+46
| | | | | | | | | RuntimeDyldImpl. These are platform independent, and moving them to the base class allows RuntimeDyldChecker to use them too. llvm-svn: 216801
* Debug info: Add a new explicit DIDescriptor flag for the "public" accessAdrian Prantl2014-08-292-3/+8
| | | | | | | | | | specifier and change the default behavior to only emit the DW_AT_accessibility(public) attribute when the isPublic() is explicitly set. rdar://problem/18154959 llvm-svn: 216799
* Comment only: Annotate loop as per mailing list discussionJean-Luc Duprat2014-08-291-0/+3
| | | | llvm-svn: 216798
* Make isValidMCLOHType take unsigned instead of enum to avoid loading invalid ↵Alexey Samsonov2014-08-291-3/+2
| | | | | | enum values llvm-svn: 216797
* AArch64: Silence -Wabsolute-value warning with std::absReid Kleckner2014-08-291-1/+2
| | | | llvm-svn: 216794
* Speculative build fix for const, gcc, and ArrayRef overloadsReid Kleckner2014-08-291-3/+3
| | | | llvm-svn: 216793
* Revert accidentally committed patches r216787-r216789David Blaikie2014-08-292-29/+9
| | | | | | | | | | Rushed when I realized I hadn't committed the FreeDeleter for a clang change I'd committed, and didn't check that I had things lying around in my client. Apologies for the noise. llvm-svn: 216792
* Omit DW_AT_artificial, DW_AT_external, and similar attributes under -gmltDavid Blaikie2014-08-291-0/+3
| | | | llvm-svn: 216789
* Omit dwarf::DW_AT_frame_base under -gmltDavid Blaikie2014-08-291-3/+6
| | | | llvm-svn: 216788
* StuffDavid Blaikie2014-08-291-6/+20
| | | | llvm-svn: 216787
* Fix typos in comments, NFCRobin Morisset2014-08-2912-15/+13
| | | | | | | | | | | | | | Summary: Just fixing comments, no functional change. Test Plan: N/A Reviewers: jfb Subscribers: mcrosier, llvm-commits Differential Revision: http://reviews.llvm.org/D5130 llvm-svn: 216784
* Add a const and munge some commentsReid Kleckner2014-08-292-4/+6
| | | | llvm-svn: 216781
* musttail: Forward regparms of variadic functions on x86_64Reid Kleckner2014-08-293-71/+161
| | | | | | | | | | | | | | | | | | | | | | Summary: If a variadic function body contains a musttail call, then we copy all of the remaining register parameters into virtual registers in the function prologue. We track the virtual registers through the function body, and add them as additional registers to pass to the call. Because this is all done in virtual registers, the register allocator usually gives us good code. If the function does a call, however, it will have to spill and reload all argument registers (ew). Forwarding regparms on x86_32 is not implemented because most compilers don't support varargs in 32-bit with regparms. Reviewers: majnemer Subscribers: aemerson, llvm-commits Differential Revision: http://reviews.llvm.org/D5060 llvm-svn: 216780
* Verifier: Don't reject varargs callee cleanup functionsReid Kleckner2014-08-292-12/+6
| | | | | | | | | | | | | | | | | | We've rejected these kinds of functions since r28405 in 2006 because it's impossible to lower the return of a callee cleanup varargs function. However there are lots of legal ways to leave such a function without returning, such as aborting. Today we can leave a function with a musttail call to another function with the correct prototype, and everything works out. I'm removing the verifier check declaring that a normal return from such a function is UB. Reviewed By: nlewycky Differential Revision: http://reviews.llvm.org/D5059 llvm-svn: 216779
* Remove spurious mask operations from AArch64 add->compares on 16 and 8 bit ↵Louis Gerbarg2014-08-291-0/+263
| | | | | | | | | | | | | | | | | | | | | | | | | | values This patch checks for DAG patterns that are an add or a sub followed by a compare on 16 and 8 bit inputs. Since AArch64 does not support those types natively they are legalized into 32 bit values, which means that mask operations are inserted into the DAG to emulate overflow behaviour. In many cases those masks do not change the result of the processing and just introduce a dependent operation, often in the middle of a hot loop. This patch detects the relevent DAG patterns and then tests to see if the transforms are equivalent with and without the mask, removing the mask if possible. The exact mechanism of this patch was discusses in http://lists.cs.uiuc.edu/pipermail/llvmdev/2014-July/074444.html There is a reasonably good chance there are missed oppurtunities due to similiar (but not identical) DAG patterns that could be funneled into this test, adding them should be simple if we see test cases. Tests included. rdar://13754426 llvm-svn: 216776
* X86: Fix conflict over ESI between base register and rep;movslReid Kleckner2014-08-292-6/+36
| | | | | | | | | | | | | | The new solution is to not use this lowering if there are any dynamic allocas in the current function. We know up front if there are dynamic allocas, but we don't know if we'll need to create stack temporaries with large alignment during lowering. Conservatively assume that we will need such temporaries. Reviewed By: hans Differential Revision: http://reviews.llvm.org/D5128 llvm-svn: 216775
* Relax the constraint more in MemoryDependencyAnalysis.cppRobin Morisset2014-08-291-6/+40
| | | | | | | | Even loads/stores that have a stronger ordering than monotonic can be safe. The rule is no release-acquire pair on the path from the QueryInst, assuming that the QueryInst is not atomic itself. llvm-svn: 216771
* [X86] Refactor X86ISelDAGToDAG::SelectAtomicLoadArith - NFCRobin Morisset2014-08-291-10/+17
| | | | | | | | | | | | | | | | | | | Summary: Mostly renaming the (not very explicit) variables Tmp0, .. Tmp4, and grouping related statements together, along with a few lines of comments for the surprising parts. No functional change intended. Test Plan: make check-all Reviewers: jfb Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D5088 llvm-svn: 216768
* Tablegen fixes for new syntax when initializing bits from variables.Jean-Luc Duprat2014-08-291-0/+9
| | | | | | Followup to r215086. llvm-svn: 216757
* [FastISel][AArch64] Fix an incorrect kill flag due to a bug in SelectTrunc.Juergen Ributzka2014-08-291-6/+13
| | | | | | | | | | | | | | | | | | | | When we select a trunc instruction we don't emit any code if the type is already i32 or smaller. This is because the instruction that uses the truncated value will deal with it. This behavior can incorrectly transfer a kill flag, which was meant for the result of the truncate, onto the source register. %2 = trunc i32 %1 to i16 ... = ... %2 -> ... = ... vreg1 <kill> ... = ... %1 ... = ... vreg1 This commit fixes this by emitting a COPY instruction, so that the result and source register are distinct virtual registers. This fixes rdar://problem/18178188. llvm-svn: 216750
* Fix a typo in AddAliasScopeMetadataHal Finkel2014-08-291-1/+1
| | | | llvm-svn: 216741
* Make fabs safe to speculatively executeMatt Arsenault2014-08-291-0/+1
| | | | llvm-svn: 216736
* R600/SI: Use mad for fsub + fmulMatt Arsenault2014-08-296-0/+54
| | | | | | | We can use a negate source modifier to match this for fsub. llvm-svn: 216735
* AArch64: only try to get operand of a known node.Tim Northover2014-08-291-5/+5
| | | | | | | A bug in r216725 meant we tried to discover the type of a SETCC before confirming the node actually was a SETCC. llvm-svn: 216734
* typoSanjay Patel2014-08-291-1/+1
| | | | llvm-svn: 216732
* [NVPTX] Make the alignment an explicit argument to ldu/ldgJingyue Wu2014-08-291-20/+2
| | | | | | | | | | | | | | | | | | | | | | Summary: Instead of specifying the alignment as metadata which may be destroyed by transformation passes, make the alignment the second argument to ldu/ldg intrinsic calls. Test Plan: ldu-ldg.ll ldu-i8.ll ldu-reg-plus-offset.ll Reviewers: eliben, meheff, jholewinski Reviewed By: meheff, jholewinski Subscribers: jholewinski, llvm-commits Differential Revision: http://reviews.llvm.org/D5093 llvm-svn: 216731
* AArch64: skip select/setcc combine in complex case.Tim Northover2014-08-291-8/+10
| | | | | | | | | | | In an llvm-stress generated test, we were trying to create a v0iN type and asserting when that failed. This case could probably be handled by the function, but not without added complexity and the situation it arises in is sufficiently odd that there's probably no benefit anyway. Should fix PR20775. llvm-svn: 216725
* [AArch64] FPLoadBalancing: move ownership of the chain to its current ↵Arnaud A. de Grandmaison2014-08-291-5/+14
| | | | | | | | | | | | | | | | | accumulator register and forget about the previously used accumulator. Coming up with a simple testcase is not easy, as this highly depends on what the register allocator is doing: this issue showed up while working with the PBQP allocator, which produced a different allocation scheme. A testcase would need to come up with chain starting in D[0-7], then moving to D[8-15], followed by a call to a function whose regmask clobbers the starting accumulator in D[0-7], then another use of the chain. Fixed some formatting, added some invariant checks while there. llvm-svn: 216721
* Use DwarfDebug::attachLowHighPC for the compilation unit DIE.Frederic Riss2014-08-291-4/+1
| | | | llvm-svn: 216719
* [SKX] Enable lowering of integer CMP operations.Robert Khasanov2014-08-291-9/+75
| | | | | | | | | | Added new types to Legalizer. Fixed getSetCCResultType function Added lowering tests. Reviewed by Elena Demikhovsky. llvm-svn: 216717
* Do not assume the value passed to memset is an i32.Job Noorman2014-08-291-8/+1
| | | | | | | | | | | | | The code in SelectionDAG::getMemset for some reason assumes the value passed to memset is an i32. This breaks the generated code for targets that only have registers smaller than 32 bits because the value might get split into multiple registers by the calling convention. See the test for the MSP430 target included in the patch for an example. This patch ensures that nothing is assumed about the type of the value. Instead, the type is taken from the selected overload of the llvm.memset intrinsic. llvm-svn: 216716
* [AArch64] Fix some failures exposed by value type v4f16 and v8f16.Jiangning Liu2014-08-292-2/+11
| | | | | | | 1) Add some missing bitcast patterns for v8f16. 2) Add type promotion for operand of ld/st operations. llvm-svn: 216706
* Cleaning up static initializers in Signals.incChris Bieneman2014-08-291-5/+4
| | | | | | Reviewed by: Chandlerc llvm-svn: 216704
* Cleaning up static initializers in TimeValue.Chris Bieneman2014-08-292-7/+1
| | | | | | Code reviewed by Chandlerc llvm-svn: 216703
* [FastISel][AArch64] Don't fold instructions that are not in the same basic ↵Juergen Ributzka2014-08-291-23/+38
| | | | | | | | | | | | | | | block. This fix checks first if the instruction to be folded (e.g. sign-/zero-extend, or shift) is in the same machine basic block as the instruction we are folding into. Not doing so can result in incorrect code, because the value might not be live-out of the basic block, where the value is defined. This fixes rdar://problem/18169495. llvm-svn: 216700
* Revert two GEP-related InstCombine commitsDavid Majnemer2014-08-291-40/+11
| | | | | | | This reverts commit r216523 and r216598; people have reported regressions. llvm-svn: 216698
* Don't promote byval pointer arguments when padding mattersReid Kleckner2014-08-281-3/+81
| | | | | | | | | | | | | | | | Don't promote byval pointer arguments when when their size in bits is not equal to their alloc size in bits. This can happen for x86_fp80, where the size in bits is 80 but the alloca size in bits in 128. Promoting these types can break passing unions of x86_fp80s and other types. Patch by Thomas Jablin! Reviewed By: rnk Differential Revision: http://reviews.llvm.org/D5057 llvm-svn: 216693
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