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* [CodeGen] isInTailCallPosition didn't consider readnone tailcallsDavid Majnemer2015-08-282-13/+12
| | | | | | | | | | A readnone tailcall may still have a chain of computation which follows it that would invalidate a tailcall lowering. Don't skip the analysis in such cases. This fixes PR24613. llvm-svn: 246304
* [x86] enable machine combiner reassociations for scalar 'and' instsSanjay Patel2015-08-281-1/+5
| | | | llvm-svn: 246300
* [SROA] Fix PR24463, a crash I introduced in SROA by allowing it toChandler Carruth2015-08-281-3/+13
| | | | | | | | | | | | handle more allocas with loads past the end of the alloca. I suspect there are some related crashers with slightly different patterns, but I'll fix those and add test cases as I find them. Thanks to David Majnemer for the excellent test case reduction here. Made this super simple to debug and fix. llvm-svn: 246289
* Re-apply r246276 - Object: Teach llvm-ar to create symbol table for COFF ↵Rui Ueyama2015-08-281-1/+4
| | | | | | | | | | | short import files This patch includes a fix for a llvm-readobj test. With this patch, the tool does no longer print out COFF headers for the short import file, but that's probably desirable because the header for the short import file is dummy. llvm-svn: 246283
* Revert r246244 and r246243Steven Wu2015-08-283-117/+13
| | | | | | These two commits cause clang/llvm bootstrap to hang. llvm-svn: 246279
* Rollback r246276 - Object: Teach llvm-ar to create symbol table for COFF ↵Rui Ueyama2015-08-281-46/+1
| | | | | | | | short import files This change caused a test for llvm-readobj to fail. llvm-svn: 246277
* Object: Teach llvm-ar to create symbol table for COFF short import files.Rui Ueyama2015-08-281-1/+46
| | | | | | | | | | | | | COFF short import files are special kind of files that contains only DLL-exported symbol names. That's different from object files because it has no data except symbol names. This change implements a SymbolicFile interface for the short import files so that symbol names can be accessed through that interface. llvm-ar is now able to read the file and create symbol table entries for short import files. llvm-svn: 246276
* LLVMCodeGen: Update libdeps corresponding to r246236.NAKAMURA Takumi2015-08-281-1/+1
| | | | llvm-svn: 246274
* [CodeGen] Support (and default to) expanding READCYCLECOUNTER to 0.Ahmed Bougacha2015-08-285-30/+49
| | | | | | | | | | | For targets that didn't support this, this will let us respect the langref instead of failing to select. Note that we don't need to change the 32-bit x86/PPC lowerings (to account for the result type/# difference) because they're both custom and bypass type legalization. llvm-svn: 246258
* [WinEH] Update coloring to handle nested cases cleanlyJoseph Tremoulet2015-08-281-70/+114
| | | | | | | | | | | | | | | | | | | | | | | Summary: Change the coloring algorithm in WinEHPrepare to visit a funclet's exits in its parents' contexts and so properly classify the continuations of nested funclets. Also change the placement of cloned blocks to be deterministic and to maintain the relative order of each funclet's blocks. Add a lit test showing various patterns that require cloning, the last several of which don't have CHECKs yet because they require cloning entire funclets which is NYI. Reviewers: rnk, andrew.w.kaylor, majnemer Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D12353 llvm-svn: 246245
* Constant propagation after hitting assume(cmp) bugfixPiotr Padlewski2015-08-283-11/+50
| | | | | | | | | Last time code run into assertion `BBE.isSingleEdge()` in lib/IR/Dominators.cpp:200. http://reviews.llvm.org/D12170 llvm-svn: 246244
* Constant propagation after hiting llvm.assumePiotr Padlewski2015-08-281-3/+68
| | | | | | | | | | | After hitting @llvm.assume(X) we can: - propagate equality that X == true - if X is icmp/fcmp (with eq operation), and one of operand is constant we can change all variables with constants in the same BasicBlock http://reviews.llvm.org/D11918 llvm-svn: 246243
* Fix: CFLAA -- Mark no-args returns as unknownGeorge Burgess IV2015-08-281-0/+10
| | | | | | | | | | | | | | Prior to this patch, we hadn't been marking StratifiedSets with the appropriate StratifiedAttrs when handling the result of no-args call instructions. This caused us to report NoAlias when handed, for example, an escaped alloca and a result from an opaque function. Now we properly mark the return value of said functions. Thanks again to Chandler, Richard, and Nick for pinging me about this. Differential review: http://reviews.llvm.org/D12408 llvm-svn: 246240
* [AArch64][CollectLOH] Fix a regression that prevented us to detect chains ofQuentin Colombet2015-08-271-2/+6
| | | | | | | | | | | more than 2 instructions. I introduced this regression a while back and did not noticed it because I somehow forgot to push the initial test cases for the pass! Fix that as well! llvm-svn: 246239
* CodeGen: Introduce splitCodeGen and teach LTOCodeGenerator to use it.Peter Collingbourne2015-08-273-13/+111
| | | | | | | | | | | | | | | llvm::splitCodeGen is a function that implements the core of parallel LTO code generation. It uses llvm::SplitModule to split the module into linkable partitions and spawning one code generation thread per partition. The function produces multiple object files which can be linked in the usual way. This has been threaded through to LTOCodeGenerator (and llvm-lto for testing purposes). Separate patches will add parallel LTO support to the gold plugin and lld. Differential Revision: http://reviews.llvm.org/D12260 llvm-svn: 246236
* [WinEH] Add some support for code generating catchpadReid Kleckner2015-08-2730-84/+193
| | | | | | | We can now run 32-bit programs with empty catch bodies. The next step is to change PEI so that we get funclet prologues and epilogues. llvm-svn: 246235
* [ValueTracking] readnone CallInsts are fair game for speculationDavid Majnemer2015-08-271-39/+3
| | | | | | | | | | Any call which is side effect free is trivially OK to speculate. We already had similar logic in EarlyCSE and GVN but we were missing it from isSafeToSpeculativelyExecute. This fixes PR24601. llvm-svn: 246232
* [CodeGen] Check FoldConstantArithmetic result before using it.Ahmed Bougacha2015-08-271-2/+3
| | | | | | | | Fixes PR24602: r245689 introduced an unguarded use of SelectionDAG::FoldConstantArithmetic, which returns 0 when it fails because of opaque (hoisted) constants. llvm-svn: 246217
* Enable constant propagation for more math functionsErik Schnetter2015-08-271-37/+55
| | | | | | | | | | | | Constant propagation for single precision math functions (such as tanf) is already working, but was not enabled. This patch enables these for many single-precision functions, and adds respective test cases. Newly handled functions: acosf asinf atanf atan2f ceilf coshf expf exp2f fabsf floorf fmodf logf log10f powf sinhf tanf tanhf llvm-svn: 246194
* Revert 246186; still breaks on some systemsErik Schnetter2015-08-271-55/+37
| | | | llvm-svn: 246191
* Improve vectorization diagnostic messages and extend vectorize(enable) pragma.Tyler Nowicki2015-08-271-15/+25
| | | | | | | | | | | | | | | | This patch changes the analysis diagnostics produced when loops with floating-point recurrences or memory operations are identified. The new messages say "cannot prove it is safe to reorder * operations; allow reordering by specifying #pragma clang loop vectorize(enable)". Depending on the type of diagnostic the message will include additional options such as ffast-math or __restrict__. This patch also allows the vectorize(enable) pragma to override the low pointer memory check threshold. When the hint is given a higher threshold is used. See the clang patch for the options produced for each diagnostic. llvm-svn: 246187
* Enable constant propagation for more math functionsErik Schnetter2015-08-271-37/+55
| | | | | | | | | | | | Constant propagation for single precision math functions (such as tanf) is already working, but was not enabled. This patch enables these for many single-precision functions, and adds respective test cases. Newly handled functions: acosf asinf atanf atan2f ceilf coshf expf exp2f fabsf floorf fmodf logf log10f powf sinhf tanf tanhf llvm-svn: 246186
* Revert r246158 since it breaks LLVM.Transforms/ConstProp.calls.llErik Schnetter2015-08-271-55/+37
| | | | llvm-svn: 246166
* Enable constant propagation for more math functionsErik Schnetter2015-08-271-37/+55
| | | | | | | | | | | | Constant propagation for single precision math functions (such as tanf) is already working, but was not enabled. This patch enables these for many single-precision functions, and adds respective test cases. Newly handled functions: acosf asinf atanf atan2f ceilf coshf expf exp2f fabsf floorf fmodf logf log10f powf sinhf tanf tanhf llvm-svn: 246158
* [LoopVectorize] Add Support for Small Size Reductions.Chad Rosier2015-08-272-32/+214
| | | | | | | | | | | | | | | | | | | | | | | Unlike scalar operations, we can perform vector operations on element types that are smaller than the native integer types. We type-promote scalar operations if they are smaller than a native type (e.g., i8 arithmetic is promoted to i32 arithmetic on Arm targets). This patch detects and removes type-promotions within the reduction detection framework, enabling the vectorization of small size reductions. In the legality phase, we look through the ANDs and extensions that InstCombine creates during promotion, keeping track of the smaller type. In the profitability phase, we use the smaller type and ignore the ANDs and extensions in the cost model. Finally, in the code generation phase, we truncate the result of the reduction to allow InstCombine to rewrite the entire expression in the smaller type. This fixes PR21369. http://reviews.llvm.org/D12202 Patch by Matt Simpson <mssimpso@codeaurora.org>! llvm-svn: 246149
* [LoopVectorize] Extract InductionInfo into a helper class...James Molloy2015-08-273-134/+87
| | | | | | | | ... and move it into LoopUtils where it can be used by other passes, just like ReductionDescriptor. The API is very similar to ReductionDescriptor - that is, not very nice at all. Sorting these both out will come in a followup. NFC llvm-svn: 246145
* Whoops, remove trailing whitespace.Alex Rosenberg2015-08-271-1/+1
| | | | llvm-svn: 246141
* isKnownNonNull needs to consider globals in non-zero address spaces.Pete Cooper2015-08-271-2/+5
| | | | | | | | | Globals in address spaces other than one may have 0 as a valid address, so we should not assume that they can be null. Reviewed by Philip Reames. llvm-svn: 246137
* Allow value forwarding past release fences in EarlyCSEPhilip Reames2015-08-271-0/+11
| | | | | | | | | | | | A release fence acts as a publication barrier for stores within the current thread to become visible to other threads which might observe the release fence. It does not require the current thread to observe stores performed on other threads. As a result, we can allow store-load and load-store forwarding across a release fence. We do need to make sure that stores before the fence can't be eliminated even if there's another store to the same location after the fence. In theory, we could reorder the second store above the fence and *then* eliminate the former, but we can't do this if the stores are on opposite sides of the fence. Note: While more aggressive then what's there, this patch is still implementing a really conservative ordering. In particular, I'm not trying to exploit undefined behavior via races, or the fact that the LangRef says only 'atomic' accesses are ordered w.r.t. fences. Differential Revision: http://reviews.llvm.org/D11434 llvm-svn: 246134
* [RewriteStatepointsForGC] Reduce the number of new instructions for base ↵Philip Reames2015-08-271-3/+57
| | | | | | | | | | | | | | pointers When computing base pointers, we introduce new instructions to propagate the base of existing instructions which might not be bases. However, the algorithm doesn't make any effort to recognize when the new instruction to be inserted is the same as an existing one already in the IR. Since this is happening immediately before rewriting, we don't really have a chance to fix it after the pass runs without teaching loop passes about statepoints. I'm really not thrilled with this patch. I've rewritten it 4 different ways now, but this is the best I've come up with. The case where the new instruction is just the original base defining value could be merged into the existing algorithm with some complexity. The problem is that we might have something like an extractelement from a phi of two vectors. It may be trivially obvious that the base of the 0th element is an existing instruction, but I can't see how to make the algorithm itself figure that out. Thus, I resort to the call to SimplifyInstruction instead. Note that we can only adjust the instructions we've inserted ourselves. The live sets are still being tracked in side structures at this point in the code. We can't easily muck with instructions which might be in them. Long term, I'm really thinking we need to materialize the live pointer sets explicitly in the IR somehow rather than using side structures to track them. Differential Revision: http://reviews.llvm.org/D12004 llvm-svn: 246133
* Improved printing of analysis diagnostics in the loop vectorizer.Tyler Nowicki2015-08-271-18/+26
| | | | | | | | This patch ensures that every analysis diagnostic produced by the vectorizer will be printed if the loop has a vectorization hint on it. The condition has also been improved to prevent printing when a disabling hint is specified. llvm-svn: 246132
* Fixed a bug that edge weights are not assigned correctly when lowering ↵Cong Hou2015-08-271-1/+1
| | | | | | | | | | switch statement. This is a one-line-change patch that moves the update to UnhandledWeights to the correct position: it should be updated for all clusters instead of just range clusters. Differential Revision: http://reviews.llvm.org/D12391 llvm-svn: 246129
* [SimplifyCFG] Prune code from a provably unreachable switch defaultPhilip Reames2015-08-261-0/+17
| | | | | | | | | | As Sanjoy pointed out over in http://reviews.llvm.org/D11819, a switch on an icmp should always be able to become a branch instruction. This patch generalizes that notion slightly to prove that the default case of a switch is unreachable if the cases completely cover all possible bit patterns in the condition. Once that's done, the switch to branch conversion kicks in just fine. Note: Duplicate case values are disallowed by the LangRef and verifier. Differential Revision: http://reviews.llvm.org/D11995 llvm-svn: 246125
* [PowerPC] Remove unnecessary braces in PPCVSXFMAMutateHal Finkel2015-08-261-3/+3
| | | | | | Address Eric's post-commit review of r245741. NFC. llvm-svn: 246121
* [NVPTX] Let NVPTX backend detect integer min and max patterns.Bjarke Hammersholt Roune2015-08-261-0/+64
| | | | | | | | | | | | | | Summary: Let NVPTX backend detect integer min and max patterns during isel and emit intrinsics that enable hardware support. Reviewers: jholewinski, meheff, jingyue Subscribers: arsenm, llvm-commits, meheff, jingyue, eliben, jholewinski Differential Revision: http://reviews.llvm.org/D12377 llvm-svn: 246107
* [ARM] Use BranchProbability::scale() to scale an integer with a probability ↵Cong Hou2015-08-261-9/+3
| | | | | | | | | | in ARMBaseInstrInfo.cpp, Previously in isProfitableToIfCvt() in ARMBaseInstrInfo.cpp, the multiplication between an integer and a branch probability is done manually in an unsafe way that may lead to overflow. This patch corrects those cases by using BranchProbability's member function scale() to avoid overflow (which stores the intermediate result in int64). Differential Revision: http://reviews.llvm.org/D12295 llvm-svn: 246106
* Assign weights to edges to jump table / bit test header when lowering switch ↵Cong Hou2015-08-262-11/+22
| | | | | | | | | | statement. Currently, when lowering switch statement and a new basic block is built for jump table / bit test header, the edge to this new block is not assigned with a correct weight. This patch collects the edge weight from all its successors and assign this sum of weights to the edge (and also the other fall-through edge). Test cases are adjusted accordingly. Differential Revision: http://reviews.llvm.org/D12166#fae6eca7 llvm-svn: 246104
* WebAssembly: NFC comment updateJF Bastien2015-08-261-1/+1
| | | | llvm-svn: 246101
* DI: Make Subprogram definitions 'distinct'Duncan P. N. Exon Smith2015-08-261-11/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Change `DIBuilder` always to produce 'distinct' nodes when creating `DISubprogram` definitions. I measured a ~5% memory improvement in the link step (of ld64) when using `-flto -g`. `DISubprogram`s are used in two ways in the debug info graph. Some are definitions, point at actual functions, and can't really be shared between compile units. With full debug info, these point down at their variables, forming uniquing cycles. These uniquing cycles are expensive to link between modules, since all unique nodes that reference them transitively need to be duplicated (see commit message for r244181 for more details). Others are declarations, primarily used for member functions in the type hierarchy. Definitions never show up there; instead, a definition points at its corresponding declaration node. I started by making all subprograms 'distinct'. However, that was too big a hammer: memory usage *increased* ~5% (net increase vs. this patch of ~10%) because the 'distinct' declarations undermine LTO type uniquing. This is a targeted fix for the definitions (where uniquing is an observable problem). A couple of notes: - There's an accompanying commit to update IRGen testcases in clang. - ^ That's what I'm using to test this commit. - In a follow-up, I'll change the verifier to require 'distinct' on definitions and add an upgrade to `BitcodeReader`. llvm-svn: 246098
* WebAssembly: handle private/internal globals.JF Bastien2015-08-261-22/+96
| | | | | | | | | | | | Things of note: - Other linkage types aren't handled yet. We'll figure it out with dynamic linking. - Special LLVM globals are either ignored, or error out for now. - TLS isn't supported yet (WebAssembly will have threads later). - There currently isn't a syntax for alignment, I left it in a comment so it's easy to hook up. - Undef is convereted to whatever the type's appropriate null value is. - assert versus report_fatal_error: follow what other AsmPrinters do, and assert only on what should have been caught elsewhere. llvm-svn: 246092
* [ms-inline-asm] Relax assertion around funky identifiers slightlyReid Kleckner2015-08-261-6/+8
| | | | | | | | | A corresponding clang change will make it so that clang can consume part of an assembler token. The assembler treats '.' as an identifier character while clang does not, so it's view of the token stream is a little different. llvm-svn: 246089
* [libFuzzer] fix minor inefficiency, PR24584Kostya Serebryany2015-08-261-1/+1
| | | | llvm-svn: 246087
* Fix LLVM C API for DataLayoutMehdi Amini2015-08-261-20/+15
| | | | | | | | | | | | | | | | | | | | | | | | | We removed access to the DataLayout on the TargetMachine and deprecated the C API function LLVMGetTargetMachineData() in r243114. However the way I tried to be backward compatible was broken: I changed the wrapper of the TargetMachine to be a structure that includes the DataLayout as well. However the TargetMachine is also wrapped by the ExecutionEngine, in the more classic way. A client using the TargetMachine wrapped by the ExecutionEngine and trying to get the DataLayout would break. It seems tricky to solve the problem completely in the C API implementation. This patch tries to address this backward compatibility in a more lighter way in the C++ API. The C API is restored in its original state and the removed C++ API is reintroduced, but privately. The C API is friended to the TargetMachine and should be the only consumer for this API. Reviewers: ributzka Differential Revision: http://reviews.llvm.org/D12263 From: Mehdi Amini <mehdi.amini@apple.com> llvm-svn: 246082
* AMDGPU: Delete dead codeMatt Arsenault2015-08-263-68/+4
| | | | | | | | | | | | | | | | | There is no context where s_mov_b64 is emitted and could potentially be moved to the VALU. It is currently only emitted for materializing immediates, which can't be dependent on vector sources. The immediate splitting is already done when selecting constants. I'm not sure what contexts if any the register splitting would have been used before. Also clean up using s_mov_b64 in place of v_mov_b64_pseudo, although this isn't required and just skips the extra step of eliminating the copy from the SReg_64. llvm-svn: 246080
* AMDGPU: Don't reprocess instructions when splitting i64 bcntMatt Arsenault2015-08-261-4/+5
| | | | llvm-svn: 246079
* AMDGPU: Fix not moving users of s_bfe_i64 to VALUMatt Arsenault2015-08-261-0/+2
| | | | | | | This wouldn't propagate to users of the original BFE and would hit a verifier error. llvm-svn: 246078
* AMDGPU: Don't create intermediate SALU instructionsMatt Arsenault2015-08-262-27/+44
| | | | | | | | | | | | When splitting 64-bit operations, create the correct VALU instructions immediately. This was splitting things like s_or_b64 into the two s_or_b32s and then pushing the new instructions onto the worklist. There's no reason we need to do this intermediate step. llvm-svn: 246077
* SelectionDAGBuilder: Fix SPDescriptor not resetting GuardRegMatthias Braun2015-08-261-0/+1
| | | | | | | | This was causing problems when some functions use a GuardReg and some don't as can happen when mixing SelectionDAG and FastISel generated functions. llvm-svn: 246075
* FastISel: Avoid adding a successor block twice for degenerate IR.Matthias Braun2015-08-261-1/+5
| | | | | | | | This fixes http://llvm.org/PR24581 Differential Revision: http://reviews.llvm.org/D12350 llvm-svn: 246074
* Expose hasLiveCondCodeDef as a member function of the X86InstrInfo class. NFCAndrew Kaylor2015-08-262-1/+5
| | | | | | | | | This takes the existing static function hasLiveCondCodeDef and makes it a member function of the X86InstrInfo class. This is a useful utility function that an upcoming change would like to use. NFC. Patch by: Kevin B. Smith Differential Revision: http://reviews.llvm.org/D12371 llvm-svn: 246073
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