| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Add support for parsing the ELF .type assembler directive. | Matt Fleming | 2010-05-21 | 2 | -0/+50 |
| | | | | | llvm-svn: 104316 | ||||
| * | Fix i64->f64 conversion, x86-64, -no-sse. A bit | Dale Johannesen | 2010-05-21 | 2 | -0/+33 |
| | | | | | | | | tricky since there's a 3rd 64-bit type, MMX vectors. PR 7135. llvm-svn: 104308 | ||||
| * | Change ARM scheduling default to list-hybrid if the target supports floating ↵ | Evan Cheng | 2010-05-21 | 1 | -1/+4 |
| | | | | | | | point instructions (and is not using soft float). llvm-svn: 104307 | ||||
| * | Rename -pre-RA-sched=hybrid to -pre-RA-sched=list-hybrid. | Evan Cheng | 2010-05-21 | 1 | -1/+1 |
| | | | | | llvm-svn: 104306 | ||||
| * | Simplify. | Devang Patel | 2010-05-21 | 1 | -16/+8 |
| | | | | | llvm-svn: 104302 | ||||
| * | Fix __crashreport_info__ declaration. | Daniel Dunbar | 2010-05-20 | 1 | -2/+2 |
| | | | | | llvm-svn: 104300 | ||||
| * | Allow targets more controls on what nodes are scheduled by reg pressure, ↵ | Evan Cheng | 2010-05-20 | 5 | -14/+37 |
| | | | | | | | what for latency in hybrid mode. llvm-svn: 104293 | ||||
| * | DominatorTree.getNode can return null for unreachable blocks. | Dan Gohman | 2010-05-20 | 1 | -1/+1 |
| | | | | | llvm-svn: 104290 | ||||
| * | Minor code cleanups. | Dan Gohman | 2010-05-20 | 1 | -8/+7 |
| | | | | | llvm-svn: 104287 | ||||
| * | Print a space after the colon. | Mikhail Glushenkov | 2010-05-20 | 1 | -2/+2 |
| | | | | | llvm-svn: 104279 | ||||
| * | Make Solve check its own post-condition, to reduce clutter in the | Dan Gohman | 2010-05-20 | 1 | -1/+2 |
| | | | | | | | top-level LSRInstance logic. llvm-svn: 104278 | ||||
| * | Add comments. | Dan Gohman | 2010-05-20 | 1 | -0/+16 |
| | | | | | llvm-svn: 104276 | ||||
| * | MC/X86: Add movq alias for movabsq, to allow matching 64-bit immediates with ↵ | Daniel Dunbar | 2010-05-20 | 1 | -0/+7 |
| | | | | | | | movq. llvm-svn: 104275 | ||||
| * | Rename variable. add comment. | Devang Patel | 2010-05-20 | 1 | -2/+5 |
| | | | | | llvm-svn: 104274 | ||||
| * | More code cleanups. Use iterators instead of indices when indices | Dan Gohman | 2010-05-20 | 1 | -22/+24 |
| | | | | | | | aren't needed. llvm-svn: 104273 | ||||
| * | X86: Model i64i32imm properly, as a subclass of all immediates. | Daniel Dunbar | 2010-05-20 | 3 | -2/+29 |
| | | | | | llvm-svn: 104272 | ||||
| * | X86: Fix immediate type of FOO64i32 operations. | Daniel Dunbar | 2010-05-20 | 1 | -10/+10 |
| | | | | | llvm-svn: 104271 | ||||
| * | Fix OptimizeShadowIV to set Changed. Change OptimizeLoopTermCond to set | Dan Gohman | 2010-05-20 | 1 | -8/+7 |
| | | | | | | | | | | Changed directly instead of using a return value. Rename FilterOutUndesirableDedicatedRegisters's Changed variable to distinguish it from LSRInstance's Changed member. llvm-svn: 104269 | ||||
| * | Add some comments. | Dan Gohman | 2010-05-20 | 1 | -0/+6 |
| | | | | | llvm-svn: 104268 | ||||
| * | Simplify this code. Don't do a DomTreeNode lookup for each visited block. | Dan Gohman | 2010-05-20 | 1 | -14/+5 |
| | | | | | llvm-svn: 104267 | ||||
| * | Refactor. | Devang Patel | 2010-05-20 | 2 | -37/+76 |
| | | | | | llvm-svn: 104265 | ||||
| * | Grammar fix. This is a test commit. | Matt Fleming | 2010-05-20 | 1 | -1/+1 |
| | | | | | llvm-svn: 104264 | ||||
| * | Minor code cleanups. | Dan Gohman | 2010-05-20 | 1 | -20/+11 |
| | | | | | llvm-svn: 104263 | ||||
| * | When canonicalizing icmp operand order to put the loop invariant | Dan Gohman | 2010-05-20 | 1 | -0/+1 |
| | | | | | | | | | | | | | operand on the left, the interesting operand is on the right. This fixes a bug where LSR was failing to recognize ICmpZero uses, which led it to be unable to reverse the induction variable in the attached testcase. Delete test/CodeGen/X86/stack-color-with-reg-2.ll, because its test is extremely fragile and hard to meaningfully update. llvm-svn: 104262 | ||||
| * | llvmc: Make segfault detection work on Win32. | Mikhail Glushenkov | 2010-05-20 | 1 | -21/+28 |
| | | | | | llvm-svn: 104261 | ||||
| * | Set Changed to true when canonicalizing ICmp operand order; even though | Dan Gohman | 2010-05-20 | 1 | -0/+1 |
| | | | | | | | it isn't a very interesting change, it's a change nonetheless. llvm-svn: 104260 | ||||
| * | Handle Neon v2f64 and v2i64 vector shuffles as register copies. | Bob Wilson | 2010-05-20 | 1 | -0/+18 |
| | | | | | | | This fixes the remaining issue with pr7167. llvm-svn: 104257 | ||||
| * | Remove dbg_value workaround and associated command line option | Jim Grosbach | 2010-05-20 | 1 | -20/+0 |
| | | | | | llvm-svn: 104254 | ||||
| * | Delete MMX_MOVQ64gmr. It was the same as MMX_MOVQ64mr, but it didn't | Dan Gohman | 2010-05-20 | 1 | -3/+0 |
| | | | | | | | have a pattern and it had an invalid encoding. llvm-svn: 104244 | ||||
| * | The PPC MFCR instruction implicitly uses all 8 of the CR | Dale Johannesen | 2010-05-20 | 5 | -21/+24 |
| | | | | | | | | | | | | | | | registers. Currently it is not so marked, which leads to VCMPEQ instructions that feed into it getting deleted. If it is so marked, local RA complains about this sequence: vreg = MCRF CR0 MFCR <kill of whatever preg got assigned to vreg> All current uses of this instruction are only interested in one of the 8 CR registers, so redefine MFCR to be a normal unary instruction with a CR input (which is emitted only as a comment). That avoids all problems. 7739628. llvm-svn: 104238 | ||||
| * | Strip llvm.dbg.lv also. | Devang Patel | 2010-05-20 | 1 | -0/+6 |
| | | | | | llvm-svn: 104236 | ||||
| * | Rename a variable to avoid shadowing. | Dan Gohman | 2010-05-20 | 1 | -2/+3 |
| | | | | | llvm-svn: 104234 | ||||
| * | Split DbgVariable. Eventually, variable info will be communicated through ↵ | Devang Patel | 2010-05-20 | 2 | -94/+111 |
| | | | | | | | frame index, or DBG_VALUE instruction, or collection of DBG_VALUE instructions. Plus each DbgVariable may not need a label. llvm-svn: 104233 | ||||
| * | Minor code simplification. | Dan Gohman | 2010-05-20 | 1 | -4/+4 |
| | | | | | llvm-svn: 104232 | ||||
| * | Fix assembly parsing and encoding of the pushf and popf family of | Dan Gohman | 2010-05-20 | 4 | -10/+31 |
| | | | | | | | instructions. llvm-svn: 104231 | ||||
| * | Set neverHasSideEffects on 64-bit pushf and popf, for consistency with | Dan Gohman | 2010-05-20 | 1 | -2/+2 |
| | | | | | | | 16-bit and 32-bit pushf and popf. llvm-svn: 104228 | ||||
| * | Move the code for deleting BaseRegs and LSRUses into helper functions, | Dan Gohman | 2010-05-20 | 1 | -5/+22 |
| | | | | | | | | and fix a bug that valgrind noticed where the code would std::swap an element with itself. llvm-svn: 104225 | ||||
| * | Reduce string trashing. | Benjamin Kramer | 2010-05-20 | 1 | -2/+2 |
| | | | | | llvm-svn: 104223 | ||||
| * | Add a hybrid bottom up scheduler that reduce register usage while avoiding | Evan Cheng | 2010-05-20 | 4 | -28/+141 |
| | | | | | | | | | | pipeline stall. It's useful for targets like ARM cortex-a8. NEON has a lot of long latency instructions so a strict register pressure reduction scheduler does not work well. Early experiments show this speeds up some NEON loops by over 30%. llvm-svn: 104216 | ||||
| * | Fix typo in comment. | Nick Lewycky | 2010-05-20 | 1 | -2/+2 |
| | | | | | llvm-svn: 104209 | ||||
| * | Define the x86 pause instruction. | Dan Gohman | 2010-05-20 | 1 | -0/+4 |
| | | | | | llvm-svn: 104204 | ||||
| * | Fix the sfence instruction to use MRM_F8 instead of MRM7r, since it | Dan Gohman | 2010-05-20 | 1 | -1/+2 |
| | | | | | | | | doesn't have a register operand. Also, use I instead of PSI, for consistency with mfence and lfence. llvm-svn: 104203 | ||||
| * | Partial code for emitting thread local bss data. | Eric Christopher | 2010-05-20 | 3 | -0/+9 |
| | | | | | llvm-svn: 104197 | ||||
| * | Teach LSR how to cope better with unrolled loops on targets where | Dan Gohman | 2010-05-19 | 1 | -3/+191 |
| | | | | | | | | | the addressing modes don't make this trivially easy. This allows it to avoid falling into the less precise heuristics in more cases. llvm-svn: 104186 | ||||
| * | Optimize away insertelement of an undef value. This shows up in | Bob Wilson | 2010-05-19 | 1 | -0/+4 |
| | | | | | | | | test/Codegen/ARM/reg_sequence.ll but it doesn't affect the generated code because the coalescer cleans it up. Radar 7998853. llvm-svn: 104185 | ||||
| * | fix rdar://7986634 - match instruction opcodes case insensitively. | Chris Lattner | 2010-05-19 | 1 | -1/+6 |
| | | | | | llvm-svn: 104183 | ||||
| * | Enable preserving debug information through post-RA scheduling | Jim Grosbach | 2010-05-19 | 1 | -1/+1 |
| | | | | | llvm-svn: 104175 | ||||
| * | Fix the post-RA instruction scheduler to handle instructions referenced by | Jim Grosbach | 2010-05-19 | 1 | -3/+3 |
| | | | | | | | more than one dbg_value instruction. rdar://7759363 llvm-svn: 104174 | ||||
| * | Code clean up. | Evan Cheng | 2010-05-19 | 1 | -7/+7 |
| | | | | | llvm-svn: 104173 | ||||
| * | Revert r104165. | Devang Patel | 2010-05-19 | 2 | -5/+13 |
| | | | | | llvm-svn: 104172 | ||||
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index : bcm5719-llvm | |
| Project Ortega BCM5719 LLVM | Raptor Computing Systems |
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