summaryrefslogtreecommitdiffstats
path: root/llvm/lib
Commit message (Collapse)AuthorAgeFilesLines
* Allow loop unrolling to get known trip counts from ScalarEvolution.Andrew Trick2011-08-112-7/+80
| | | | | | | | | | | | | SCEV unrolling can unroll loops with arbitrary induction variables. It is a prerequisite for -disable-iv-rewrite performance. It is also easily handles loops of arbitrary structure including multiple exits and is generally more robust. This is under a temporary option to avoid affecting default behavior for the next couple of weeks. It is needed so that I can checkin unit tests for updateUnloop. llvm-svn: 137384
* Remove the InterferenceResult class.Jakob Stoklund Olesen2011-08-111-32/+0
| | | | llvm-svn: 137381
* Eliminate the last use of InterferenceResult.Jakob Stoklund Olesen2011-08-112-63/+57
| | | | | | | | The Query class now holds two iterators instead of an InterferenceResult instance. The iterators are used as bookmarks for repeated collectInterferingVRegs calls. llvm-svn: 137380
* Enclose directive .cprestore with .set macro and nomacro to silence assemblerAkira Hatanaka2011-08-111-3/+9
| | | | | | warning. llvm-svn: 137378
* Remove no-longer-true comments. These are for the assembler, also.Jim Grosbach2011-08-111-52/+24
| | | | llvm-svn: 137375
* ARM STRT assembly parsing and encoding.Jim Grosbach2011-08-112-14/+30
| | | | llvm-svn: 137372
* Make the USAT16 operand decoder auto-generate-able.Owen Anderson2011-08-111-2/+2
| | | | llvm-svn: 137371
* Add another accidentally omitted predicate operand.Owen Anderson2011-08-111-0/+2
| | | | llvm-svn: 137370
* Add missing predicate operand on SMLA and friends.Owen Anderson2011-08-111-0/+2
| | | | llvm-svn: 137368
* ARM load shifted register pre-index fix shift value asm parser encoding.Jim Grosbach2011-08-111-1/+1
| | | | llvm-svn: 137367
* Handle new register classes in Thumb2 mode. Should fix the ARM buildbots.Owen Anderson2011-08-111-2/+4
| | | | llvm-svn: 137364
* Making SEL decodings auto-generate-able.Owen Anderson2011-08-111-2/+2
| | | | llvm-svn: 137363
* Add a dag combine to xform 256-bit shuffles into simple vectorBruno Cardoso Lopes2011-08-111-1/+54
| | | | | | | inserts and extracts. This simple combine makes us generate only 1 instruction instead of 11 in the v8 case. llvm-svn: 137362
* Tidy up comment.Jim Grosbach2011-08-111-2/+1
| | | | llvm-svn: 137359
* Fix decoding support for STREXD and LDREXD.Owen Anderson2011-08-112-2/+29
| | | | llvm-svn: 137356
* Remove more dead code.Jakob Stoklund Olesen2011-08-112-37/+3
| | | | | | | collectInterferingVRegs will be the primary function for interference checks. llvm-svn: 137354
* ARM STRH assembly parsing and encoding.Jim Grosbach2011-08-113-18/+60
| | | | llvm-svn: 137353
* Fix typos in comments, and delete an unused function.Dan Gohman2011-08-111-6/+2
| | | | llvm-svn: 137352
* Add isIndirectBranch flag.Akira Hatanaka2011-08-111-1/+2
| | | | llvm-svn: 137351
* Privatize an unused part of the LiveIntervalUnion::Query interface.Jakob Stoklund Olesen2011-08-112-19/+13
| | | | | | No clients are iterating over interference overlaps. llvm-svn: 137350
* Fix decoding for indexed STRB and LDRB. Fixes <rdar://problem/9926161>.Owen Anderson2011-08-111-0/+4
| | | | llvm-svn: 137347
* Remove some dead code.Jakob Stoklund Olesen2011-08-112-39/+0
| | | | | | | | The InterferenceResult iterator turned out to be less important than we thought it would be. LiveIntervalUnion clients want higher level information, like the list of interfering virtual registers. llvm-svn: 137346
* Tidy up. Remove unused template parameter.Jim Grosbach2011-08-112-11/+11
| | | | llvm-svn: 137345
* Improve operand validation for Thumb2 addressing modes.Owen Anderson2011-08-111-48/+50
| | | | llvm-svn: 137344
* ARM STRD assembly parsing and encoding.Jim Grosbach2011-08-113-62/+54
| | | | llvm-svn: 137342
* Fix for LoopInfo::updateUnloop. Remove subloop blocks from formerAndrew Trick2011-08-111-16/+29
| | | | | | | | | ancestor loops. I have a unit test that depends on scev-unroll, which unfortunately isn't checked in. But I will check it in when I can. llvm-svn: 137341
* Continue to tighten decoding by performing more operand validation.Owen Anderson2011-08-113-2/+75
| | | | llvm-svn: 137340
* Tidy up.Jim Grosbach2011-08-111-1/+0
| | | | llvm-svn: 137339
* ARM STRBT assembly parsing and encoding.Jim Grosbach2011-08-112-25/+37
| | | | llvm-svn: 137337
* ARM STR(immediate) assembly parsing and encoding.Jim Grosbach2011-08-112-3/+22
| | | | llvm-svn: 137331
* Tighten decoding of addrmode2 instructions to reject more UNPREDICTABLE cases.Owen Anderson2011-08-111-0/+2
| | | | llvm-svn: 137325
* Fix PR10492 by teaching MOVHLPS and MOVLPS mask matching to be more strict.Bruno Cardoso Lopes2011-08-111-2/+9
| | | | llvm-svn: 137324
* Tighten operand decoding of addrmode2 instruction. The offset register ↵Owen Anderson2011-08-112-2/+2
| | | | | | cannot be PC. llvm-svn: 137323
* Correct immediate range for shifter operands. Patch by James Molloy, with ↵Owen Anderson2011-08-112-4/+17
| | | | | | additional encoding fixes added by me. llvm-svn: 137322
* Plug a memory leak.Benjamin Kramer2011-08-111-3/+3
| | | | llvm-svn: 137321
* Improve error checking in the new ARM disassembler. Patch by James Molloy.Owen Anderson2011-08-111-116/+159
| | | | llvm-svn: 137320
* ARM push of a single register encodes as pre-indexed STR.Jim Grosbach2011-08-112-0/+23
| | | | | | | Per the ARM ARM, a 'push' of a single register encodes as an STR, not an STM. llvm-svn: 137318
* Cleanup. Another thorough review by Nick!Andrew Trick2011-08-111-6/+6
| | | | llvm-svn: 137317
* ARM pop of a single register encodes as post-indexed LDR.Jim Grosbach2011-08-112-0/+38
| | | | | | | Per the ARM ARM, a 'pop' of a single register encodes as an LDR, not an LDM. llvm-svn: 137316
* Add a comment, per Bruno's CR.Nadav Rotem2011-08-111-0/+3
| | | | llvm-svn: 137313
* [AVX] When joining two XMM registers into a YMM register, make sure that theNadav Rotem2011-08-111-0/+32
| | | | | | | lower XMM register gets in first. This will allow the SUBREG pattern to elliminate the first vector insertion. llvm-svn: 137310
* [AVX] If the data which is going to be saved is already in two XMM registersNadav Rotem2011-08-111-0/+23
| | | | | | | | | | | | | | | | (for example, after integer operation), do not pack the registers into a YMM before saving. Its better to save as two XMM registers. Before: vinsertf128 $1, %xmm3, %ymm0, %ymm3 vinsertf128 $0, %xmm1, %ymm3, %ymm1 vmovaps %ymm1, 416(%rsp) After: vmovaps %xmm3, 416+16(%rsp) vmovaps %xmm1, 416(%rsp) llvm-svn: 137308
* fix PR10605 / rdar://9930964 by adding a pretty scary missed check.Chris Lattner2011-08-111-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | It's somewhat surprising anything works without this. Before we would compile the testcase into: test: # @test movl $4, 8(%rdi) movl 8(%rdi), %eax orl %esi, %eax cmpl $32, %edx movl %eax, -4(%rsp) # 4-byte Spill je .LBB0_2 now we produce: test: # @test movl 8(%rdi), %eax movl $4, 8(%rdi) orl %esi, %eax cmpl $32, %edx movl %eax, -4(%rsp) # 4-byte Spill je .LBB0_2 llvm-svn: 137303
* Cleanup: Remove Int_ CVTSS2SI* formsBruno Cardoso Lopes2011-08-112-11/+23
| | | | llvm-svn: 137297
* Splats for v8i32/v8f32 can be handled by VPERMILPSY. This was causingBruno Cardoso Lopes2011-08-111-6/+6
| | | | | | infinite recursive calls in legalize. Fix PR10562 llvm-svn: 137296
* Use the splat index to generate the desired shuffle. Otherwise weBruno Cardoso Lopes2011-08-111-4/+4
| | | | | | | could only get undefs and the vector shuffle becomes an undef, generating wrong code. llvm-svn: 137295
* Fix X86TargetLowering::LowerExternalSymbol so that it actually works in ↵Eli Friedman2011-08-111-5/+16
| | | | | | | | non-trivial cases. This hasn't been an issue before because the function isn't normally called (but apparently is used to generate a tail-call to sin() on ELF x86-32 with PIC and SSE2). Fixes PR9693. llvm-svn: 137292
* Stay within 80 columns.Devang Patel2011-08-102-22/+34
| | | | llvm-svn: 137283
* ARM LDRT assembly parsing and encoding.Jim Grosbach2011-08-102-23/+24
| | | | llvm-svn: 137282
* Tidy up. 80 columns.Jim Grosbach2011-08-101-16/+18
| | | | llvm-svn: 137277
OpenPOWER on IntegriCloud