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* [X86][SSE] Vectorize CTTZ + CTTZ_ZERO_UNDEFSimon Pilgrim2015-09-191-4/+57
| | | | | | | | | | Now that we have fast vector CTPOP implementations we can use this to speed up vector CTTZ using the pattern (cttz(x) = ctpop((x & -x) - 1)) Additionally, for AVX512CD that provides lzcnt instructions we can use the pattern (cttz_undef(x) = (width - 1) - ctlz(x & -x)) Differential Revision: http://reviews.llvm.org/D12663 llvm-svn: 248091
* [InstCombine] Use SimplifyDemandedVectorEltsLow helper function. NFCI.Simon Pilgrim2015-09-191-17/+8
| | | | | | Use the SimplifyDemandedVectorEltsLow helper function introduced in D12680. llvm-svn: 248089
* AMDGPU: Remove dead codeMatt Arsenault2015-09-195-18/+2
| | | | | | | getCFGStructurizerRegClass is not used for SI, so move it into R600 specific stuff. llvm-svn: 248087
* NFC: Fix indentation and add braces to clarify nested of else-statement.Bob Wilson2015-09-191-2/+3
| | | | llvm-svn: 248086
* [PrologEpilogInserter] Minor refactoring.Maksim Panchenko2015-09-191-1/+1
| | | | | | Differential Revision: http://reviews.llvm.org/D12924 llvm-svn: 248084
* Test commit. Fix comment. NFC.Maksim Panchenko2015-09-191-1/+1
| | | | llvm-svn: 248082
* [InstCombine] FoldICmpCstShrCst failed for ashr when comparing against -1David Majnemer2015-09-191-1/+1
| | | | | | | | | (icmp eq (ashr C1, %V) -1) may have multiple answers if C1 is not a power of two and has the sign bit set. This fixes PR24873. llvm-svn: 248074
* [InstCombine] FoldICmpCstShrCst didn't handle icmps of -1 in the ashr case ↵David Majnemer2015-09-191-6/+10
| | | | | | correctly llvm-svn: 248073
* [IndVars] Widen more comparisons for non-negative induction varsSanjoy Das2015-09-181-3/+26
| | | | | | | | | | | | | | | | | | | | Summary: If an induction variable is provably non-negative, its sign extension is equal to its zero extension. This means narrow uses like icmp slt iNarrow %indvar, %rhs can be widened into icmp slt iWide zext(%indvar), sext(%rhs) Reviewers: atrick, mcrosier, hfinkel Subscribers: hfinkel, reames, llvm-commits Differential Revision: http://reviews.llvm.org/D12745 llvm-svn: 248045
* Update edge weights properly when merging blocks in if-conversion.Cong Hou2015-09-181-6/+70
| | | | | | | | In if-conversion, there is a utility function MergeBlocks() that is used to merge blocks. However, when new edges are built in this function the edge weight is either not provided or not updated properly, leading to a modified CFG with incorrect edge weights. This patch corrects this issue. Differential Revision: http://reviews.llvm.org/D12513 llvm-svn: 248030
* Limit the range of processors supported by ARM fast isel to v6 orEric Christopher2015-09-181-0/+4
| | | | | | | | later as that's all that is tested right now. Fixes PR24858. llvm-svn: 248027
* Clean up: Refactoring the hardcoded value of 6 for ↵Larisse Voufo2015-09-184-8/+23
| | | | | | FindAvailableLoadedValue()'s parameter MaxInstsToScan. (Complete version of r247497. See D12886) llvm-svn: 248022
* Make MachineScheduler debug output less confusing.James Y Knight2015-09-182-6/+31
| | | | | | At least...a little bit. llvm-svn: 248020
* Scaling up values in ARMBaseInstrInfo::isProfitableToIfCvt() before they are ↵Cong Hou2015-09-181-10/+17
| | | | | | | | | | scaled by a probability to avoid precision issue. In ARMBaseInstrInfo::isProfitableToIfCvt(), there is a simple cost model in which the number of cycles is scaled by a probability to estimate the cost. However, when the number of cycles is small (which is usually the case), there is a precision issue after the computation. To avoid this issue, this patch scales those cycles by 1024 (chosen to make the multiplication a litter faster) before they are scaled by the probability. Other variables are also scaled up for the final comparison. Differential Revision: http://reviews.llvm.org/D12742 llvm-svn: 248018
* SelectionDAGDumper: Leave out the <multiple use> markersMatthias Braun2015-09-181-3/+0
| | | | | | | | | They mostly clutter the output while it is still possible to see which node has multiple users without them. Differential Revision: http://reviews.llvm.org/D12569 llvm-svn: 248013
* SelectionDAGDumper: Avoid unnecessary newlinesMatthias Braun2015-09-181-4/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Before: t0 = EntryToken:ch t0: <multiple use> t0: <multiple use> t1 = CopyFromReg:v4f32,ch t0, Register:v4f32 %vreg0 t25 = IMPLICIT_DEF:v4f32 t26 = HADDPSrr:v4f32 t1, t25 t23 = CopyToReg:ch,glue t0, Register:v4f32 %XMM0, t26 t23: <multiple use> t23: <multiple use> t24 = RETQ:ch Register:v4f32 %XMM0, t23, t23:1 After: t0: <multiple use> t0: <multiple use> t1 = CopyFromReg:v4f32,ch t0, Register:v4f32 %vreg0 t26 = X86ISD::FHADD:v4f32 t1, undef:v4f32 t23 = CopyToReg:ch,glue t0, Register:v4f32 %XMM0, t26 t23: <multiple use> t21 = TargetConstant:i16<0> t23: <multiple use> t24 = X86ISD::RET_FLAG:ch t23, t21, Register:v4f32 %XMM0, t23:1 Differential Revision: http://reviews.llvm.org/D12568 llvm-svn: 248012
* SelectionDAGDumper: Hide [ID=X], [ORD=X] and source locations by default.Matthias Braun2015-09-181-16/+23
| | | | | | | | You can show them with the new -dag-dump-verbose switch. Differential Revision: http://reviews.llvm.org/D12566 llvm-svn: 248011
* SelectionDAG: Introduce PersistentID to SDNode for assert builds.Matthias Braun2015-09-182-4/+30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This gives us more human readable numbers to identify nodes in debug dumps. Before: 0x7fcbd9700160: ch = EntryToken 0x7fcbd985c7c8: i64 = Register %RAX ... 0x7fcbd9700160: <multiple use> 0x7fcbd985c578: i64,ch = MOV64rm 0x7fcbd985c6a0, 0x7fcbd985cc68, 0x7fcbd985c200, 0x7fcbd985cd90, 0x7fcbd985ceb8, 0x7fcbd9700160<Mem:LD8[@foo]> [ORD=2] 0x7fcbd985c8f0: ch,glue = CopyToReg 0x7fcbd9700160, 0x7fcbd985c7c8, 0x7fcbd985c578 [ORD=3] 0x7fcbd985c7c8: <multiple use> 0x7fcbd985c8f0: <multiple use> 0x7fcbd985c8f0: <multiple use> 0x7fcbd985ca18: ch = RETQ 0x7fcbd985c7c8, 0x7fcbd985c8f0, 0x7fcbd985c8f0:1 [ORD=3] Now: t0: ch = EntryToken t5: i64 = Register %RAX ... t0: <multiple use> t3: i64,ch = MOV64rm t10, t12, t11, t13, t14, t0<Mem:LD8[@foo]> [ORD=2] t6: ch,glue = CopyToReg t0, t5, t3 [ORD=3] t5: <multiple use> t6: <multiple use> t6: <multiple use> t7: ch = RETQ t5, t6, t6:1 [ORD=3] Differential Revision: http://reviews.llvm.org/D12564 llvm-svn: 248010
* [AArch64] Improved bitfield instruction selection.Geoff Berry2015-09-181-11/+67
| | | | | | | | | | | | | | | | | | Summary: For bitfield insert OR matching, check both operands for larger pattern first before checking for smaller pattern. Add pattern for unsigned bitfield insert-in-zero done with SHL+AND. Resolves PR21631. Reviewers: jmolloy, t.p.northover Subscribers: aemerson, rengolin, llvm-commits, mcrosier Differential Revision: http://reviews.llvm.org/D12908 llvm-svn: 248006
* Remove temporary file on signal.Rafael Espindola2015-09-181-1/+6
| | | | | | Without this lld leaves temporary files behind when it crashes. llvm-svn: 247994
* [mips][microMIPS] Fix an invalid read for lwm32 and reserved reglist values.Daniel Sanders2015-09-181-0/+6
| | | | | | | | | | | | | | | Summary: Some values of 'reglist' are reserved and cause the disassembler to read past the end of the Regs array. Treat lwm32's containing reserved values as invalid instructions. Reviewers: zoran.jovanovic Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D12959 llvm-svn: 247990
* [AArch64] Reorder cases to improve readability. NFC.Chad Rosier2015-09-181-9/+9
| | | | llvm-svn: 247989
* [AArch64] Remove some redundant cases. NFC.Chad Rosier2015-09-181-16/+8
| | | | llvm-svn: 247988
* Silencing a -Wsign-compare warning; NFC.Aaron Ballman2015-09-181-1/+1
| | | | llvm-svn: 247986
* [LazyValueInfo] Report nonnull range for nonnull pointersIgor Laevsky2015-09-181-2/+4
| | | | | | | | | | | | Currently LazyValueInfo will report only alloca's as having nonnull range. For loads with !nonnull metadata it will bailout with no additional information. Same is true for calls returning nonnull pointers. This change extends LazyValueInfo to handle additional nonnull instructions. Differential Revision: http://reviews.llvm.org/D12932 llvm-svn: 247985
* Support align attribute for return valuesArtur Pilipenko2015-09-182-1/+9
| | | | | | | | Reviewed By: reames Differential Revision: http://reviews.llvm.org/D12844 llvm-svn: 247984
* [Support] Reapply r245289 "Always wait for GraphViz before opening the viewer"Michael Kruse2015-09-181-1/+1
| | | | | | | | | | | | | The change was accidentally undone by r245290. Original log message: When calling DisplayGraph and a PS viewer is chosen, two programs are executed: The GraphViz generator and the PostScript viewer. Always wait for the generator to finish to ensure that the .ps file is written before opening the viewer for that file. DisplayGraph's wait parameter refers to whether to wait until the user closes the viewer. This happened on Windows and if none of the options to open the .dot file directly applies, also on Linux. Differential Revision: http://reviews.llvm.org/D11876 llvm-svn: 247980
* [WinEH] Moved funclet pads should be in relative orderDavid Majnemer2015-09-181-9/+5
| | | | | | | | | | | We shifted the MachineBasicBlocks to the end of the MachineFunction in DFS order. This will not ensure that MachineBasicBlocks which fell through to one another will remain contiguous. Instead, implement a stable sort algorithm for iplist. This partially reverts commit r214150. llvm-svn: 247978
* Whitespace. Indent with spaces instead of a tab.Bob Wilson2015-09-181-1/+1
| | | | llvm-svn: 247969
* [ShrinkWrap] Refactor the handling of infinite loop in the analysis.Quentin Colombet2015-09-171-9/+11
| | | | | | | | | - Strenghten the logic to be sure we hoist the restore point out of the current loop. (The fixes a bug with infinite loop, added as part of the patch.) - Walk over the exit blocks of the current loop to conver to the desired restore point in one iteration of the update loop. llvm-svn: 247958
* [opaque pointer types] Add an explicit pointee type to alias records in the IRDavid Blaikie2015-09-172-24/+41
| | | | | | | | | | Since aliases actually use and verify their explicit type already, no further invalid testing is required here. The invalid.test:ALIAS-TYPE-MISMATCH case catches errors due to emitting a non-pointee type in the new format or a non-pointer type in the old format. llvm-svn: 247952
* [bpf] expand indirect branchesAlexei Starovoitov2015-09-171-0/+1
| | | | | | | | BPF instruction set doesn't have indirect branches. Expand them. Reported by John Fastabend. llvm-svn: 247951
* Revert "(HEAD -> master, origin/master, origin/HEAD) RegisterPressure: Move ↵Matthias Braun2015-09-172-34/+36
| | | | | | | | | | LiveInRegs/LiveOutRegs from RegisterPressure to PressureTracker" This reverts commit r247943. Accidental commit, code review was not finished yet. llvm-svn: 247945
* RegisterPressure: Move LiveInRegs/LiveOutRegs from RegisterPressure to ↵Matthias Braun2015-09-172-36/+34
| | | | | | | | PressureTracker Differential Revision: http://reviews.llvm.org/D12814 llvm-svn: 247943
* MachineScheduler: Provide an option for node hiding cutoff and disable it by ↵Matthias Braun2015-09-171-1/+9
| | | | | | default llvm-svn: 247942
* [SPARC] Add mulscc.Joerg Sonnenberger2015-09-171-0/+4
| | | | llvm-svn: 247940
* fix typo; NFCSanjay Patel2015-09-171-1/+1
| | | | llvm-svn: 247938
* [WinEH] Add a funclet layout passDavid Majnemer2015-09-174-0/+101
| | | | | | | | | Windows EH funclets need to be contiguous. The FuncletLayout pass will ensure that the funclets are together and begin with a funclet entry MBB. Differential Revision: http://reviews.llvm.org/D12943 llvm-svn: 247937
* [WinEH] Make funclet return instrs pseudo instrsReid Kleckner2015-09-179-100/+99
| | | | | | | | | This makes catchret look more like a branch, and less like a weird use of BlockAddress. It also lets us get away from llvm.x86.seh.restoreframe, which relies on the old parentfpoffset label arithmetic. llvm-svn: 247936
* gvn small fixPiotr Padlewski2015-09-171-3/+1
| | | | | | http://reviews.llvm.org/D12928 llvm-svn: 247935
* [InstCombine] Added vector demanded bits support for SSE4A EXTRQ/INSERTQ ↵Simon Pilgrim2015-09-172-1/+83
| | | | | | | | | | instructions The SSE4A instructions EXTRQ/INSERTQ only use the lower 64-bits (or less) for many of their input vector operands and all of them have undefined upper 64-bits results. Differential Revision: http://reviews.llvm.org/D12680 llvm-svn: 247934
* Added MD_invariant_group to LLVMContextPiotr Padlewski2015-09-172-1/+8
| | | | | | http://reviews.llvm.org/D12926 llvm-svn: 247931
* Restore "Function bitcode index in Value Symbol Table and lazy reading support"Teresa Johnson2015-09-172-40/+306
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit r247898 (which reverted r247894). Patch fixed to address two issues exposed by buildbots: - unused variable warning in NDEBUG mode - std::initializer_list lifetime issue causing test failures Original Summary: Support for including the function bitcode indices in the Value Symbol Table. This requires writing the VST after the function blocks, which in turn requires a new VST forward declaration record encoding the offset of the full VST (which is backpatched to contain the offset after the VST is written). This patch also enables the lazy function reader to use the new function indices out of the VST. This support will be used by ThinLTO as well, which will be in a follow on patch. Backwards compatibility with older bitcode files is maintained. A new test is also included. The bitcode format (used for the lazy reader as well as the upcoming ThinLTO patches) came out of discussions with Duncan and others and is described here: https://drive.google.com/file/d/0B036uwnWM6RWdnBLakxmeDdOeXc/view Reviewers: dexonsmith, davidxl, joker.eph Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D12536 llvm-svn: 247927
* [SCEV] Use auto instead of full iterator type; NFCI.Sanjoy Das2015-09-171-2/+1
| | | | llvm-svn: 247919
* [WinEH] Add and use hasEHPadSuccessor instead of getLandingPadSuccessorReid Kleckner2015-09-174-2/+10
| | | | | | | | | | | | getLandingPadSuccessor assumes that each invoke can have at most one EH pad successor, but WinEH invokes can have more than one. Two out of three callers of getLandingPadSuccessor don't use the returned landingpad, so we can make them use this simple predicate instead. Eventually we'll have to circle back and fix SplitKit.cpp so that register allocation works. Baby steps. llvm-svn: 247904
* Test commit.Zia Ansari2015-09-171-1/+1
| | | | llvm-svn: 247901
* Revert "Function bitcode index in Value Symbol Table and lazy reading support"Teresa Johnson2015-09-172-299/+40
| | | | | | | | | | Temporarily revert to fix some buildbot issues. One is a minor issue with a variable unused in NDEBUG mode. More concerning are some test failures on win7 that I need to dig into. This reverts commit 4e66a74543459832cfd571db42b4543580ae1d1d. llvm-svn: 247898
* [mips] Add assembler support for the .cprestore directive.Daniel Sanders2015-09-173-13/+159
| | | | | | | | | | | | | | | | | | Summary: This assembler directive is used in O32 PIC to restore the current function's $gp after executing JAL's. The $gp is first stored on the stack at a user-specified offset. It has the following format: ".cprestore 8" (where 8 is the offset). This fixes llvm.org/PR20967. Patch by Toma Tabacu. Reviewers: seanbruno, tomatabacu Subscribers: brooks, seanbruno, emaste, llvm-commits Differential Revision: http://reviews.llvm.org/D6267 llvm-svn: 247897
* Function bitcode index in Value Symbol Table and lazy reading supportTeresa Johnson2015-09-172-40/+299
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: Support for including the function bitcode indices in the Value Symbol Table. This requires writing the VST after the function blocks, which in turn requires a new VST forward declaration record encoding the offset of the full VST (which is backpatched to contain the offset after the VST is written). This patch also enables the lazy function reader to use the new function indices out of the VST. This support will be used by ThinLTO as well, which will be in a follow on patch. Backwards compatibility with older bitcode files is maintained. A new test is also included. The bitcode format (used for the lazy reader as well as the upcoming ThinLTO patches) came out of discussions with Duncan and others and is described here: https://drive.google.com/file/d/0B036uwnWM6RWdnBLakxmeDdOeXc/view Reviewers: dexonsmith, davidxl, joker.eph Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D12536 llvm-svn: 247894
* Refactor string encoding checks in BitcodeWriter (NFC)Teresa Johnson2015-09-171-14/+23
| | | | llvm-svn: 247891
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