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* Added patterns for ADD8rm, etc. These fold load operands. e.g. addb 4(%esp), %alEvan Cheng2005-12-091-3/+6
| | | | llvm-svn: 24648
* Avoid emitting two tabs when switching to a named sectionChris Lattner2005-12-091-2/+2
| | | | llvm-svn: 24646
* Teach the PPC backend about the ctor and dtor list when not using __main andChris Lattner2005-12-091-0/+34
| | | | | | linking the entire program into one bc file. llvm-svn: 24645
* Teach legalize how to promote sext_inreg to fix a problem Andrew pointedChris Lattner2005-12-091-0/+5
| | | | | | out to me. llvm-svn: 24644
* it helps if your conditionals are not reversedAndrew Lenharth2005-12-091-9/+9
| | | | llvm-svn: 24641
* improve code insertion in two ways:Chris Lattner2005-12-081-20/+26
| | | | | | | | | | | | | 1. Only forward subst offsets into loads and stores, not into arbitrary things, where it will likely become a load. 2. If the source is a cast from pointer, forward subst the cast as well, allowing us to fold the cast away (improving cases when the cast is from an alloca or global). This hasn't been fully tested, but does appear to further reduce register pressure and improve code. Lets let the testers grind on it a bit. :) llvm-svn: 24640
* Add another important case we missChris Lattner2005-12-081-0/+19
| | | | llvm-svn: 24639
* Added support for ComplexPattern.Evan Cheng2005-12-081-0/+21
| | | | llvm-svn: 24638
* Added explicit type field to ComplexPattern.Evan Cheng2005-12-081-2/+2
| | | | llvm-svn: 24637
* * Added intelligence to X86 LEA addressing mode matching routine so it returnsEvan Cheng2005-12-082-84/+103
| | | | | | | false if the match is not profitable. e.g. leal 1(%eax), %eax. * Added patterns for X86 integer loads and LEA32. llvm-svn: 24635
* Fix a crash where ConstantVec nodes were being generated with the wrongNate Begeman2005-12-072-2/+30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | type when the target did not support them. Also teach Legalize how to expand ConstantVecs. This allows us to generate _test: lwz r2, 12(r3) lwz r4, 8(r3) lwz r5, 4(r3) lwz r6, 0(r3) addi r2, r2, 4 addi r4, r4, 3 addi r5, r5, 2 addi r6, r6, 1 stw r2, 12(r3) stw r4, 8(r3) stw r5, 4(r3) stw r6, 0(r3) blr For: void %test(%v4i *%P) { %T = load %v4i* %P %S = add %v4i %T, <int 1, int 2, int 3, int 4> store %v4i %S, %v4i * %P ret void } On PowerPC. llvm-svn: 24633
* Only transform (sext (truncate x)) -> (sextinreg x) if before legalize orChris Lattner2005-12-071-1/+3
| | | | | | if the target supports the resultant sextinreg llvm-svn: 24632
* X86 doesn't support sextinreg for 8-bit things either.Chris Lattner2005-12-071-0/+1
| | | | llvm-svn: 24631
* Teach the dag combiner to turn a truncate/sign_extend pair into a sextinregChris Lattner2005-12-071-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | when the types match up. This allows the X86 backend to compile: sbyte %toggle_value(sbyte* %tmp.1) { %tmp.2 = load sbyte* %tmp.1 ret sbyte %tmp.2 } to this: _toggle_value: mov %EAX, DWORD PTR [%ESP + 4] movsx %EAX, BYTE PTR [%EAX] ret instead of this: _toggle_value: mov %EAX, DWORD PTR [%ESP + 4] movsx %EAX, BYTE PTR [%EAX] movsx %EAX, %AL ret noticed in Shootout/objinst. -Chris llvm-svn: 24630
* fix divide and remainderAndrew Lenharth2005-12-062-13/+14
| | | | llvm-svn: 24628
* Silence another annoying GCC warningChris Lattner2005-12-061-1/+1
| | | | llvm-svn: 24627
* more decent branches for FP. I might have to make some intermediate nodes ↵Andrew Lenharth2005-12-061-2/+33
| | | | | | to actually be able to use the DAG for FPcmp llvm-svn: 24625
* OK, this does wonders for broken stuffAndrew Lenharth2005-12-061-0/+1
| | | | llvm-svn: 24624
* Collapsing node if variable length struct with final field of length zeroSumant Kowshik2005-12-061-1/+18
| | | | llvm-svn: 24621
* Fix test/Regression/Linker/2005-12-06-AppendingZeroLengthArrays.ll andChris Lattner2005-12-061-0/+2
| | | | | | | PR662. Thanks to Markus for providing me with a ton of files to reproduce the problem! llvm-svn: 24619
* Teach the SelectionDAG ISel how to turn ConstantPacked values intoNate Begeman2005-12-064-5/+62
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | constant nodes with vector types. Also teach the asm printer how to print ConstantPacked constant pool entries. This allows us to generate altivec code such as the following, which adds a vector constantto a packed float. LCPI1_0: <4 x float> < float 0.0e+0, float 0.0e+0, float 0.0e+0, float 1.0e+0 > .space 4 .space 4 .space 4 .long 1065353216 ; float 1 .text .align 4 .globl _foo _foo: lis r2, ha16(LCPI1_0) la r2, lo16(LCPI1_0)(r2) li r4, 0 lvx v0, r4, r2 lvx v1, r4, r3 vaddfp v0, v1, v0 stvx v0, r4, r3 blr For the llvm code: void %foo(<4 x float> * %a) { entry: %tmp1 = load <4 x float> * %a; %tmp2 = add <4 x float> %tmp1, < float 0.0, float 0.0, float 0.0, float 1.0 > store <4 x float> %tmp2, <4 x float> *%a ret void } llvm-svn: 24616
* Use new PPC-specific nodes to represent shifts which require the 6-bitChris Lattner2005-12-063-15/+40
| | | | | | | | | amount handling that PPC provides. These are generated by the lowering code and prevents the dag combiner from assuming (rightfully) that the shifts don't only look at 5 bits. This fixes a miscompilation of crafty with the new front-end. llvm-svn: 24615
* added instructions with inverted immediatesAndrew Lenharth2005-12-062-32/+23
| | | | llvm-svn: 24614
* yea, it helps to have your path set right when testingAndrew Lenharth2005-12-051-2/+4
| | | | llvm-svn: 24613
* These never trigger, but whateverAndrew Lenharth2005-12-052-9/+40
| | | | llvm-svn: 24612
* Remove unnecessary let hasCtrlDep=1 now it can be inferred.Evan Cheng2005-12-051-27/+25
| | | | llvm-svn: 24611
* move this over to the dagAndrew Lenharth2005-12-052-10/+9
| | | | llvm-svn: 24609
* getRawValue zero extens for unsigned values, use getsextvalue so that weChris Lattner2005-12-051-3/+3
| | | | | | | know that small negative values fit into the immediate field of addressing modes. llvm-svn: 24608
* fix constant pool loadsAndrew Lenharth2005-12-051-1/+1
| | | | llvm-svn: 24607
* Fix the #1 code quality problem that I have seen on X86 (and it also affectsChris Lattner2005-12-051-6/+162
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | PPC and other targets). In a particular, consider code like this: struct Vector3 { double x, y, z; }; struct Matrix3 { Vector3 a, b, c; }; double dot(Vector3 &a, Vector3 &b) { return a.x * b.x + a.y * b.y + a.z * b.z; } Vector3 mul(Vector3 &a, Matrix3 &b) { Vector3 r; r.x = dot( a, b.a ); r.y = dot( a, b.b ); r.z = dot( a, b.c ); return r; } void transform(Matrix3 &m, Vector3 *x, int n) { for (int i = 0; i < n; i++) x[i] = mul( x[i], m ); } we compile transform to a loop with all of the GEP instructions for indexing into 'm' pulled out of the loop (9 of them). Because isel occurs a bb at a time we are unable to fold the constant index into the loads in the loop, leading to PPC code that looks like this: LBB3_1: ; no_exit.preheader li r2, 0 addi r6, r3, 64 ;; 9 values live across the loop body! addi r7, r3, 56 addi r8, r3, 48 addi r9, r3, 40 addi r10, r3, 32 addi r11, r3, 24 addi r12, r3, 16 addi r30, r3, 8 LBB3_2: ; no_exit lfd f0, 0(r30) lfd f1, 8(r4) fmul f0, f1, f0 lfd f2, 0(r3) ;; no constant indices folded into the loads! lfd f3, 0(r4) lfd f4, 0(r10) lfd f5, 0(r6) lfd f6, 0(r7) lfd f7, 0(r8) lfd f8, 0(r9) lfd f9, 0(r11) lfd f10, 0(r12) lfd f11, 16(r4) fmadd f0, f3, f2, f0 fmul f2, f1, f4 fmadd f0, f11, f10, f0 fmadd f2, f3, f9, f2 fmul f1, f1, f6 stfd f0, 0(r4) fmadd f0, f11, f8, f2 fmadd f1, f3, f7, f1 stfd f0, 8(r4) fmadd f0, f11, f5, f1 addi r29, r4, 24 stfd f0, 16(r4) addi r2, r2, 1 cmpw cr0, r2, r5 or r4, r29, r29 bne cr0, LBB3_2 ; no_exit uh, yuck. With this patch, we now sink the constant offsets into the loop, producing this code: LBB3_1: ; no_exit.preheader li r2, 0 LBB3_2: ; no_exit lfd f0, 8(r3) lfd f1, 8(r4) fmul f0, f1, f0 lfd f2, 0(r3) lfd f3, 0(r4) lfd f4, 32(r3) ;; much nicer. lfd f5, 64(r3) lfd f6, 56(r3) lfd f7, 48(r3) lfd f8, 40(r3) lfd f9, 24(r3) lfd f10, 16(r3) lfd f11, 16(r4) fmadd f0, f3, f2, f0 fmul f2, f1, f4 fmadd f0, f11, f10, f0 fmadd f2, f3, f9, f2 fmul f1, f1, f6 stfd f0, 0(r4) fmadd f0, f11, f8, f2 fmadd f1, f3, f7, f1 stfd f0, 8(r4) fmadd f0, f11, f5, f1 addi r6, r4, 24 stfd f0, 16(r4) addi r2, r2, 1 cmpw cr0, r2, r5 or r4, r6, r6 bne cr0, LBB3_2 ; no_exit This is much nicer as it reduces register pressure in the loop a lot. On X86, this takes the function from having 9 spilled registers to 2. This should help some spec programs on X86 (gzip?) This is currently only enabled with -enable-gep-isel-opt to allow perf testing tonight. llvm-svn: 24606
* Add a flag to Module::getGlobalVariable to allow it to return vars withChris Lattner2005-12-051-7/+7
| | | | | | | | internal linkage. Patch provided by Evan Jones, thanks! llvm-svn: 24604
* Wrap a long line, never internalize llvm.used.Chris Lattner2005-12-051-2/+6
| | | | llvm-svn: 24602
* Several things:Chris Lattner2005-12-051-24/+32
| | | | | | | | | | | | | 1. Remove redundant type casts now that PR673 is implemented. 2. Implement the OUT*ir instructions correctly. The port number really *is* a 16-bit value, but the patterns should only match if the number is 0-255. Update the patterns so they now match. 3. Fix patterns for shifts to reflect that the shift amount is always an i8, not an i16 as they were believed to be before. This previous fib stopped working when we started knowing that CL has type i8. 4. Change use of i16i8imm in SH*ri patterns to all be imm. llvm-svn: 24599
* On some targets (e.g. X86), shift amounts are not the same as the valueChris Lattner2005-12-051-3/+6
| | | | | | being shifted. Don't assume they are. llvm-svn: 24598
* Add some explicit type casts so that tblgen knows the type of the ↵Chris Lattner2005-12-051-6/+6
| | | | | | shiftamount, which is not necessarily the same as the type being shifted. llvm-svn: 24595
* Add some explicit type casts so that tblgen knows the type of the shiftChris Lattner2005-12-051-5/+5
| | | | | | amount, which is not necessarily the same as the type being shifted. llvm-svn: 24594
* The basic fneg cases are already autogen'dChris Lattner2005-12-041-4/+2
| | | | llvm-svn: 24592
* Autogen matching code for ADJCALLSTACK[UP|DOWN], thanks to Evan's tblgenChris Lattner2005-12-042-11/+12
| | | | | | improvements. llvm-svn: 24591
* Finish moving uncond br over to .td file, remove from .cpp file.Chris Lattner2005-12-042-4/+2
| | | | llvm-svn: 24590
* Define BR in the .td file now that Evan made tblgen smarter.Chris Lattner2005-12-042-5/+10
| | | | llvm-svn: 24589
* Added isel patterns for RET, JMP, and WRITEPORT.Evan Cheng2005-12-041-39/+53
| | | | llvm-svn: 24588
* * Added instruction property hasCtrlDep for those which r/w control-flowEvan Cheng2005-12-042-3/+27
| | | | | | | | | | | chains. * Added DAG node property SDNPHasChain for nodes which r/w control-flow chains. * Renamed SDTVT to SDTOther. * Added several new SDTypeProfiles for BR, BRCOND, RET, and WRITEPORT. * Added SDNode definitions for BR, BRCOND, RET, and WRITEPORT. llvm-svn: 24586
* Fix PR672 another way which should be more robustChris Lattner2005-12-041-16/+14
| | | | llvm-svn: 24585
* dbg.stoppoint returns a value, don't forget to init itChris Lattner2005-12-031-0/+1
| | | | llvm-svn: 24583
* Fix SimplifyCFG/2005-12-03-IncorrectPHIFold.llChris Lattner2005-12-031-8/+14
| | | | llvm-svn: 24581
* Fix test/Regression/ExecutionEngine/2005-12-02-TailCallBug.ll and PR672.Chris Lattner2005-12-031-0/+14
| | | | | | | | This also fixes 177.mesa, the only program that fails with --enable-x86-fastcc turned on. Given a clean nightly tester run, we should be able to turn it on by default! llvm-svn: 24578
* bah, must generate all resultsAndrew Lenharth2005-12-021-2/+8
| | | | llvm-svn: 24574
* cycle counter fixAndrew Lenharth2005-12-021-0/+6
| | | | llvm-svn: 24573
* add a noteChris Lattner2005-12-021-0/+6
| | | | llvm-svn: 24572
* Don't remove two operand, two result nodes from the binary ops map. TheseChris Lattner2005-12-011-36/+39
| | | | | | | | should come from the arbitrary ops map. This fixes Regression/CodeGen/PowerPC/2005-12-01-Crash.ll llvm-svn: 24571
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