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* Added the infrastructute necessary for MIPS JIT support. Patch by VladimirBruno Cardoso Lopes2011-07-219-3/+519
| | | | | | | | Stefanovic. I removed the part that actually emits the instructions cause I want that to get in better shape first and in incremental steps. This also makes it easier to review the upcoming parts. llvm-svn: 135678
* Make better use of ConstantExpr::getGetElementPtr's InBounds parameter.Jay Foad2011-07-215-31/+25
| | | | llvm-svn: 135676
* Convert ConstantExpr::getGetElementPtr andJay Foad2011-07-2113-72/+57
| | | | | | ConstantExpr::getInBoundsGetElementPtr to use ArrayRef. llvm-svn: 135673
* move tier out of an anonymous namespace, it doesn't make senseChris Lattner2011-07-215-39/+38
| | | | | | | | to for it to be an an anon namespace and be in a header. Eliminate some extraenous uses of tie. llvm-svn: 135669
* - Register v16i16 as valid VR256 register classBruno Cardoso Lopes2011-07-212-19/+22
| | | | | | | | - Add more bitcasts for v16i16 - Since 135661 and 135662 already added the splat logic, just add one more splat test for v16i16 llvm-svn: 135663
* Add support for 256-bit versions of VPERMIL instruction. This is a newBruno Cardoso Lopes2011-07-217-0/+121
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | instruction introduced in AVX, which can operate on 128 and 256-bit vectors. It considers a 256-bit vector as two independent 128-bit lanes. It can permute any 32 or 64 elements inside a lane, and restricts the second lane to have the same permutation of the first one. With the improved splat support introduced early today, adding codegen for this instruction enable more efficient 256-bit code: Instead of: vextractf128 $0, %ymm0, %xmm0 punpcklbw %xmm0, %xmm0 punpckhbw %xmm0, %xmm0 vinsertf128 $0, %xmm0, %ymm0, %ymm1 vinsertf128 $1, %xmm0, %ymm1, %ymm0 vextractf128 $1, %ymm0, %xmm1 shufps $1, %xmm1, %xmm1 movss %xmm1, 28(%rsp) movss %xmm1, 24(%rsp) movss %xmm1, 20(%rsp) movss %xmm1, 16(%rsp) vextractf128 $0, %ymm0, %xmm0 shufps $1, %xmm0, %xmm0 movss %xmm0, 12(%rsp) movss %xmm0, 8(%rsp) movss %xmm0, 4(%rsp) movss %xmm0, (%rsp) vmovaps (%rsp), %ymm0 We get: vextractf128 $0, %ymm0, %xmm0 punpcklbw %xmm0, %xmm0 punpckhbw %xmm0, %xmm0 vinsertf128 $0, %xmm0, %ymm0, %ymm1 vinsertf128 $1, %xmm0, %ymm1, %ymm0 vpermilps $85, %ymm0, %ymm0 llvm-svn: 135662
* Improve splat promotion to handle AVX types: v32i8 and v16i16. AlsoBruno Cardoso Lopes2011-07-211-24/+87
| | | | | | | | | refactor the code and add a bunch of comments. The final shuffle emitted by handling 256-bit types is suitable for the VPERM shuffle instruction which is going to be introduced in a next commit (with a testcase which cover this commit) llvm-svn: 135661
* Add aditional patterns for vextractf128 instructionBruno Cardoso Lopes2011-07-211-0/+8
| | | | llvm-svn: 135660
* Add aditional patterns for vinsertf128 instructionBruno Cardoso Lopes2011-07-211-0/+8
| | | | llvm-svn: 135659
* Add v16i16 type to VR256 classBruno Cardoso Lopes2011-07-211-2/+2
| | | | llvm-svn: 135658
* Move code around. No functionality changesBruno Cardoso Lopes2011-07-211-65/+78
| | | | llvm-svn: 135657
* Tidy up codeBruno Cardoso Lopes2011-07-211-15/+5
| | | | llvm-svn: 135656
* LSR, correct fix for rdar://9786536. Silly casting bug.Andrew Trick2011-07-211-2/+2
| | | | llvm-svn: 135654
* LSR must sometimes sign-extend before generating double constants.Andrew Trick2011-07-211-3/+10
| | | | | | rdar://9786536 llvm-svn: 135650
* Mark instructions which are part of the frame setup with the ↵Bill Wendling2011-07-211-9/+20
| | | | | | MachineInstr::FrameSetup flag. llvm-svn: 135645
* LSR crashes on an empty IVUsers list.Andrew Trick2011-07-211-0/+3
| | | | | | rdar://9786536 llvm-svn: 135644
* X86 is the only target that uses coff format. This should fixes test ↵Evan Cheng2011-07-201-2/+3
| | | | | | failures running on Windows, Cygwin, or MingW hosts. llvm-svn: 135639
* Sink ARMMCExpr and ARMAddressingModes into MC layer. First step to separate ↵Evan Cheng2011-07-2029-192/+200
| | | | | | ARM MC code from target. llvm-svn: 135636
* Remove unused function.Bill Wendling2011-07-201-64/+0
| | | | llvm-svn: 135635
* Remove the now defunct getCompactUnwindEncoding method from the frame ↵Bill Wendling2011-07-202-118/+0
| | | | | | lowering code. llvm-svn: 135634
* Refactor.Devang Patel2011-07-202-31/+42
| | | | llvm-svn: 135633
* There are two ways to map a variable to its lexical scope. Lexical scope ↵Devang Patel2011-07-202-2/+16
| | | | | | information is embedded in MDNode describing the variable. It is also available as a part of DebugLoc attached with DBG_VALUE instruction. DebugLoc attached with an instruction is less reliable in optimized code so use information embedded in the MDNode. llvm-svn: 135629
* Clean up includes of llvm/Analysis/ConstantFolding.h so it's included where ↵Eli Friedman2011-07-205-1/+4
| | | | | | it's used and not included where it isn't. llvm-svn: 135628
* While emitting constant value, look through derived type and use underlying ↵Devang Patel2011-07-201-14/+23
| | | | | | basic type to determine size and signness of the constant value. llvm-svn: 135627
* ARM PKH shift ammount operand printing tweaks.Jim Grosbach2011-07-206-18/+39
| | | | | | | | | | Move the shift operator and special value (32 encoded as 0 for PKHTB) handling into the instruction printer. This cleans up a bit of the disassembler special casing for these instructions, more easily handles not printing the operand at all for "lsl #0" and prepares for correct asm parsing of these operands. llvm-svn: 135626
* Bring LICM into compliance with the new "Memory Model for Concurrent ↵Eli Friedman2011-07-201-18/+30
| | | | | | Operations" in LangRef. llvm-svn: 135625
* Tidy up a bit.Jim Grosbach2011-07-203-12/+7
| | | | | | | Move common definitions for ARM and Thumb2 into ARMInstrFormats.td and rename them to be a bit more descriptive that they're for the PKH instructions. llvm-svn: 135617
* ARM: Tidy up representation of PKH instruction.Jim Grosbach2011-07-205-37/+35
| | | | | | | | | The shift type is implied by the instruction (PKHBT vs. PKHTB) and so shouldn't be also encoded as part of the shift value immediate. Otherwise we're able to represent invalid instructions, plus it needlessly complicates the representation. Preparatory work for asm parsing of these instructions. llvm-svn: 135616
* Fix cmake again :)Benjamin Kramer2011-07-201-1/+0
| | | | llvm-svn: 135613
* Goodbye TargetAsmInfo. This eliminate last bit of CodeGen and Target in llvm-mc.Evan Cheng2011-07-2019-213/+73
| | | | | | | There is still a bit more refactoring left to do in Targets. But we are now very close to fixing all the layering issues in MC. llvm-svn: 135611
* Extend the hack for _GLOBAL_OFFSET_TABLE_ slightly; PR10389.Eli Friedman2011-07-201-1/+3
| | | | llvm-svn: 135607
* ARM assembly parsing of MUL instruction.Jim Grosbach2011-07-201-1/+2
| | | | | | | Correctly handle 's' bit and predication suffices. Add parsing and encoding tests. llvm-svn: 135596
* PR10421: Fix a straightforward bug in the widening logic for CONCAT_VECTORS.Eli Friedman2011-07-201-5/+5
| | | | llvm-svn: 135595
* Initialize the EHFrameSection pointer to zero.Benjamin Kramer2011-07-201-0/+1
| | | | | | This should fix the spurious buildbot errors. llvm-svn: 135594
* Fix a GCC warning.Jay Foad2011-07-201-2/+2
| | | | llvm-svn: 135581
* - Move CodeModel from a TargetMachine global option to MCCodeGenInfo.Evan Cheng2011-07-2047-195/+184
| | | | | | | | - Introduce JITDefault code model. This tells targets to set different default code model for JIT. This eliminates the ugly hack in TargetMachine where code model is changed after construction. llvm-svn: 135580
* Include MCRegisterInfo to eliminate a compilation warning.Evan Cheng2011-07-201-1/+2
| | | | llvm-svn: 135575
* Fix the CMake build.Francois Pichet2011-07-201-0/+1
| | | | llvm-svn: 135573
* Add MCObjectFileInfo and sink the MCSections initialization code fromEvan Cheng2011-07-2017-582/+595
| | | | | | | | TargetLoweringObjectFileImpl down to MCObjectFileInfo. TargetAsmInfo is done to one last method. It's *almost* gone! llvm-svn: 135569
* indvars: Added getInsertPointForUses to find a valid place to truncate the IV.Andrew Trick2011-07-201-15/+32
| | | | llvm-svn: 135568
* indvars -disable-iv-rewrite: Add NarrowIVDefUse to cache def-useAndrew Trick2011-07-201-54/+61
| | | | | | | info. Holding Use* pointers is bad form even though it happened to work in this case. llvm-svn: 135566
* X86Subtarget.h: Assume "x86_64-cygwin", though it has not been released yet, ↵NAKAMURA Takumi2011-07-201-1/+2
| | | | | | to appease test/CodeGen/X86 on cygwin. llvm-svn: 135564
* Extra semi-colon.Eric Christopher2011-07-201-1/+1
| | | | llvm-svn: 135561
* indvars -disable-iv-rewrite fix: derived GEP IVsAndrew Trick2011-07-201-0/+6
| | | | llvm-svn: 135558
* Don't leak CodeGenInfos.Benjamin Kramer2011-07-201-1/+3
| | | | llvm-svn: 135555
* Change name of class.Akira Hatanaka2011-07-201-23/+23
| | | | llvm-svn: 135550
* Define classes for definitions of atomic instructions.Akira Hatanaka2011-07-201-106/+42
| | | | llvm-svn: 135546
* Lower memory barriers to sync instructions.Akira Hatanaka2011-07-193-2/+28
| | | | llvm-svn: 135537
* Fix an obvious typo that's preventing x86 (32-bit) from using .literal16.Evan Cheng2011-07-191-1/+1
| | | | llvm-svn: 135535
* PR10386: Don't try to split an edge from an indirectbr.Eli Friedman2011-07-191-2/+9
| | | | llvm-svn: 135534
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