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* [WebAssembly] Add COMDAT supportSam Clegg2018-01-094-14/+141
| | | | | | | | | | | | | | This adds COMDAT support to the Wasm object-file format. Spec: https://github.com/WebAssembly/tool-conventions/pull/31 Corresponding LLD change: https://bugs.llvm.org/show_bug.cgi?id=35533, and D40845 Patch by Nicholas Wilson Differential Revision: https://reviews.llvm.org/D40844 llvm-svn: 322135
* [DWARFv5] MC support for MD5 file checksumsPaul Robinson2018-01-0910-34/+92
| | | | | | | Extend .file directive syntax to allow specifying an MD5 checksum for the source file. Emit the checksums in DWARF v5 line tables. llvm-svn: 322134
* Tidy some grammar in some commentsEric Christopher2018-01-092-4/+4
| | | | llvm-svn: 322133
* Use a MCExpr for the size of MCFillFragment.Rafael Espindola2018-01-093-16/+18
| | | | | | | This allows the size to be found during ralaxation. This fixes pr35858. llvm-svn: 322131
* [WebAssembly] MC: Use zero for provisional value of undefined symbolsSam Clegg2018-01-091-2/+2
| | | | | | | | | | This is more in line with what happens in the final executable when symbols are undefined (i.e. weak references). Differential Revision: https://reviews.llvm.org/D41840 llvm-svn: 322130
* [IPSCCP] Remove calls without side effectsChris Bieneman2018-01-092-1/+6
| | | | | | | | | | | | | | | Summary: When performing constant propagation for call instructions we have historically replaced all uses of the return from a call, but not removed the call itself. This is required for correctness if the calls have side effects, however the compiler should be able to safely remove calls that don't have side effects. This allows the compiler to completely fold away calls to functions that have no side effects if the inputs are constant and the output can be determined at compile time. Reviewers: davide, sanjoy, bruno, dberlin Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D38856 llvm-svn: 322125
* [PowerPC] Manually schedule the prologue and epilogueStefan Pintilie2018-01-091-6/+62
| | | | | | | | | | | | | | | | | | | | | This patch makes the following changes to the schedule of instructions in the prologue and epilogue. The stack pointer update is moved down in the prologue so that the callee saves do not have to wait for the update to happen. Saving the lr is moved down in the prologue to hide the latency of the mflr. The stack pointer is moved up in the epilogue so that restoring of the lr can happen sooner. The mtlr is moved up in the epilogue so that it is away form the blr at the end of the epilogue. The latency of the mtlr can now be hidden by the loads of the callee saved registers. This commit is almost identical to this one: r322036 except that two warnings that broke build bots have been fixed. The revision number is D41737 as before. llvm-svn: 322124
* Don't create MCFillFragment directly.Rafael Espindola2018-01-092-32/+15
| | | | | | Instead use higher level APIs that take care of most bookkeeping. llvm-svn: 322123
* [WebAssembly] Explicitly specify function/global index space in YAMLSam Clegg2018-01-092-2/+6
| | | | | | | | | | | These indexes are useful because they are not always zero based and functions and globals are referenced elsewhere by their index. This matches what we already do for the type index space. Differential Revision: https://reviews.llvm.org/D41877 llvm-svn: 322121
* [SelectionDAG] Fixed f16-from-vector promotion problemTim Renouf2018-01-091-1/+7
| | | | | | | | | | | | | | | | | | Summary: In the case of an fp_extend of v1f16 to v1f32 where the v1f16 is the result of a bitcast from i16, avoid creating an illegal fp16_to_fp where the input is not a vector and the result is a v1f32. V2: The fix is now to avoid vector scalarization creating a v1->scalar bitcast. Reviewers: srhines, t.p.northover Subscribers: nhaehnle, llvm-commits, dstuttard, t-tye, yaxunl, wdng, kzhuravl, arsenm Differential Revision: https://reviews.llvm.org/D41126 llvm-svn: 322120
* [AMDGPU] Fixed incorrect uniform branch conditionTim Renouf2018-01-091-0/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | Summary: I had a case where multiple nested uniform ifs resulted in code that did v_cmp comparisons, combining the results with s_and_b64, s_or_b64 and s_xor_b64 and using the resulting mask in s_cbranch_vccnz, without first ensuring that bits for inactive lanes were clear. There was already code for inserting an "s_and_b64 vcc, exec, vcc" to clear bits for inactive lanes in the case that the branch is instruction selected as s_cbranch_scc1 and is then changed to s_cbranch_vccnz in SIFixSGPRCopies. I have added the same code into SILowerControlFlow for the case that the branch is instruction selected as s_cbranch_vccnz. This de-optimizes the code in some cases where the s_and is not needed, because vcc is the result of a v_cmp, or multiple v_cmp instructions combined by s_and/s_or. We should add a pass to re-optimize those cases. Reviewers: arsenm, kzhuravl Subscribers: wdng, yaxunl, t-tye, llvm-commits, dstuttard, timcorringham, nhaehnle Differential Revision: https://reviews.llvm.org/D41292 llvm-svn: 322119
* NewGVN: Fix PR/33367, which was causing us to delete non-copy intrinsics ↵Daniel Berlin2018-01-091-2/+5
| | | | | | accidentally in some rare cases llvm-svn: 322115
* Inline a emitFill variant that is only used once. NFC.Rafael Espindola2018-01-093-21/+7
| | | | llvm-svn: 322111
* Add a pass to generate synthetic function entry counts.Easwaran Raman2018-01-0910-7/+277
| | | | | | | | | | | | | | | | | | | | | | | | Summary: This pass synthesizes function entry counts by traversing the callgraph and using the relative block frequencies of the callsites. The intended use of these counts is in inlining to determine hot/cold callsites in the absence of profile information. The pass is split into two files with the code that propagates the counts in a callgraph in a Utils file. I plan to add support for propagation in the thinlto link phase and the propagation code will be shared and hence this split. I did not add support to the old PM since hot callsite determination in inlining is not possible in old PM (although we could use hot callee heuristic with synthetic counts in the old PM it is not worth the effort tuning it) Reviewers: davidxl, silvas Subscribers: mgorny, mehdi_amini, llvm-commits Differential Revision: https://reviews.llvm.org/D41604 llvm-svn: 322110
* [Option] For typo '-foo', suggest '--foo'Brian Gesiak2018-01-091-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | Summary: https://reviews.llvm.org/rL321877 introduced the `OptTable::findNearest` method, to find the closest edit distance option for a given string. However, the implementation contained a bug: for a typo `-foo` with an edit distance of 1 away from a valid option `--foo`, `findNearest` would suggest a nearby option of `foo`. That is, the result would not include the `--` prefix, and so was not a valid option. Fix the bug by ensuring that the prefix string is initialized to one of the valid prefixes for the option. Test Plan: `check-llvm-unit` Reviewers: v.g.vassilev, teemperor, ruiu, jroelofs, yamaguchi Reviewed By: jroelofs Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D41873 llvm-svn: 322109
* Make one of the emitFill methods non virtual. NFC.Rafael Espindola2018-01-093-21/+8
| | | | | | This is just preparatory work to fix PR35858. llvm-svn: 322108
* [COST]Fix PR35865: Fix cost model evaluation for shuffle on X86.Alexey Bataev2018-01-091-1/+2
| | | | | | | | | | | | | | Summary: If the vector type is transformed to non-vector single type, the compile may crash trying to get vector information about non-vector type. Reviewers: RKSimon, spatel, mkuper, hfinkel Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D41862 llvm-svn: 322106
* [WebAssembly] Update libcall signature listsDerek Schuff2018-01-091-0/+60
| | | | | | New signatures added in r322087. A fix for this tight coupling is forthcoming. llvm-svn: 322105
* [InstCombine] weaken assertions for icmp folds (PR35846)Sanjay Patel2018-01-091-10/+4
| | | | | | | | | Because of potential UB (known bits conflicts with an llvm.assume), we have to check rather than assert here because InstSimplify doesn't kill the compare: https://bugs.llvm.org/show_bug.cgi?id=35846 llvm-svn: 322104
* Fix crash when linking metadata with ODR type uniquingTeresa Johnson2018-01-091-1/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: With DebugTypeODRUniquing enabled, during IR linking debug metadata in the destination module may be reached from the source module. This means that ConstantAsMetadata nodes (e.g. on DITemplateValueParameter) may contain a value the destination module. When trying to map such metadata nodes, we will attempt to map a GV already in the dest module. linkGlobalValueProto will end up with a source GV that is the same as the dest GV as well as the new GV. Trying to access the TypeMap for the source GV type, which is actually a dest GV type, hits an assertion since it appears that we have mapped into the source module (because the type is the value not a key into the map). Detect that we don't need to access the TypeMap in this case, since there is no need to create a bitcast from the new GV to the source GV type as they GV are the same. Fixes PR35722. Reviewers: mehdi_amini, pcc Subscribers: probinson, llvm-commits, eraman Differential Revision: https://reviews.llvm.org/D41624 llvm-svn: 322103
* [X86] Add a DAG combine to combine (sext (setcc)) with VLXCraig Topper2018-01-091-0/+42
| | | | | | | | | | | | Normally target independent DAG combine would do this combine based on getSetCCResultType, but with VLX getSetCCResultType returns a vXi1 type preventing the DAG combining from kicking in. But doing this combine can allow us to remove the explicit sign extend that would otherwise be emitted. This patch adds a target specific DAG combine to combine the sext+setcc when the result type is the same size as the input to the setcc. I've restricted this to FP compares and things that can be represented with PCMPEQ and PCMPGT since we don't have full integer compare support on the older ISAs. Differential Revision: https://reviews.llvm.org/D41850 llvm-svn: 322101
* Test commitMatthew Voss2018-01-091-1/+1
| | | | | | This is a commit to test commit access. llvm-svn: 322099
* [TargetParser] Add missing armv8l ARMv8 variant.Florian Hahn2018-01-091-1/+1
| | | | | | | | | | | | | | | | | | This change adds the missing armv8l variant as an alias of armv8 architecture. The issue was observed with several regressions in validation on armv8l hardware (for instance ExecutionEngine/frem.ll failed due to lack of neon fpu). Tested with regression testsuite passed without regression on ARM and x86_64. Patch by Yvan Roux. Reviewers: rengolin, rogfer01, olista01, fhahn Reviewed By: fhahn Differential Revision: https://reviews.llvm.org/D41859 llvm-svn: 322098
* [CodeGen] Don't print "pred:" and "opt:" in -debug outputFrancis Visoiu Mistrih2018-01-094-18/+12
| | | | | | | | | | In -debug output we print "pred:" whenever a MachineOperand is a predicate operand in the instruction descriptor, and "opt:" whenever a MachineOperand is an optional def in the instruction descriptor. Differential Revision: https://reviews.llvm.org/D41870 llvm-svn: 322096
* [Support] Use realpath(3) instead of trying to open a file.Davide Italiano2018-01-091-6/+6
| | | | | | | | | If we don't have read permissions on the directory the call would fail. <rdar://problem/35871293> llvm-svn: 322095
* [Support] Add WritableMemoryBuffer::getNewMemBufferPavel Labath2018-01-092-8/+13
| | | | | | | | | | | | | | | | | | Summary: The idea is that it would replace (non-Writable)MemoryBuffer::getNewMemBuffer, which is quite useless unless you const_cast its contents to write to it (which all (both) callers of this function were doing). This patch also fixes one of the usages in COFFWriter. After fixing the other usage in clang, I plan to delete the old function. Reviewers: dblaikie, Bigcheese Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D41540 llvm-svn: 322094
* Recommit r322073: [AArch64][SVE] Asm: Add predicated ADD/SUB instructionsSander de Smalen2018-01-094-4/+38
| | | | | | | | | Fixed issue that was found on sanitizer-x86_64-linux-fast. I changed the result type of 'Parser.getTok().getString().lower()' in AArch64AsmParser::tryParseSVEPredicateVector() from 'StringRef' to 'auto', since StringRef::lower() returns a std::string. llvm-svn: 322092
* [CodeGen] Print frame-setup/destroy flags in -debug output like we do in MIRFrancis Visoiu Mistrih2018-01-091-15/+5
| | | | | | | | | | | | | | | Currently the MachineInstr::print function prints the frame-setup/frame-destroy differently than it does in MIR. Instead of: %x21 = LDR %sp, -16; flags: FrameDestroy print: %x21 = frame-destroy LDR %sp, -16 llvm-svn: 322088
* [SelectionDAG] lower math intrinsics to finite version of libcalls when ↵Sanjay Patel2018-01-093-20/+65
| | | | | | | | | | | | | | | | | | | | | | possible (PR35672) Ingredients in this patch: 1. Add HANDLE_LIBCALL defs for finite mathlib functions that correspond to LLVM intrinsics. 2. Plumbing to send TargetLibraryInfo down to SelectionDAGLegalize. 3. Relaxed math and library checking in SelectionDAGLegalize::ConvertNodeToLibcall() to choose finite libcalls. There was a bug about determining the availability of the finite calls that should be fixed with: rL322010 Not in this patch: This doesn't resolve the question/bug of clang creating the intrinsic IR in the first place. There's likely follow-up work needed to support the long double variants better. There's room for improvement to reduce the code duplication. Create finite calls that don't originate from a corresponding intrinsic or DAG node? Differential Revision: https://reviews.llvm.org/D41338 llvm-svn: 322087
* [CodeGen] Don't print register classes in -debug outputFrancis Visoiu Mistrih2018-01-091-37/+0
| | | | | | | | | | Since register classes and banks are already printed with the register definition, don't print it at the end of every instruction anymore. This follows MIR in this regard and is another step to the unification of the two formats. llvm-svn: 322086
* [DAG] Elide overlapping storesNirav Dave2018-01-091-21/+20
| | | | | | | | | | | | | | | | Relanding after fixing handling of pre-indexed memory operations in BaseIndexOffset analysis (r322003). Extend overlapping store elision to handle overwrites of stores by larger stores. Reviewers: craig.topper, rnk, t.p.northover Subscribers: javed.absar, hiraditya, llvm-commits Differential Revision: https://reviews.llvm.org/D40969 llvm-svn: 322085
* [EarlyCSE] Salvage debug info during DCEPetar Jovanovic2018-01-091-0/+1
| | | | | | | | | | | EarlyCSE did not try to salvage debug info during erasing of instructions. This change fixes it. Patch by Djordje Todorovic. Differential Revision: https://reviews.llvm.org/D41496 llvm-svn: 322083
* [InstCombine] Check for out of range ashr values using APInt before calling ↵Simon Pilgrim2018-01-091-3/+5
| | | | | | | | getZExtValue Reduced from oss-fuzz #5032 test case llvm-svn: 322078
* Reverted r322073 because of AddressSanitizer failure onSander de Smalen2018-01-093-37/+3
| | | | | | sanitizer-x86_64-linux-fast builder. llvm-svn: 322077
* [AArch64][SVE] Asm: Add predicated ADD/SUB instructionsSander de Smalen2018-01-093-3/+37
| | | | | | | | | | | | | | | | | Summary: Add the predicated ADD/SUB instructions and corresponding tests. Patch [3/3] in a series to add predicated ADD/SUB instructions for SVE. Reviewers: rengolin, mcrosier, evandro, fhahn, echristo Reviewed By: fhahn Subscribers: aemerson, javed.absar, tschuett, llvm-commits, kristof.beyls Differential Revision: https://reviews.llvm.org/D41443 llvm-svn: 322073
* [MIR] Add support for the frame-destroy MachineInstr flagFrancis Visoiu Mistrih2018-01-094-0/+8
| | | | | | | | | We are printing / parsing the `frame-setup` MachineInstr flag but not the `frame-destroy` one. Differential Revision: https://reviews.llvm.org/D41509 llvm-svn: 322071
* [AArch64][SVE] Asm: Add parsing of merging/zeroing suffix for SVE predicate ↵Sander de Smalen2018-01-092-0/+32
| | | | | | | | | | | | | | | | | | | vector operands Summary: Parsing of the '/m' (merging) or '/z' (zeroing) suffix of a predicate operand. Patch [2/3] in a series to add predicated ADD/SUB instructions for SVE. Reviewers: rengolin, mcrosier, evandro, fhahn, echristo, MatzeB, t.p.northover Reviewed By: fhahn Subscribers: t.p.northover, MatzeB, aemerson, javed.absar, tschuett, llvm-commits, kristof.beyls Differential Revision: https://reviews.llvm.org/D41442 llvm-svn: 322070
* [Nios2] Arithmetic instructions for R1 and R2 ISA.Nikolai Bozhenov2018-01-095-11/+138
| | | | | | | | | | | | | | Summary: This commit enables some of the arithmetic instructions for Nios2 ISA (for both R1 and R2 revisions), implements facilities required to emit those instructions and provides LIT tests for added instructions. Reviewed By: hfinkel Differential Revision: https://reviews.llvm.org/D41236 Author: belickim <mateusz.belicki@intel.com> llvm-svn: 322069
* Instrument Control Flow For Indirect Branch TrackingOren Ben Simhon2018-01-095-1/+176
| | | | | | | | | | | | | CET (Control-Flow Enforcement Technology) introduces a new mechanism called IBT (Indirect Branch Tracking). According to IBT, each Indirect branch should land on dedicated ENDBR instruction (End Branch). The new pass adds ENDBR instructions for every indirect jmp/call (including jumps using jump tables / switches). For more information, please see the following: https://software.intel.com/sites/default/files/managed/4d/2a/control-flow-enforcement-technology-preview.pdf Differential Revision: https://reviews.llvm.org/D40482 Change-Id: Icb754489faf483a95248f96982a4e8b1009eb709 llvm-svn: 322062
* [X86] Allow more cmpps/pd immediate encodings to be commuted during isel.Craig Topper2018-01-091-2/+2
| | | | | | The code that checks the immediate wasn't masking to the lower 3-bits like the code in X86InstrInfo.cpp that's used by the peephole pass does. llvm-svn: 322060
* [SCEV] Do not cache S -> V if S is not equivalent of VSerguei Katkov2018-01-091-1/+19
| | | | | | | | | | | | | | | | SCEV tracks the correspondence of created SCEV to original instruction. However during creation of SCEV it is possible that nuw/nsw/exact flags are lost. As a result during expansion of the SCEV the instruction with nuw/nsw/exact will be used where it was expected and we produce poison incorreclty. Reviewers: sanjoy, mkazantsev, sebpop, jbhateja Reviewed By: sanjoy Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D41578 llvm-svn: 322058
* [CGP] Fix Complex addressing mode for offsetSerguei Katkov2018-01-091-1/+6
| | | | | | | | | | | | | | If the offset is differ in two addressing mode we can continue only if ScaleReg is not set due to we will use it as merge of different offsets. It should fix PR35799 and PR35805. Reviewers: john.brawn, reames Reviewed By: reames Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D41227 llvm-svn: 322056
* [PowerPC] Can not assume an intrinsic argument is a simple type.Sean Fertile2018-01-091-6/+7
| | | | | | | | | | | | | The CTRLoop pass performs checks on the argument of certain libcalls/intrinsics, and assumes the arguments must be of a simple type. This isn't always the case though. For example if we unroll and vectorize a loop we may end up with vectors larger then the largest legal type, along with intrinsics that operate on those wider types. This happened in the ffmpeg build, where we unrolled a loop and ended up with a sqrt intrinsic that operated on V16f64, triggering an assertion. Differential Revision: https://reviews.llvm.org/D41758 llvm-svn: 322055
* Remove unused function HvxSelector::zerous.Eric Christopher2018-01-091-20/+0
| | | | llvm-svn: 322053
* Revert "[PowerPC] Manually schedule the prologue and epilogue"Stefan Pintilie2018-01-091-65/+6
| | | | | | | | [PowerPC] This reverts commit r322036. Failing build bots. Revert the commit now. llvm-svn: 322051
* [X86] Remove llvm.x86.avx512.cvt*2mask.* intrinsics and autoupgrade to (icmp ↵Craig Topper2018-01-093-29/+19
| | | | | | | | slt X, 0) I had to drop fast-isel-abort from a test because we can't fast isel some of the mask stuff. When we used intrinsics we implicitly fell back to SelectionDAG for the intrinsic call without triggering the abort error. But with native IR that doesn't happen the same way. llvm-svn: 322050
* [X86] Remove unnecessary isel pattern that is a combination of two other ↵Craig Topper2018-01-091-2/+0
| | | | | | | | | | | | | | | patterns. The pattern was this def : Pat<(i32 (zext (i8 (bitconvert (v8i1 VK8:$src))))), (MOVZX32rr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS VK8:$src, GR32)), sub_8bit))>, Requires<[NoDQI]>; but if you just let (i32 (zext X)) match byte itself you'll get MOVZX32rr8. And if you let (i8 (bitconvert (v8i1 VK8:$src))) match by itself you'll get (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS VK8:$src, GR32)), sub_8bit). So we can just let isel do the two patterns naturally. llvm-svn: 322049
* [MachineOutliner] AArch64: Handle instrs that use SP and will never need fixupsJessica Paquette2018-01-095-18/+97
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit does two things. Firstly, it adds a collection of flags which can be passed along to the target to encode information about the MBB that an instruction lives in to the outliner. Second, it adds some of those flags to the AArch64 outliner in order to add more stack instructions to the list of legal instructions that are handled by the outliner. The two flags added check if - There are calls in the MachineBasicBlock containing the instruction - The link register is available in the entire block If the link register is available and there are no calls, then a stack instruction can always be outlined without fixups, regardless of what it is, since in this case, the outliner will never modify the stack to create a call or outlined frame. The motivation for doing this was checking which instructions are most often missed by the outliner. Instructions like, say %sp<def> = ADDXri %sp, 32, 0; flags: FrameDestroy are very common, but cannot be outlined in the case that the outliner might modify the stack. This commit allows us to outline instructions like this. llvm-svn: 322048
* [PowerPC] Manually schedule the prologue and epilogueStefan Pintilie2018-01-081-6/+65
| | | | | | | | | | | | | | | | | | This patch makes the following changes to the schedule of instructions in the prologue and epilogue. The stack pointer update is moved down in the prologue so that the callee saves do not have to wait for the update to happen. Saving the lr is moved down in the prologue to hide the latency of the mflr. The stack pointer is moved up in the epilogue so that restoring of the lr can happen sooner. The mtlr is moved up in the epilogue so that it is away form the blr at the end of the epilogue. The latency of the mtlr can now be hidden by the loads of the callee saved registers. Differential Revision: https://reviews.llvm.org/D41737 llvm-svn: 322036
* AlwaysInliner: Alow setting InsertLifetime in the new-style passJustin Bogner2018-01-081-1/+2
| | | | llvm-svn: 322033
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