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* [X86][AVX] Added support for lowering to VBROADCASTF128/VBROADCASTI128 ↵Simon Pilgrim2016-07-224-12/+72
| | | | | | | | | | | | | | | | (reapplied) As reported on PR26235, we don't currently make use of the VBROADCASTF128/VBROADCASTI128 instructions (or the AVX512 equivalents) to load+splat a 128-bit vector to both lanes of a 256-bit vector. This patch enables lowering from subvector insertion/concatenation patterns and auto-upgrades the llvm.x86.avx.vbroadcastf128.pd.256 / llvm.x86.avx.vbroadcastf128.ps.256 intrinsics to match. We could possibly investigate using VBROADCASTF128/VBROADCASTI128 to load repeated constants as well (similar to how we already do for scalar broadcasts). Reapplied with fix for PR28657 - removed intrinsic definitions (clang companion patch to be be submitted shortly). Differential Revision: https://reviews.llvm.org/D22460 llvm-svn: 276416
* [FastISel] Ignore @llvm.assume.Ahmed Bougacha2016-07-221-0/+2
| | | | llvm-svn: 276410
* Revert "[X86][AVX] Added support for lowering to VBROADCASTF128/VBROADCASTI128"Benjamin Kramer2016-07-224-72/+12
| | | | | | | | It caused PR28657. This reverts commit r276281. llvm-svn: 276405
* [llvm-cov] - Improve llvm-cov error messageYing Yi2016-07-221-1/+2
| | | | | | | | | | | | | | | | | | | Summary: When giving the following command: % llvm-cov report -instr-profile=default.profraw llvm-cov will give the following error message: >llvm-cov report: Not enough positional command line arguments specified! >Must specify at least 1 positional arguments: See: orbis-llvm-cov report -help This patch changes the error message from '1 positional arguments' to '1 positional argument'. Differential Revision: https://reviews.llvm.org/D22621 llvm-svn: 276404
* This refactoring of ARM machine block size computation creates two utilitySjoerd Meijer2016-07-225-123/+193
| | | | | | | | | functions so that the size computation is available not only in ConstantIslands but in other passes as well. Differential Revision: https://reviews.llvm.org/D22640 llvm-svn: 276399
* [mips][microMIPS] Implement SLT, SLTI, SLTIU, SLTU microMIPS32r6 instructionsHrvoje Varga2016-07-226-68/+102
| | | | | | Differential Revision: https://reviews.llvm.org/D19906 llvm-svn: 276397
* [AVX512] Add ExeDomain to vector extend and truncate instructions.Craig Topper2016-07-221-2/+5
| | | | llvm-svn: 276394
* [AVX512] Add initial support for the Execution Domain fixing pass to change ↵Craig Topper2016-07-222-2/+57
| | | | | | some EVEX instructions. llvm-svn: 276393
* [AVX512] Fix the ExeDomain for some packed fp instructions.Craig Topper2016-07-221-5/+19
| | | | llvm-svn: 276392
* [AVX512] Add load folding for some AVX512VL logic and arithmetic instructions.Craig Topper2016-07-221-0/+36
| | | | llvm-svn: 276391
* [AVX512] Update X86InstrInfo::foldMemoryOperandCustom to handle the EVEX ↵Craig Topper2016-07-221-4/+8
| | | | | | encoded instructions too. llvm-svn: 276390
* Don't remove side effecting instructions due to ConstantFoldInstructionDavid Majnemer2016-07-225-9/+20
| | | | | | | | | Just because we can constant fold the result of an instruction does not imply that we can delete the instruction. It may have side effects. This fixes PR28655. llvm-svn: 276389
* Sync up InstrProfData.inc with compiler-rt with fixes to referencesXinliang David Li2016-07-221-3/+3
| | | | llvm-svn: 276388
* Avoid dsymutil calls to getFileNameByIndex.Pete Cooper2016-07-221-6/+11
| | | | | | | | | | | | This change adds a hasFileAtIndex method. getChildDeclContext can first call this method, and if it returns true it knows it can then lookup the resolved path cache for the given file index. If we hit that cache then we don't even have to call getFileNameByIndex. Running dsymutil against the swift executable built from github gives a 20% performance improvement without any change in the binary. Differential Revision: https://reviews.llvm.org/D22655 Reviewed by friss. llvm-svn: 276380
* Fix detection of stack-use-after scope for char arrays.Vitaly Buka2016-07-221-0/+4
| | | | | | | | | | | | | | Summary: Clang inserts GetElementPtrInst so findAllocaForValue was not able to find allocas. PR27453 Reviewers: kcc, eugenis Differential Revision: https://reviews.llvm.org/D22657 llvm-svn: 276374
* [IRCE] Add an option to skip profitability checksSanjoy Das2016-07-221-2/+7
| | | | | | | | If `-irce-skip-profitability-checks` is passed in, IRCE will kick in in all cases where it is legal for it to kick in. This flag is intended to help diagnose and analyse performance issues. llvm-svn: 276372
* GVN-hoist: move check before mutating the IRSebastian Pop2016-07-221-6/+8
| | | | llvm-svn: 276368
* [AArch64] Cleanup sign extend in genAlternativeCodeSequenceDavid Majnemer2016-07-211-3/+3
| | | | | | | | Use the machinery in MathExtras instead of rolling it by hand. This fixes PR28624. llvm-svn: 276366
* GVN-hoist: add missing check for all GEP operands availableSebastian Pop2016-07-211-0/+3
| | | | llvm-svn: 276364
* [Sparc]: Fix bug in LowerSTORE due to r275592Douglas Katzman2016-07-211-1/+1
| | | | llvm-svn: 276362
* [InstCombine] break up foldICmpEqualityWithConstant(); NFCISanjay Patel2016-07-212-148/+161
| | | | | | | Almost all of these folds require changes to allow vector types. Splitting up the logic should make that easier to do incrementally. llvm-svn: 276360
* GVH-hoist: only clone GEPs (PR28606)Sebastian Pop2016-07-211-14/+7
| | | | | | | | | Do not clone stored values unless they are GEPs that are special cased to avoid hoisting them without hoisting their associated ld/st. Differential revision: https://reviews.llvm.org/D22652 llvm-svn: 276358
* [Profile] deprecate __llvm_profile_override_default_filenameXinliang David Li2016-07-211-16/+16
| | | | | | | | This eliminates unncessary calls and init functions. Differential Revision: http://reviews.llvm.org/D22613 llvm-svn: 276354
* [PM] Port NaryReassociate to the new PMWei Mi2016-07-214-112/+78
| | | | | | Differential Revision: https://reviews.llvm.org/D22648 llvm-svn: 276349
* [MIRTesting] Abort when failing to parse a function.Quentin Colombet2016-07-211-2/+4
| | | | | | | | | | When we failed to parse a function in the mir parser, we should abort the whole compilation instead of continuing in a weird state. Indeed, this was creating strange machine function passes failures that were hard to understand, until we notice that the function actually did not get parsed correctly! llvm-svn: 276348
* [X86] Do not use AND8ri8 in AVX512 patternMichael Kuperstein2016-07-211-1/+1
| | | | | | | This variant is (as documented in the TD) for disassembler use only, and should not be used in patterns - it is longer, and is broken on 64-bit. llvm-svn: 276347
* [InstSimplify] don't crash handling a pointer or aggregate typeSanjay Patel2016-07-211-0/+3
| | | | llvm-svn: 276345
* [AArch64][Inline-Asm] Return the 32-bit floating point register classAkira Hatanaka2016-07-211-1/+1
| | | | | | | | | | | | | | | when constraint "w" is used on a 32-bit operand. This enables compiling the following code, which used to error out in the backend: void foo1(int a) { asm volatile ("sqxtn h0, %s0\n" : : "w"(a):); } Fixes PR28633. llvm-svn: 276344
* [InstSimplify] recognize trunc + icmp sgt/slt variants of select ↵Sanjay Patel2016-07-211-7/+33
| | | | | | | | | | | | | | | | | | simplifications (PR28466) rL245171 exposed a hole in InstSimplify that manifested in a strange way in PR28466: https://llvm.org/bugs/show_bug.cgi?id=28466 It's possible to use trunc + icmp sgt/slt in place of an and + icmp eq/ne, so we need to recognize that pattern to eliminate selects that are choosing between some value and some bitmasked version of that value. Note that there is significant room for improvement (refactoring) and enhancement (more patterns, possibly in InstCombine rather than here). Differential Revision: https://reviews.llvm.org/D22537 llvm-svn: 276341
* [OptDiag,LDist] Convert remaining opt remarks to use the new APIAdam Nemet2016-07-211-6/+5
| | | | llvm-svn: 276340
* [LV] Move vector int induction update to end of latchMatthew Simpson2016-07-211-3/+12
| | | | | | | | | | | This patch moves the update instruction for vectorized integer induction phi nodes to the end of the latch block. This ensures consistent placement of all induction updates across all the kinds of int inductions we create (scalar, splat vector, or vector phi). Differential Revision: https://reviews.llvm.org/D22416 llvm-svn: 276339
* Fix the clang-cl self-host with VS 2013 headersReid Kleckner2016-07-211-2/+1
| | | | | | | | std::numeric_limits<int64_t>::max() is not constexpr in VC 2013 headers, and Clang complains that it isn't. MSVC 2013 itself is emitting a dynamic initializer for this thing. Instead, use an enum. llvm-svn: 276334
* Normalize file docs. NFC.George Burgess IV2016-07-211-1/+1
| | | | | | | | Having the added `\brief` made doxygen interpret it as the summary for the `llvm` namespace (visible at: http://llvm.org/doxygen/namespaces.html). llvm-svn: 276331
* [PGO] Make needsComdatForCounter() available (NFC)Rong Xu2016-07-212-27/+26
| | | | | | | | | | Move needsComdatForCounter() to lib/ProfileData/InstrProf.cpp from lib/Transforms/Instrumentation/InstrProfiling.cpp to make is available for other files. Differential Revision: https://reviews.llvm.org/D22643 llvm-svn: 276330
* Revert "Invariant start/end intrinsics overloaded for address space"Anna Thomas2016-07-211-27/+1
| | | | | | This reverts commit r276316. llvm-svn: 276320
* [IndVars] Reflow oddly formatted condition; NFCSanjoy Das2016-07-211-2/+2
| | | | llvm-svn: 276319
* Invariant start/end intrinsics overloaded for address spaceAnna Thomas2016-07-211-1/+27
| | | | | | | | | | | | | | | | | | | | | Summary: The llvm.invariant.start and llvm.invariant.end intrinsics currently support specifying invariant memory objects only in the default address space. With this change, these intrinsics are overloaded for any adddress space for memory objects and we can use these llvm invariant intrinsics in non-default address spaces. Example: llvm.invariant.start.p1i8(i64 4, i8 addrspace(1)* %ptr) This overloaded intrinsic is needed for representing final or invariant memory in managed languages. Reviewers: tstellarAMD, reames, apilipenko Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D22519 llvm-svn: 276316
* make InstCombine compare helper functions private; NFCSanjay Patel2016-07-212-68/+69
| | | | | | Also, rename some of them for consistency and to follow current conventions. llvm-svn: 276312
* Avoid a string copy, NFCVedant Kumar2016-07-211-1/+1
| | | | llvm-svn: 276310
* [IRTranslator] Add G_SUB opcode.Quentin Colombet2016-07-211-0/+2
| | | | | | This commit adds a generic SUB opcode to global-isel. llvm-svn: 276308
* [IRTranslator] Add comments to explain the ordering of the switch. NFC.Quentin Colombet2016-07-211-0/+3
| | | | | | Group arithmetic operations, bitwise operations, and branch operations. llvm-svn: 276305
* [InstCombine] break up visitICmpInstWithInstAndIntCst(); NFCISanjay Patel2016-07-212-155/+166
| | | | | | | Making smaller pieces out of some of these ~1000 line functions should make it easier to incrementally upgrade them to handle vector types. llvm-svn: 276304
* [AMDGPU] Emit read-only data to .rodata for hsaKonstantin Zhuravlyov2016-07-211-1/+2
| | | | | | Differential Revision: https://reviews.llvm.org/D22538 llvm-svn: 276298
* [IRTranslator] Add G_AND opcode.Quentin Colombet2016-07-211-0/+2
| | | | | | This commit adds a generic AND opcode to global-isel. llvm-svn: 276297
* AMDGPU/SI: Add support for R_AMDGPU_ABS32Konstantin Zhuravlyov2016-07-211-0/+1
| | | | | | Differential Revision: https://reviews.llvm.org/D21646 llvm-svn: 276294
* [AArch64] Load/store opt: Don't count transient instructions towards search ↵Geoff Berry2016-07-211-15/+14
| | | | | | | | | | | | | | | | | | limits. Summary: This change also changes findMatchingInsn and findMatchingUpdateInsnForward to take DBG_VALUE opcodes into account when tracking register defs and uses, which could potentially inhibit these optimizations in the presence of debug information. Reviewers: mcrosier Subscribers: aemerson, rengolin, mcrosier, llvm-commits Differential Revision: https://reviews.llvm.org/D22582 llvm-svn: 276293
* [X86][SSE] Allow folding of store/zext with PEXTRW of 0'th elementSimon Pilgrim2016-07-211-6/+15
| | | | | | | | | | | | | | Under normal circumstances we prefer the higher performance MOVD to extract the 0'th element of a v8i16 vector instead of PEXTRW. But as detailed on PR27265, this prevents the SSE41 implementation of PEXTRW from folding the store of the 0'th element. Additionally it prevents us from making use of the fact that the (SSE2) reg-reg version of PEXTRW implicitly zero-extends the i16 element to the i32/i64 destination register. This patch only preferentially lowers to MOVD if we will not be zero-extending the extracted i16, nor prevent a store from being folded (on SSSE41). Fix for PR27265. Differential Revision: https://reviews.llvm.org/D22509 llvm-svn: 276289
* [X86][SSE] Pull out duplicate EXTRW lowering code. NFCI.Simon Pilgrim2016-07-211-26/+16
| | | | | | As requested on D22509, I've pulled out the v8i16 extraction lowering as the SSE41 and pre-SSE41 implementations are effectively the same. llvm-svn: 276285
* [X86][AVX] Added support for lowering to VBROADCASTF128/VBROADCASTI128Simon Pilgrim2016-07-214-12/+72
| | | | | | | | | | | | As reported on PR26235, we don't currently make use of the VBROADCASTF128/VBROADCASTI128 instructions (or the AVX512 equivalents) to load+splat a 128-bit vector to both lanes of a 256-bit vector. This patch enables lowering from subvector insertion/concatenation patterns and auto-upgrades the llvm.x86.avx.vbroadcastf128.pd.256 / llvm.x86.avx.vbroadcastf128.ps.256 intrinsics to match. We could possibly investigate using VBROADCASTF128/VBROADCASTI128 to load repeated constants as well (similar to how we already do for scalar broadcasts). Differential Revision: https://reviews.llvm.org/D22460 llvm-svn: 276281
* [DemandedBits] Reduce number of duplicated DenseMap lookups.Benjamin Kramer2016-07-211-5/+4
| | | | | | No functionality change intended. llvm-svn: 276278
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