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* Fix PR11985Michael Liao2012-09-1211-30/+54
| | | | | | | | | | | - BlockAddress has no support of BA + offset form and there is no way to propagate that offset into machine operand; - Add BA + offset support and a new interface 'getTargetBlockAddress' to simplify target block address forming; - All targets are modified to use new interface and X86 backend is enhanced to support BA + offset addressing. llvm-svn: 163743
* Detect overflow in the path count computation. rdar://12277446.Dan Gohman2012-09-121-0/+13
| | | | llvm-svn: 163739
* Remove an overly-aggressive assertion. The code following this assertion ↵Owen Anderson2012-09-121-2/+0
| | | | | | already knows how to handle the case where DstRC was NULL, so it's not actually protecting us from anything, and this pattern can come up when using unknown_class operands in the SelectionDAG. llvm-svn: 163736
* Delete dead code.Jakob Stoklund Olesen2012-09-121-36/+0
| | | | llvm-svn: 163735
* Revert "Add some support for dealing with an object pointer on arguments."Eric Christopher2012-09-124-40/+0
| | | | | | This should be done on the subprogram, not the variable itself. llvm-svn: 163734
* [ms-inline asm] Make the operand size directives case insensitive.Chad Rosier2012-09-121-8/+9
| | | | llvm-svn: 163729
* PGO: preserve branch-weight metadata when removing a case which jumpsManman Ren2012-09-121-0/+22
| | | | | | to the default target. llvm-svn: 163724
* Fix a couple of Doxygen comment issues pointed out by -Wdocumentation.Dmitri Gribenko2012-09-122-2/+2
| | | | llvm-svn: 163721
* Enable exceptions handling on PPC64 now that cr misaligned spillingRoman Divacky2012-09-121-2/+1
| | | | | | was fixed in r163713. llvm-svn: 163715
* This patch corrects logic in PPCFrameLowering for save and restore of ↵Roman Divacky2012-09-124-74/+277
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | nonvolatile condition register fields across calls under the SVR4 ABIs. * With the 64-bit ABI, the save location is at a fixed offset of 8 from the stack pointer. The frame pointer cannot be used to access this portion of the stack frame since the distance from the frame pointer may change with alloca calls. * With the 32-bit ABI, the save location is just below the general register save area, and is accessed via the frame pointer like the rest of the save areas. This is an optional slot, so it must only be created if any of CR2, CR3, and CR4 were modified. * For both ABIs, save/restore logic is generated only if one of the nonvolatile CR fields were modified. I also took this opportunity to clean up an extra FIXME in PPCFrameLowering.h. Save area offsets for 32-bit GPRs are meaningless for the 64-bit ABI, so I removed them for correctness and efficiency. Fixes PR13708 and partially also PR13623. It lets us enable exception handling on PPC64. Patch by William J. Schmidt! llvm-svn: 163713
* Add support for AMD Geode.Roman Divacky2012-09-122-0/+2
| | | | llvm-svn: 163710
* Fix constant folding through bitcasts by no longer relying on undefined ↵Kristof Beyls2012-09-121-2/+2
| | | | | | | | | | | | behaviour (converting NaN values between float and double). SelectionDAG::getConstantFP(double Val, EVT VT, bool isTarget); should not be used when Val is not a simple constant (as the comment in SelectionDAG.h indicates). This patch avoids using this function when folding an unknown constant through a bitcast, where it cannot be guaranteed that Val will be a simple constant. llvm-svn: 163703
* Add a flag to disable the code that looks for allocas which escaped the ↵Nadav Rotem2012-09-121-6/+18
| | | | | | lifetime regions. This is useful for debugging. No testcase because without this check we fail on assertions when finding escaped allocas. llvm-svn: 163702
* Add a function computeRegisterLiveness() to MachineBasicBlock. This uses ↵James Molloy2012-09-121-0/+74
| | | | | | | | analyzePhysReg() from r163694 to heuristically try and determine the liveness state of a physical register upon arrival at a particular instruction in a block. The search for liveness is clipped to a specific number of instructions around the target MachineInstr, in order to avoid degenerating into an O(N^2) algorithm. It tries to use various clues about how instructions around (both before and after) a given MachineInstr use that register, to determine its state at the MachineInstr. llvm-svn: 163695
* Add an analyzePhysReg() function to MachineOperandIteratorBase that analyses ↵James Molloy2012-09-122-4/+54
| | | | | | | | an instruction's use of a physical register, analogous to analyzeVirtReg. Rename RegInfo to VirtRegInfo so as not to be confused with the new PhysRegInfo. llvm-svn: 163694
* When calling print directly on a global (eg from the debugger) itDuncan Sands2012-09-121-3/+3
| | | | | | | | | was printing a newline that doesn't occur when printing other kinds of LLVM values. Move the printing of that newline elsewhere, making globals print the same as other values while leaving the output when printing an entire module unchanged. Patch by Saša Tomić. llvm-svn: 163693
* Enable stack-coloring, in hope that the recent fixes will enable correct ↵Nadav Rotem2012-09-121-1/+1
| | | | | | dragonegg self-hosting. llvm-svn: 163687
* Make findLastUseBefore handle reg-unit liveness.Lang Hames2012-09-121-8/+29
| | | | | | | | | findLastUseBefore was previous considering virtreg liveness only, leading to incorrect live intervals for reg units when instrs with physreg operands were moved up. llvm-svn: 163685
* Indentation fixes. No functional change.Craig Topper2012-09-121-8/+8
| | | | llvm-svn: 163682
* Release build: guard dump functions withManman Ren2012-09-1222-30/+30
| | | | | | | | "#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)" No functional change. Update r163344. llvm-svn: 163679
* Stack coloring: remove lifetime intervals which contain escaped allocas.Nadav Rotem2012-09-121-0/+47
| | | | | | | | | | The input program may contain intructions which are not inside lifetime markers. This can happen due to a bug in the compiler or due to a bug in user code (for example, returning a reference to a local variable). This commit adds checks that all of the instructions in the function and invalidates lifetime ranges which do not contain all of the instructions. llvm-svn: 163678
* Add some support for dealing with an object pointer on arguments.Eric Christopher2012-09-124-0/+40
| | | | | | Part of rdar://9797999 llvm-svn: 163667
* Rename the isMemory() function to isMem(). No functional change intended.Chad Rosier2012-09-111-22/+22
| | | | llvm-svn: 163654
* Release build: guard dump functions withManman Ren2012-09-1120-27/+27
| | | | | | | | "#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)" No functional change. Update r163339. llvm-svn: 163653
* StringSwitchify.Chad Rosier2012-09-111-8/+10
| | | | llvm-svn: 163649
* Simplify logic. No functional change intended.Chad Rosier2012-09-111-9/+8
| | | | llvm-svn: 163648
* [ms-inline asm] Split the parsing of IR asm strings into GCC and MS variants.Chad Rosier2012-09-111-67/+158
| | | | | | Add support in the EmitMSInlineAsmStr() function for handling integer consts. llvm-svn: 163645
* SimplifyCFG: preserve branch-weight metadata when creating a new switch fromManman Ren2012-09-111-81/+45
| | | | | | | | | | | | | a pair of switch/branch where both depend on the value of the same variable and the default case of the first switch/branch goes to the second switch/branch. Code clean up and fixed a few issues: 1> handling the case where some cases of the 2nd switch are invalidated 2> correctly calculate the weight for the 2nd switch when it is a conditional eq Testing case is modified from Alastair's original patch. llvm-svn: 163635
* Add TRI::getSubRegIndexLaneMask().Jakob Stoklund Olesen2012-09-111-2/+4
| | | | | | | | | | | | | | | | | Sub-register lane masks are bitmasks that can be used to determine if two sub-registers of a virtual register will overlap. For example, ARM's ssub0 and ssub1 sub-register indices don't overlap each other, but both overlap dsub0 and qsub0. The lane masks will be accurate on most targets, but on targets that use sub-register indexes in an irregular way, the masks may conservatively report that two sub-register indices overlap when the eventually allocated physregs don't. Irregular register banks also mean that the bits in a lane mask can't be mapped onto register units, but the concept is similar. llvm-svn: 163630
* Add MCRI::getNumSubRegIndices() and start checking SubRegIndex ranges.Jakob Stoklund Olesen2012-09-111-0/+3
| | | | | | | | Apparently, NumSubRegIndices was completely unused before. Adjust it by one to include the null subreg index, just like getNumRegs() includes the null register. llvm-svn: 163628
* Dragonegg selfhost exposed additional cases where alloca usage moved outside ↵Nadav Rotem2012-09-111-1/+1
| | | | | | of lifetime markers. Disabling the pass for now. llvm-svn: 163623
* Enable stack coloring.Nadav Rotem2012-09-111-1/+1
| | | | llvm-svn: 163617
* Stack Coloring: Dont crash on dbg values which use stack frames.Nadav Rotem2012-09-111-3/+5
| | | | llvm-svn: 163616
* Make a bunch of lowering helper functions static instead of member ↵Craig Topper2012-09-112-82/+56
| | | | | | functions. No functional change. llvm-svn: 163596
* Change unsigned to a uint16_t in static disassembler tables to reduce the ↵Craig Topper2012-09-112-2/+2
| | | | | | table size. llvm-svn: 163594
* llvm/lib/Transforms/Utils/CMakeLists.txt: Update.NAKAMURA Takumi2012-09-111-0/+1
| | | | llvm-svn: 163593
* Add a pass that renames everything with metasyntatic names. This works well ↵Alex Rosenberg2012-09-112-0/+133
| | | | | | after using bugpoint to reduce the confusion presented by the original names, which no longer mean what they used to. llvm-svn: 163592
* Teach DAG combiner to constant fold FABS of a BUILD_VECTOR of ConstantFPs. ↵Craig Topper2012-09-111-22/+47
| | | | | | Factor similar code out of FNEG DAG combiner. llvm-svn: 163587
* Add support for finding cacheflush on OpenBSD/mips64 platforms.Chandler Carruth2012-09-112-4/+8
| | | | | | Patch by Brad Smith! llvm-svn: 163584
* Reorganize MachineScheduler interfaces and publish them in the header.Andrew Trick2012-09-113-766/+118
| | | | | | | | | | | | | | The Hexagon target decided to use a lot of functionality from the target-independent scheduler. That's fine, and other targets should be able to do the same. This reorg and API update makes that easy. For the record, ScheduleDAGMI was not meant to be subclassed. Instead, new scheduling algorithms should be able to implement MachineSchedStrategy and be done. But if need be, it's nice to be able to extend ScheduleDAGMI, so I also made that easier. The target scheduler is somewhat more apt to break that way though. llvm-svn: 163580
* Revert r160148 it seems to cause more problems than it shouldEric Christopher2012-09-101-1/+1
| | | | | | right now. We'll fix PR13303 a different way. llvm-svn: 163570
* 80-col fixup.Eric Christopher2012-09-103-4/+6
| | | | llvm-svn: 163569
* 80-col fixup.Eric Christopher2012-09-101-1/+2
| | | | llvm-svn: 163568
* No reason to construct this twice.Eric Christopher2012-09-102-2/+2
| | | | llvm-svn: 163567
* Update function names to conform to guidelines. No functional change intended.Chad Rosier2012-09-107-14/+14
| | | | llvm-svn: 163561
* Revert r163556. Missed updates to tablegen files.Chad Rosier2012-09-102-4/+4
| | | | llvm-svn: 163557
* Update function names to conform to guidelines. No functional change intended.Chad Rosier2012-09-102-4/+4
| | | | llvm-svn: 163556
* [ms-inline asm] Properly emit the asm directives when the AsmPrinterVariantChad Rosier2012-09-101-1/+17
| | | | | | and InlineAsmVariant don't match. llvm-svn: 163550
* Remove redundant semicolons which are null statements.Dmitri Gribenko2012-09-106-7/+7
| | | | llvm-svn: 163547
* Disable stack coloring because it makes dragonegg fail bootstrapping.Nadav Rotem2012-09-101-1/+1
| | | | llvm-svn: 163545
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