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* [AMDGPU] fcanonicalize elimination optimizationStanislav Mekhanoshin2017-07-121-9/+86
| | | | | | | | | | | | We are using multiplication by 1.0 to flush denormals and quiet sNaNs. That is possible to omit this multiplication if source of the fcanonicalize instruction is known to be flushed/quieted, i.e. if it comes from another instruction known to do the normalization and we are using IEEE mode to quiet sNaNs. Differential Revision: https://reviews.llvm.org/D35218 llvm-svn: 307848
* Don't expose a map in the DWARFContext interface.Rafael Espindola2017-07-121-6/+6
| | | | | | | | | Doing so is leaking an implementation detail. I have an implementation that uses the lld infrastructure and doesn't use a map or object::SectionRef. llvm-svn: 307846
* [LoopUnrollRuntime] NFC: Refactored safety checks of unrolling multi-exit loopAnna Thomas2017-07-121-47/+58
| | | | | | | | | | | Refactored the code and separated out a function `canSafelyUnrollMultiExitLoop` to reduce redundant checks and make it easier to add profitability heuristics later. Added tests to runtime unrolling to make sure that unrolling for multi-exit loops is not done unless the option -unroll-runtime-multi-exit is true. llvm-svn: 307843
* [AArch64] Add AArch64Subtarget::isFusion function.Florian Hahn2017-07-122-1/+8
| | | | | | | | | | | | | | | | | | | | | | Summary: isFusion returns true if the subtarget supports any kind of instruction fusion, similar to ARMSubtarget::isFusion. This was suggested in D34142. This changes the current behavior slightly, because the macro fusion mutation is now added to the PostRA MachineScheduler in case the subtarget supports any kind of fusion. I think that makes sense because if the PostRA MachineScheduler is run, there is potential that instructions scheduled back to back are re-scheduled. Reviewers: evandro, t.p.northover, joelkevinjones, joel_k_jones, steleman Reviewed By: joelkevinjones Subscribers: joel_k_jones, aemerson, rengolin, javed.absar, kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D34958 llvm-svn: 307842
* [WebAssembly] Mark element atomic memcpy/memmove intrinsics as unsupportedHeejin Ahn2017-07-121-11/+10
| | | | | | | | | | | | | | | | Summary: Element atomic intrinsicAtomic instructions are not yet supported in WebAssembly, so we mark them as unsupported for the moment. Reviewers: sunfish, dschuff, sbc100 Reviewed By: dschuff, sbc100 Subscribers: jfb, sbc100, jgravelle-google Differential Revision: https://reviews.llvm.org/D35322 llvm-svn: 307841
* Remove unneeded use of #undef DEBUG_TYPE. NFCSam Clegg2017-07-124-9/+12
| | | | | | | | | | | Where is is needed (at the end of headers that define it), be consistent about its use. Also fix a few header guards that I found in the process. Differential Revision: https://reviews.llvm.org/D34916 llvm-svn: 307840
* [LV] Don't allow outside uses of IVs if the SCEV is predicated on loop ↵Michael Kuperstein2017-07-121-2/+7
| | | | | | | | | conditions. This fixes PR33706. Differential Revision: https://reviews.llvm.org/D35227 llvm-svn: 307837
* [mips][mt][6/7] Add support for mftr, mttr instructions.Simon Dardis2017-07-126-0/+372
| | | | | | | | | | | | | | | | | Unlike many other instructions, these instructions have aliases which take coprocessor registers, gpr register, accumulator (and dsp accumulator) registers, floating point registers, floating point control registers and coprocessor 2 data and control operands. For the moment, these aliases are treated as pseudo instructions which are expanded into the underlying instruction. As a result, disassembling these instructions shows the underlying instruction and not the alias. Reviewers: slthakur, atanasyan Differential Revision: https://reviews.llvm.org/D35253 llvm-svn: 307836
* Fix non-Windows build after PDB native builtin type changeReid Kleckner2017-07-122-6/+8
| | | | | | Some C++14 features slipped in along with an extra member qualification. llvm-svn: 307835
* [PDB] Enable NativeSession to create symbols for built-in types on demandAdrian McCarthy2017-07-126-5/+108
| | | | | | | | | | | | | | | | Summary: There is a reserved range of type indexes for built-in types (like integers). This will create a symbol for a built-in type if the caller askes for one by type index. This is also plumbing for being able to recall symbols by type index in general, but user-defined types will come in subsequent patches. Reviewers: rnk, zturner Subscribers: mgorny, hiraditya, llvm-commits Differential Revision: https://reviews.llvm.org/D35163 llvm-svn: 307834
* Fix to web assembly lib call listDaniel Neilson2017-07-121-0/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: Revision 307796 caused an internal build break in WebAssembly bots in the form of a crash. ex: Here's the crash dump from one of the failing tests: /usr/local/google/home/blaikie/dev/llvm/build/default/./bin/llc < /usr/local/google/home/blaikie/dev/llvm/src/test/CodeGen/WebAssembly/global.ll -asm-verbose=false -disable-wasm-fallthrough-return-opt -disable-wasm-explicit-locals | /usr/local/google/home/blaikie/dev/llvm/build/default/./bin/FileCheck /usr/local/google/home/blaikie/dev/llvm/src/test/CodeGen/WebAssembly/global.ll -- Exit Code: 2 Command Output (stderr): -- Stack dump: 0. Program arguments: build/default/./bin/llc -asm-verbose=false -disable-wasm-fallthrough-return-opt -disable-wasm-explicit-locals 1. Running pass 'Function Pass Manager' on module '<stdin>'. 2. Running pass 'WebAssembly Assembly Printer' on function '@call_memcpy' FileCheck error: '-' is empty. FileCheck command line: build/default/./bin/FileCheck src/test/CodeGen/WebAssembly/global.ll The problem is in lib/Target/WebAssembly/WebAssemblyRuntimeLibcallSignatures.cpp. There’s an array declared: 545 static const char * Fix to web assembly lib call list Summary: Revision 307796 caused an internal build break in WebAssembly bots in the form of a crash. ex: Here's the crash dump from one of the failing tests: /usr/local/google/home/blaikie/dev/llvm/build/default/./bin/llc < /usr/local/google/home/blaikie/dev/llvm/src/test/CodeGen/WebAssembly/global.ll -asm-verbose=false -disable-wasm-fallthrough-return-opt -disable-wasm-explicit-locals | /usr/local/google/home/blaikie/dev/llvm/build/default/./bin/FileCheck /usr/local/google/home/blaikie/dev/llvm/src/test/CodeGen/WebAssembly/global.ll -- Exit Code: 2 Command Output (stderr): -- Stack dump: 0. Program arguments: build/default/./bin/llc -asm-verbose=false -disable-wasm-fallthrough-return-opt -disable-wasm-explicit-locals 1. Running pass 'Function Pass Manager' on module '<stdin>'. 2. Running pass 'WebAssembly Assembly Printer' on function '@call_memcpy' FileCheck error: '-' is empty. FileCheck command line: build/default/./bin/FileCheck src/test/CodeGen/WebAssembly/global.ll The problem is in lib/Target/WebAssembly/WebAssemblyRuntimeLibcallSignatures.cpp. There’s an array declared: static const char * RuntimeLibcallNames[RTLIB::UNKNOWN_LIBCALL] = { That is defining a runtime lib call name for each entry in the enum RTLIB:Libcall from include/llvm/CodeGen/RuntimeLibcalls.h. Revision 307796 added entries to the enum, but didn’t add entries to the RuntimeLibcallNames array, which caused a crash when attempting to access past the end of the array. This patch fixes the issue by adding the element atomic memmove to the WebAssembly arrays. Reviewed by: reames llvm-svn: 307831
* [LoopRotate] Fix DomTree update logic for unreachable nodes. Fix PR33701.Jakub Kuderski2017-07-121-4/+16
| | | | | | | | | | | | | | | | | | | Summary: LoopRotate manually updates the DoomTree by iterating over all predecessors of a basic block and computing the Nearest Common Dominator. When a predecessor happens to be unreachable, `DT.findNearestCommonDominator` returns nullptr. This patch teaches LoopRotate to handle this case and fixes [[ https://bugs.llvm.org/show_bug.cgi?id=33701 | PR33701 ]]. In the future, LoopRotate should be taught to use the new incremental API for updating the DomTree. Reviewers: dberlin, davide, uabelho, grosser Subscribers: efriedma, mzolotukhin Differential Revision: https://reviews.llvm.org/D35074 llvm-svn: 307828
* Use std::mutex to avoid memory allocation after OOMReid Kleckner2017-07-121-13/+18
| | | | | | | | | | | | | | | ManagedStatic<sys::Mutex> would lazilly allocate a sys::Mutex to lock when reporting an OOM, which is a bad idea. The three STL implementations that I know of use pthread_mutex_lock and EnterCriticalSection to implement std::mutex. I'm pretty sure that neither of those allocate heap memory. It seems that we unconditionally use std::mutex without testing LLVM_ENABLE_THREADS elsewhere in the codebase, so this should be portable. llvm-svn: 307827
* [libFuzzer] Add a dependency on symbolizer from libFuzzer testsGeorge Karpenkov2017-07-121-1/+1
| | | | | | | | | Some libFuzzer tests on Linux would fail with bizarre error messages unless llvm-symbolizer binary is present. Differential Revision: https://reviews.llvm.org/D35313 llvm-svn: 307826
* [libFuzzer] NFC Declare LIBFUZZER_FLAGS_BASE outside of an if-blockGeorge Karpenkov2017-07-121-1/+1
| | | | | | | | | | | The current code relies on the assumption that tests are included only if LLVM_USE_SANITIZE_COVERAGE is enabled. This commit makes it easier to relax the assumption in the future, as the variable LIBFUZZER_FLAGS_BASE is used further in libFuzzer tests. Differential Revision: https://reviews.llvm.org/D35314 llvm-svn: 307825
* [libFuzzer] Do not use LLVM ostream in testsGeorge Karpenkov2017-07-121-0/+3
| | | | | | Differential Revision: https://reviews.llvm.org/D35312 llvm-svn: 307824
* [x86] improve SBB optimizations for SETB/SETA with subtractSanjay Patel2017-07-121-26/+33
| | | | | | | | | | | | | | This is another step towards removing a combine that turns sext into select of constants and preparing the backend for an IR future where select is the canonical form. Earlier commits in this area: https://reviews.llvm.org/rL306040 https://reviews.llvm.org/rL306072 https://reviews.llvm.org/rL307404 (https://reviews.llvm.org/D34652) https://reviews.llvm.org/rL307471 llvm-svn: 307821
* GlobalISel: Handle selection of G_IMPLICIT_DEF in AArch64Justin Bogner2017-07-121-0/+3
| | | | | | | | A generic variant of IMPLICIT_DEF was added in r306875, but this survives to selection and hits a `Cannot Select`. Add handling that converts the note to a regular IMPLICIT_DEF. llvm-svn: 307817
* [mips][mt][5/7] Add support for fork and yield instructions.Simon Dardis2017-07-124-2/+65
| | | | | | | | Reviewers: slthakur, atanasyan Differential Revision: https://reviews.llvm.org/D35252 llvm-svn: 307808
* [CodeGen] Add dependency printerEvandro Menezes2017-07-121-35/+56
| | | | | | | | Add SDep printer to make debugging sessions more productive. Differential revision: https://reviews.llvm.org/D35144 llvm-svn: 307799
* [X86/FastIsel] Fall-back to SelectionDAG when lowering soft-floats.Davide Italiano2017-07-121-0/+3
| | | | | | | | | | FastIsel can't handle them, so we would end up crashing during register class selection. Fixes PR26522. Differential Revision: https://reviews.llvm.org/D35272 llvm-svn: 307797
* Add element atomic memmove intrinsicDaniel Neilson2017-07-123-0/+101
| | | | | | | | | | | | | | Summary: Continuing the work from https://reviews.llvm.org/D33240, this change introduces an element unordered-atomic memmove intrinsic. This intrinsic is essentially memmove with the implementation requirement that all loads/stores used for the copy are done with unordered-atomic loads/stores of a given element size. Reviewers: eli.friedman, reames, mkazantsev, skatkov Reviewed By: reames Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D34884 llvm-svn: 307796
* [mips][mt][4/7] Add IAS support for dvpe, evpe instructions.Simon Dardis2017-07-124-5/+28
| | | | | | | | Reviewers: slthakur, atanasyan Differential Revision: https://reviews.llvm.org/D35251 llvm-svn: 307793
* [ARM] Adjust ifcvt heuristic for the diamond ifcvt caseJohn Brawn2017-07-121-0/+3
| | | | | | | | | When we have a diamond ifcvt the fallthough block will have a branch at the end of it that disappears when predicated, so discount it from the predication cost. Differential Revision: https://reviews.llvm.org/D34952 llvm-svn: 307788
* [mips][mt] Add missing files from last commitSimon Dardis2017-07-122-0/+104
| | | | llvm-svn: 307779
* [mips][mt][3/7] Add IAS support for emt, dmt instructions.Simon Dardis2017-07-124-2/+21
| | | | | | | | Reviewers: slthakur, atanasyan Differential Revision: https://reviews.llvm.org/D35250 llvm-svn: 307774
* [Linker] Add directives to support mixing ARM/Thumb module-level inline asm.Florian Hahn2017-07-121-2/+16
| | | | | | | | | | | | | | | | | | | | | | Summary: By prepending `.text .thumb .balign 2` to the module-level inline assembly from a Thumb module, the assembler will generate the assembly from that module as Thumb, even if the destination module uses an ARM triple. Similar directives are used for module-level inline assembly in ARM modules. The alignment and instruction set are reset based on the target triple before emitting the first function label. Reviewers: olista01, tejohnson, echristo, t.p.northover, rafael Reviewed By: echristo Subscribers: aemerson, javed.absar, eraman, kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D34622 llvm-svn: 307772
* [ARM] GlobalISel: Simplify inst selector code. NFCDiana Picus2017-07-121-198/+143
| | | | | | | | | | | Refactor CmpHelper into something simpler. It was overkill to use templates for this - instead, use a simple CmpConstants structure to hold the opcodes and other constants that are different when selecting int / float / double comparisons. Also, extract some of the helpers that were in CmpHelper into ARMInstructionSelector and make use of some of them when selecting other things than just compares. llvm-svn: 307766
* [PM] Fix a silly bug in my recent update to the CG update logic.Chandler Carruth2017-07-121-1/+1
| | | | | | | | I used the wrong variable to update. This was even covered by a unittest I wrote, and the comments for the unittest were correct (if confusing) but the test itself just matched the buggy behavior. =[ llvm-svn: 307764
* [ARM] GlobalISel: Select s64 G_FCMPDiana Picus2017-07-121-3/+38
| | | | | | | Very similar to how we select s32 G_FCMP, the only thing that is different is the exact opcodes that we use. llvm-svn: 307763
* Have Module::createRNG return a unique_ptrSerge Guelton2017-07-121-2/+2
| | | | | | Instead of a raw pointer, this makes memory management safer. llvm-svn: 307762
* [X86] Synchronize the ProcessorFeatures enum used by getHostCPUName with the ↵Craig Topper2017-07-121-41/+123
| | | | | | | | enum in libgcc and soon compiler-rt. This adds all the feature bits libgcc has. They will soon be added to compiler-rt as well. This adds a second 32 bit feature variable to hold the bits that are needed by getHostCPUName that are not in libgcc. libgcc had already used 31 of the 32 bits in the existing variable and we needed 3 bits so at minimum 2 bits would spill over. I chose to move all 3. llvm-svn: 307758
* [X86] Sync ProcessorTypes and ProcessorSubtypes enums used by getHostCPUName ↵Craig Topper2017-07-121-50/+35
| | | | | | | | with the version proposed to for compiler-rt's cpu_model.c This keeps the starting entries in the enums in sync with what's in gcc and in review D35214 for compiler-rt. llvm-svn: 307757
* [X86] Cleanup the switches in getHostCPUName to remove impossible combinations.Craig Topper2017-07-121-26/+9
| | | | llvm-svn: 307756
* [X86] Remove 'barcelona' string from getHostCPUName. Use 'amdfam10' instead. ↵Craig Topper2017-07-121-2/+0
| | | | | | The x86 backend doesn't distinguish. llvm-svn: 307755
* [MemoryBuiltins] Allow truncation in visitAllocaInst()Mikael Holmen2017-07-121-17/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: Solves PR33689. If the pointer size is less than the size of the type used for the array size in an alloca (the <ty> type below) then we could trigger the assert in the PR. In that example we have pointer size i16 and <ty> is i32. <result> = alloca [inalloca] <type> [, <ty> <NumElements>] [, align <alignment>] Handle the situation by allowing truncation as well as zero extension in ObjectSizeOffsetVisitor::visitAllocaInst(). Also, we now detect overflow in visitAllocaInst(), similar to how it was already done in visitCallSite(). Reviewers: craig.topper, rnk, george.burgess.iv Reviewed By: george.burgess.iv Subscribers: davide, llvm-commits Differential Revision: https://reviews.llvm.org/D35003 llvm-svn: 307754
* Fix minor typo introduced in r276404Don Hinton2017-07-121-1/+1
| | | | | | | | | | | | | | | | | Summary: A space was added between '-' and 'help' when emitting help output. See https://reviews.llvm.org/D22621 for details. Reviewers: MaggieYi, vsk Reviewed By: vsk Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D35283 llvm-svn: 307745
* LowerTypeTests: When importing functions skip definitions where the summary ↵Peter Collingbourne2017-07-121-3/+8
| | | | | | | | | | | | | | contains a decl. This normally indicates mixed CFI + non-CFI compilation, and will result in us treating the function in the same way as a function defined outside of the LTO unit. Part of PR33752. Differential Revision: https://reviews.llvm.org/D35281 llvm-svn: 307744
* [WebAssembly] Expose the offset of each data segmentSam Clegg2017-07-122-5/+8
| | | | | | | | | | | | | | Summary: This allows tools like lld that process relocations to apply data relocation correctly. This information is required because relocation are stored as section offset. Subscribers: jfb, dschuff, jgravelle-google, aheejin Differential Revision: https://reviews.llvm.org/D35234 llvm-svn: 307741
* Fix unused variable warningsKonstantin Zhuravlyov2017-07-121-0/+2
| | | | | | Differential Revision: https://reviews.llvm.org/D35280 llvm-svn: 307740
* Simplify interface now that we don't need to pass IsPCRel. NFC.Rafael Espindola2017-07-115-16/+20
| | | | llvm-svn: 307734
* [codeview] Change readobj symbol dumping formatReid Kleckner2017-07-111-72/+19
| | | | | | | | Avoid duplicating DictScope with hand-written names everywhere. Print the S_-prefixed symbol kind for every record. This should make it easier to search for certain kinds of records when debugging PDB linking. llvm-svn: 307732
* Fully fix the movw/movt addend.Rafael Espindola2017-07-1115-35/+35
| | | | | | | | | | The issue is not if the value is pcrel. It is whether we have a relocation or not. If we have a relocation, the static linker will select the upper bits. If we don't have a relocation, we have to do it. llvm-svn: 307730
* [IPO] Temporarily rollback r307215.Davide Italiano2017-07-111-18/+0
| | | | | | | | | [GlobalOpt] Remove unreachable blocks before optimizing a function. While the change is presumably correct, it exposes a latent bug in DI which breaks on of the CFI checks. I'll analyze it further and try to understand what's going on. llvm-svn: 307729
* [codeview] Fix type index discovery for four symbol recordsReid Kleckner2017-07-111-0/+12
| | | | | | | | | | | | I encountered these when linking LLD, which uses atls.lib. Those objects appear to use these uncommon symbol records: 0x115E S_HEAPALLOCSITE 0x113D S_ENVBLOCK 0x1113 S_GTHREAD32 0x1153 S_FILESTATIC llvm-svn: 307725
* Enhance synchscope representationKonstantin Zhuravlyov2017-07-1134-209/+433
| | | | | | | | | | | | | | | | | | | | | | | | | | | OpenCL 2.0 introduces the notion of memory scopes in atomic operations to global and local memory. These scopes restrict how synchronization is achieved, which can result in improved performance. This change extends existing notion of synchronization scopes in LLVM to support arbitrary scopes expressed as target-specific strings, in addition to the already defined scopes (single thread, system). The LLVM IR and MIR syntax for expressing synchronization scopes has changed to use *syncscope("<scope>")*, where <scope> can be "singlethread" (this replaces *singlethread* keyword), or a target-specific name. As before, if the scope is not specified, it defaults to CrossThread/System scope. Implementation details: - Mapping from synchronization scope name/string to synchronization scope id is stored in LLVM context; - CrossThread/System and SingleThread scopes are pre-defined to efficiently check for known scopes without comparing strings; - Synchronization scope names are stored in SYNC_SCOPE_NAMES_BLOCK in the bitcode. Differential Revision: https://reviews.llvm.org/D21723 llvm-svn: 307722
* [CodeGen] Rename DEBUG_TYPE to match passnamesEvandro Menezes2017-07-1111-11/+11
| | | | | | | | | Rename missing DEBUG_TYPE "machine-scheduler" from backend files, which were absent from https://reviews.llvm.org/rL303921. Differential revision: https://reviews.llvm.org/D35231 llvm-svn: 307719
* [mips][mt] Correct spelling error in comment. NFCI.Simon Dardis2017-07-111-1/+1
| | | | llvm-svn: 307717
* [mips][mt][2/7] Implement .module and .set directives for the MT ASE.Simon Dardis2017-07-113-0/+82
| | | | | | | | | | | | This patch implements the .module and .set directives for the MT ASE, notably that .module sets the relevant flags in .MIPS.abiflags and .set doesn't. Reviewers: slthakur, atanasyan Differential Revision: https://reviews.llvm.org/D35249 llvm-svn: 307716
* [ARM, ELF] Don't shift movt relocation offsetsMartin Storsjo2017-07-111-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | For ELF, a movw+movt pair is handled as two separate relocations. If an offset should be applied to the symbol address, this offset is stored as an immediate in the instruction (as opposed to stored as an offset in the relocation itself). Even though the actual value stored in the movt immediate after linking is the top half of the value, we need to store the unshifted offset prior to linking. When the relocation is made during linking, the offset gets added to the target symbol value, and the upper half of the value is stored in the instruction. This makes sure that movw+movt with offset symbols get properly handled, in case the offset addition in the lower half should be carried over to the upper half. This makes the output from the additions to the test case match the output from GNU binutils. For COFF and MachO, the movw/movt relocations are handled as a pair, and the overflow from the lower half gets carried over to the movt, so they should keep the shifted offset just as before. Differential Revision: https://reviews.llvm.org/D35242 llvm-svn: 307713
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