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* [CodeView] Only add the Scoped flag for an enum type when it has an ↵Aaron Smith2018-10-021-5/+13
| | | | | | | | | | | | immediate function scope to match MSVC Reviewers: rnk, zturner, llvm-commits Reviewed By: rnk Differential Revision: https://reviews.llvm.org/D52706 llvm-svn: 343627
* [CodeView] Emit function options for subprogram and member functionsAaron Smith2018-10-022-12/+44
| | | | | | | | | | | | | | | | | | | | | | | | | Summary: Use the newly added DebugInfo (DI) Trivial flag, which indicates if a C++ record is trivial or not, to determine Codeview::FunctionOptions. Clang and MSVC generate slightly different Codeview for C++ records. For example, here is the C++ code for a class with a defaulted ctor, class C { public: C() = default; }; Clang will produce a LF for the defaulted ctor while MSVC does not. For more details, refer to FIXMEs in the test cases in "function-options.ll" included with this set of changes. Reviewers: zturner, rnk, llvm-commits, aleksandr.urakov Reviewed By: rnk Subscribers: Hui, JDevlieghere Differential Revision: https://reviews.llvm.org/D45123 llvm-svn: 343626
* Revert "X86, AArch64, ARM: Do not attach debug location to spill/reload ↵Matt Morehouse2018-10-023-21/+29
| | | | | | | | instructions" This reverts r343520 due to breakage of HWASan tests on Android. llvm-svn: 343616
* [X86][Disassembler] Add bizarro versions of the MOVSXD instruction that sign ↵Craig Topper2018-10-021-0/+20
| | | | | | | | | | extend from a GR32 to GR32 or GR16. The 0x63 opcodes in 64-bit mode have a fixed source size of 32-bits, but the destination size is controlled by REX.W and the 0x66 opsize prefix. This instruction is normally used with a REX.W prefix which provides desired behavior. The other encodings are interpretted as valid by the processor, but aren't useful. This patch makes us recognize them for the disassembler to match objdump. llvm-svn: 343614
* [globalisel][verifier] Run the MachineVerifier from IRTranslator onwardsDaniel Sanders2018-10-022-0/+9
| | | | | | | | | | | | | | -verify-machineinstrs inserts the MachineVerifier after every MachineInstr-based pass. However, GlobalISel creates MachineInstr-based passes earlier than DAGISel and the corresponding verifiers are not being added. This patch fixes that. If GlobalISel triggers the fallback path then the MIR can be left in a bad state that is going to be cleared by ResetMachineFunctions. In this situation verifying between GlobalISel passes will prevent the fallback path from recovering from this. As a result, we bail out of verifying a function if the FailedISel attribute is present. llvm-svn: 343613
* [codeview] Fix 32-bit x86 variable locations in realigned stack framesReid Kleckner2018-10-028-8/+90
| | | | | | | | | | | | | | | | | | Add the .cv_fpo_stackalign directive so that we can define $T0, or the VFRAME virtual register, with it. This was overlooked in the initial implementation because unlike MSVC, we push CSRs before allocating stack space, so this value is only needed to describe local variable locations. Variables that the compiler now addresses via ESP are instead described as being stored at offsets from VFRAME, which for us is ESP after alignment in the prologue. This adds tests that show that we use the VFRAME register properly in our S_DEFRANGE records, and that we emit the correct FPO data to define it. Fixes PR38857 llvm-svn: 343603
* [X86][Btver2] Fix BLENDV and AESDEC schedulesSimon Pilgrim2018-10-021-4/+4
| | | | | | Match AMD Fam16h SOG + llvm-exegesis tests llvm-svn: 343597
* [Hexagon] Fix extracting subvectors of non-HVX vNi1Krzysztof Parzyszek2018-10-021-1/+2
| | | | | | Patch by Brendon Cahoon. llvm-svn: 343596
* [ARM] Emmit data symbol for constant pool dataDiogo N. Sampaio2018-10-021-0/+5
| | | | | | | | | | | The ARM elf emitter would omit printing data symbol when constant data. This patch overrides the emitFill method as to enforce that the symbol is correctly printed. Differential revision: https://reviews.llvm.org/D52737 llvm-svn: 343594
* [X86] Remove unnecessary BT(C/R/S)m(i/r) scheduler overridesSimon Pilgrim2018-10-027-38/+24
| | | | | | Some SchedAlias remain due to some badly setup RMW tags - but at least the overrides are all removed llvm-svn: 343586
* [X86] Add APInt constant assembly printer helperSimon Pilgrim2018-10-021-15/+18
| | | | llvm-svn: 343577
* [AArch64][v8.5A] Add Memory Tagging instructionsOliver Stannard2018-10-025-22/+218
| | | | | | | | | | | This adds new instructions to manipluate tagged pointers, and to load and store the tags associated with memory. Patch by Pablo Barrio, David Spickett and Oliver Stannard! Differential revision: https://reviews.llvm.org/D52490 llvm-svn: 343572
* [AArch64][v8.5A] Add Memory Tagging system registersOliver Stannard2018-10-021-0/+16
| | | | | | | | | | | This adds new system registers introduced by the Memory Tagging extension. Patch by Pablo Barrio! Differential revision: https://reviews.llvm.org/D52488 llvm-svn: 343571
* [AArch64][v8.5A] Add MTE system instructionsOliver Stannard2018-10-022-0/+22
| | | | | | | | | | | The Memory Tagging Extension adds system instructions for data cache maintenance, implemented as new operands to the DC instruction. Patch by Pablo Barrio! Differential revision: https://reviews.llvm.org/D52487 llvm-svn: 343570
* [InstCombine] Fold ~A - Min/Max(~A, O) -> Max/Min(A, ~O) - ADavid Green2018-10-022-1/+41
| | | | | | | | | | | | | | | This is an attempt to get out of a local-minimum that instcombine currently gets stuck in. We essentially combine two optimisations at once, ~a - ~b = b-a and min(~a, ~b) = ~max(a, b), only doing the transform if the result is at least neutral. This involves using IsFreeToInvert, which has been expanded a little to include selects that can be easily inverted. This is trying to fix PR35875, using the ideas from Sanjay. It is a large improvement to one of our rgb to cmy kernels. Differential Revision: https://reviews.llvm.org/D52177 llvm-svn: 343569
* [AArch64][v8.5A] Add MTE as an optional AArch64 extensionOliver Stannard2018-10-022-0/+5
| | | | | | | | | | | | This adds the memory tagging extension, which is an optional extension introduced in v8.5A. The new instructions and registers will be added by subsequent patches. Patch by Pablo Barrio! Differential revision: https://reviews.llvm.org/D52486 llvm-svn: 343563
* [X86] Standardize floating point assembly commentsSimon Pilgrim2018-10-021-7/+11
| | | | | | | | Consistently try to use APFloat::toString for floating point constant comments to get rid of differences between Constant / ConstantDataSequential values - it should help stop some of the linux-windows buildbot failures matching NaN/INF etc. as well. Differential Revision: https://reviews.llvm.org/D52702 llvm-svn: 343562
* AMDGPU: Expand atomicrmw nand in IRMatt Arsenault2018-10-023-0/+10
| | | | llvm-svn: 343559
* [WebAssembly] Restore slashes in SIMD conversion namesThomas Lively2018-10-021-8/+8
| | | | | | | | | | | | Summary: Depends on D52372 and D52442. Reviewers: aheejin, dschuff, aardappel Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D52512 llvm-svn: 343558
* [SimplifyCFG] Use Value::hasNUses instead of 'getNumUses() =='. NFCICraig Topper2018-10-011-1/+1
| | | | | | getNumUses is linear in the number of uses. Since we're looking for a specific use count, we can use hasNUses which will stop as soon as it determines there are more than N uses instead of walking all of them. llvm-svn: 343550
* [SimplifyCFG] Update comments that refer to CondBB to say ThenBB instead. NFCCraig Topper2018-10-011-4/+4
| | | | | | There is no variable in this function named CondBB, but there is one named ThenBB and I believe the comments are all refering to it. llvm-svn: 343548
* [PDB] Add support for more kinds of PDB Sym Tags.Zachary Turner2018-10-011-1/+13
| | | | | | | DIA SDK is returning several new sym tag types, so we update the enumeration and printing code to support these. llvm-svn: 343547
* Revert: r343521 and r343541: [globalisel] Add a combiner helpers for ↵Daniel Sanders2018-10-016-361/+4
| | | | | | | | | | extending loads and use them in a pre-legalize combiner for AArch64 There's a strange assertion on two of the Green Dragon bots that goes away when this is reverted. The assertion is in RegBankAlloc and if it is this commit then -verify-machine-instrs should have caught it earlier in the pipeline. llvm-svn: 343546
* [codeview] Simplify S_DEFRANGE emission code, NFCReid Kleckner2018-10-011-30/+22
| | | | | | | These assembler directives are still pretty unreadable and it would be nice to clean them up at some point. llvm-svn: 343544
* [codeview] Emit S_FRAMEPROC and use S_DEFRANGE_FRAMEPOINTER_RELReid Kleckner2018-10-016-42/+260
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: Before this change, LLVM would always describe locals on the stack as being relative to some specific register, RSP, ESP, EBP, ESI, etc. Variables in stack memory are pretty common, so there is a special S_DEFRANGE_FRAMEPOINTER_REL symbol for them. This change uses it to reduce the size of our debug info. On top of the size savings, there are cases on 32-bit x86 where local variables are addressed from ESP, but ESP changes across the function. Unlike in DWARF, there is no FPO data to describe the stack adjustments made to push arguments onto the stack and pop them off after the call, which makes it hard for the debugger to find the local variables in frames further up the stack. To handle this, CodeView has a special VFRAME register, which corresponds to the $T0 variable set by our FPO data in 32-bit. Offsets to local variables are instead relative to this value. This is part of PR38857. Reviewers: hans, zturner, javed.absar Subscribers: aprantl, hiraditya, JDevlieghere, llvm-commits Differential Revision: https://reviews.llvm.org/D52217 llvm-svn: 343543
* Fix the Windows build in GlobalISelReid Kleckner2018-10-011-7/+6
| | | | | | | | | | | | | | Clang-cl was complaining about some sort of constexpr narrowing bug: C:\src\llvm-project\llvm\lib\CodeGen\GlobalISel\CombinerHelper.cpp(136,31): error: non-constant-expression cannot be narrowed from type 'llvm::TargetOpcode::(anonymous enum at C:\src\llvm-project\llvm\include\llvm/CodeGen/TargetOpcodes.h:22:1)' to 'unsigned int' in initializer list [-Wc++11-narrowing] unsigned(MI.getOpcode()) == unsigned(TargetOpcode::G_LOAD) ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ C:\src\llvm-project\llvm\lib\CodeGen\GlobalISel\CombinerHelper.cpp(136,31): note: insert an explicit cast to silence this issue unsigned(MI.getOpcode()) == unsigned(TargetOpcode::G_LOAD) ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ static_cast<unsigned int>( llvm-svn: 343541
* Recommit r343499 "[X86] Enable load folding in the test shrinking code"Craig Topper2018-10-011-9/+25
| | | | | | | Original message: This patch adds load folding support to the test shrinking code. This was noticed missing in the review for D52669 llvm-svn: 343540
* Recommit r343498 "[X86] Improve test instruction shrinking when the sign ↵Craig Topper2018-10-011-5/+21
| | | | | | | | | | | | | | | flag is used and the output of the and is truncated." This includes a fix to prevent i16 compares with i32/i64 ands from being shrunk if bit 15 of the and is set and the sign bit is used. Original commit message: Currently we skip looking through truncates if the sign flag is used. But that's overly restrictive. It's safe to look through the truncate as long as we ensure one of the 3 things when we shrink. Either the MSB of the mask at the shrunken size isn't set. If the mask bit is set then either the shrunk size needs to be equal to the compare size or the sign There are still missed opportunities to shrink a load and fold it in here. This will be fixed in a future patch. llvm-svn: 343539
* [PowerPC] Folding XForm to DForm loads requires alignment for some DForm loads.Stefan Pintilie2018-10-011-0/+8
| | | | | | | | | | | Going from XForm Load to DSForm Load requires that the immediate be 4 byte aligned. If we are not aligned we must leave the load as LDX (XForm). This bug is causing a compile-time failure in the benchmark h264ref. Differential Revision: https://reviews.llvm.org/D51988 llvm-svn: 343525
* Temporarily revert "[GVNHoist] Re-enable GVNHoist by default"Eric Christopher2018-10-012-4/+4
| | | | | | | | | This reverts commit r342387 as it's showing significant performance regressions in a number of benchmarks. Followed up with the committer and original thread with an example and will get performance numbers before recommitting. llvm-svn: 343522
* [globalisel] Add a combiner helpers for extending loads and use them in a ↵Daniel Sanders2018-10-016-4/+362
| | | | | | | | | | | | | | pre-legalize combiner for AArch64 Summary: Depends on D45541 Reviewers: ab, aditya_nandakumar, bogner, rtereshin, volkan, rovka, javed.absar, aemerson Subscribers: aemerson, rengolin, mgorny, javed.absar, kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D45543 llvm-svn: 343521
* X86, AArch64, ARM: Do not attach debug location to spill/reload instructionsMatthias Braun2018-10-013-29/+21
| | | | | | | | | | | Spill/reload instructions are artificially generated by the compiler and have no relation to the original source code. So the best thing to do is not attach any debug location to them (instead of just taking the next debug location we find on following instructions). Differential Revision: https://reviews.llvm.org/D52125 llvm-svn: 343520
* Revert r343499 and r343498. X86 test improvementsCraig Topper2018-10-011-43/+14
| | | | | | | | There's a subtle bug in the handling of truncate from i32/i64 to i32 without minsize. I'll be adding more test cases and trying to find a fix. llvm-svn: 343516
* [Hexagon] Remove incorrect pattern for swizKrzysztof Parzyszek2018-10-011-8/+0
| | | | | | | | | | | | The pattern had a couple of problems: - It was checking for loads of bytes in the reverse order to what it should have been looking for. - It would replace loads of bytes with a load of a word without making sure that the alignment was correct. Thanks to Eli Friedman for pointing it out. llvm-svn: 343514
* [AMDGPU] Fixed SIInstrInfo::getOpSize to handle subregsStanislav Mekhanoshin2018-10-011-0/+5
| | | | | | | | | | Currently it returns incorrect operand size for a target independet node such as COPY if operand is a register with subreg. Instead of correct subreg size it returns a size of the whole superreg. Differential Revision: https://reviews.llvm.org/D52736 llvm-svn: 343508
* [PDB] Add support for dumping Typedef records.Zachary Turner2018-10-015-0/+123
| | | | | | | | | | These work a little differently because they are actually in the globals stream and are treated as symbol records, even though DIA presents them as types. So this also adds the necessary infrastructure to cache records that live somewhere other than the TPI stream as well. llvm-svn: 343507
* [PDB] Add support for parsing VFTable Shape records.Zachary Turner2018-10-015-2/+53
| | | | | | This allows them to be returned from the native API. llvm-svn: 343506
* MIRParser: Check that instructions only reference DILocation metadataMatthias Braun2018-10-011-0/+2
| | | | llvm-svn: 343505
* [WebAssembly] Fixed AsmParser not allowing instructions with /Wouter van Oortmerssen2018-10-011-9/+28
| | | | | | | | | | | | | | | | | | | Summary: The AsmParser Lexer regards these as a seperate token. Here we expand the instruction name with them if they are adjacent (no whitespace). Tested: the basic-assembly.s test case has one case with a / in it. The currently are also instructions with : in them, which we intend to rename rather than fix them here. Reviewers: tlively, dschuff Subscribers: sbc100, jgravelle-google, aheejin, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D52442 llvm-svn: 343501
* [X86] Enable load folding in the test shrinking codeCraig Topper2018-10-011-9/+25
| | | | | | | | This patch adds load folding support to the test shrinking code. This was noticed missing in the review for D52669 Differential Revision: https://reviews.llvm.org/D52699 llvm-svn: 343499
* [X86] Improve test instruction shrinking when the sign flag is used and the ↵Craig Topper2018-10-011-5/+18
| | | | | | | | | | | | | | output of the and is truncated Currently we skip looking through truncates if the sign flag is used. But that's overly restrictive. It's safe to look through the truncate as long as we ensure one of the 3 things when we shrink. Either the MSB of the mask at the shrunken size isn't set. If the mask bit is set then either the shrunk size needs to be equal to the compare size or the sign flag needs to be unused. There are still missed opportunities to shrink a load and fold it in here. This will be fixed in a future patch. Differential Revision: https://reviews.llvm.org/D52669 llvm-svn: 343498
* [X86][Btver2] Fix BT(C|R|S)mr & BT(C|R|S)mi schedule latency + uop countsSimon Pilgrim2018-10-011-2/+2
| | | | | | Match AMD Fam16h SOG + llvm-exegesis tests llvm-svn: 343494
* DAGCombiner: StoreMerging: Fix bad index calculating when adjusting ↵Matthias Braun2018-10-011-17/+8
| | | | | | | | | | | | | | | | mismatching vector types This fixes a case of bad index calculation when merging mismatching vector types. This changes the existing code to just use the existing extract_{subvector|element} and a bitcast (instead of bitcast first and then newly created extract_xxx) so we don't need to adjust any indices in the first place. rdar://44584718 Differential Revision: https://reviews.llvm.org/D52681 llvm-svn: 343493
* [X86] Create schedule classes for BT(C|R|S)mi and BT(C|R|S)mr instructionsSimon Pilgrim2018-10-0111-49/+71
| | | | llvm-svn: 343490
* [AArch64] Refactor cheap cost modelEvandro Menezes2018-10-011-12/+23
| | | | | | | Refactor the order in `TII::isAsCheapAsAMove()` to ease future development and maintenance. Practically NFC. llvm-svn: 343489
* [X86] Remove unnecessary BTmi/BTmr scheduler overridesSimon Pilgrim2018-10-017-56/+9
| | | | llvm-svn: 343487
* [InstCombine] Handle vector compares in foldGEPIcmp(), take 2Jesper Antonsson2018-10-011-1/+2
| | | | | | | | | | | | | | | | | | | Summary: This is a continuation of the fix for PR34627 "InstCombine assertion at vector gep/icmp folding". (I just realized bugpoint had fuzzed the original test for me, so I had fixed another trigger of the same assert in adjacent code in InstCombine.) This patch avoids optimizing an icmp (to look only at the base pointers) when the resulting icmp would have a different type. The patch adds a testcase and also cleans up and shrinks the pre-existing test for the adjacent assert trigger. Reviewers: lebedev.ri, majnemer, spatel Reviewed By: lebedev.ri Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D52494 llvm-svn: 343486
* [X86][Btver2] Fix BTmr schedule uop countsSimon Pilgrim2018-10-011-1/+1
| | | | | | Match AMD Fam16h SOG + llvm-exegesis tests llvm-svn: 343484
* [InstCombine] try to convert vector insert+extract to trunc; 2nd trySanjay Patel2018-10-011-2/+46
| | | | | | | | | | | | | | | | | | | | | | | This was originally committed at rL343407, but reverted at rL343458 because it crashed trying to handle a case where the destination type is FP. This version of the patch adds a check for that possibility. Tests added at rL343480. Original commit message: This transform is requested for the backend in: https://bugs.llvm.org/show_bug.cgi?id=39016 ...but I figured it was worth doing in IR too, and it's probably easier to implement here, so that's this patch. In the simplest case, we are just truncating a scalar value. If the extract index doesn't correspond to the LSBs of the scalar, then we have to shift-right before the truncate. Endian-ness makes this tricky, but hopefully the ASCII-art helps visualize the transform. Differential Revision: https://reviews.llvm.org/D52439 llvm-svn: 343482
* [X86] Create schedule classes for BTmi and BTmr instructionsSimon Pilgrim2018-10-0111-27/+53
| | | | llvm-svn: 343478
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