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* Add target specific node for PMULUDQ. Change patterns to use it and custom ↵Craig Topper2012-02-054-69/+69
| | | | | | lower intrinsics to it. Use it instead of intrinsic to handle 64-bit vector multiplies. llvm-svn: 149807
* Improve the bitcode reader's handling of constant strings to useChris Lattner2012-02-051-22/+6
| | | | | | | ConstantDataArray::getString direction, instead of "boxing" each byte into a ConstantInt and using ConstantArray::get. llvm-svn: 149805
* reapply the patches reverted in r149470 that reenable ConstantDataArray,Chris Lattner2012-02-0515-490/+264
| | | | | | | | | but with a critical fix to the SelectionDAG code that optimizes copies from strings into immediate stores: the previous code was stopping reading string data at the first nul. Address this by adding a new argument to llvm::getConstantStringInfo, preserving the behavior before the patch. llvm-svn: 149800
* Remove most of the intrinsics for XOP VPCMOV instruction. They all aliased ↵Craig Topper2012-02-051-125/+0
| | | | | | to the same instruction with different types. This would be better accomplished with casts in the not yet created xopintrin.h header file. llvm-svn: 149795
* Modified the Enhanced Disassembler to create andSean Callanan2012-02-043-31/+40
| | | | | | | | | | cache disassemblers according to the string value of the target triple, not according to the enum of the triple CPU. The reason for this is that certain attributes of the instruction set are not reflected in the enum, but only in the string. llvm-svn: 149773
* Drop the REDEF_BY_EC VNInfo flag.Jakob Stoklund Olesen2012-02-043-37/+0
| | | | | | | | | | A live range that has an early clobber tied redef now looks like a normal tied redef, except the early clobber def uses the early clobber slot. This is enough to handle any strange interference problems. llvm-svn: 149769
* Correctly terminate a physreg redefined by an early clobber.Jakob Stoklund Olesen2012-02-041-1/+1
| | | | | | | | | | | | | | | | | I don't have a test that fails because of this, but a test case like CodeGen/X86/2009-12-01-EarlyClobberBug.ll exposes the problem. EAX is redefined by a tied early clobber operand on inline asm, and the live range should look like this: %EAX,inf = [48r,64e:0)[64e,80r:1) 0@48r 1@64e Previously, the two values got merged: %EAX,inf = [48r,80r:0) 0@48r With this bug fixed, the REDEF_BY_EC VNInfo flag is no longer needed. llvm-svn: 149768
* Fix a leak!Nick Lewycky2012-02-041-0/+2
| | | | | | | | | | | | Andy, in a previous commit you made this into an ImmutablePass so that you could add it to the PassManager, then in the next commit you left it a Pass but removed the code that added it to the PM. If you do add it to the PM then the PM should take care of deleting it, but it's also true that nothing in codegen needs this object to exist after it's done its work here. It's not clear to me which design you want; this should likely either cease to be a Pass or be added to the PM where other parts of CodeGen will request it. llvm-svn: 149765
* Don't store COPY pointers in VNInfo.Jakob Stoklund Olesen2012-02-047-96/+46
| | | | | | | | | | If a value is defined by a COPY, that instuction can easily and cheaply be found by getInstructionFromIndex(VNI->def). This reduces the size of VNInfo from 24 to 16 bytes, and improves llc compile time by 3%. llvm-svn: 149763
* Boost the effective chain depth of loads and stores.Hal Finkel2012-02-041-0/+10
| | | | | | By default, boost the chain depth contribution of loads and stores. This will allow a load/store pair to vectorize even when it would not otherwise be long enough to satisfy the chain depth requirement. llvm-svn: 149761
* remove the blank line from previous ci.Qirun Zhang2012-02-041-1/+0
| | | | llvm-svn: 149758
* test commit.Qirun Zhang2012-02-041-0/+1
| | | | | | add a blank line. llvm-svn: 149757
* TargetPassConfig: confine the MC configuration to TargetMachine.Andrew Trick2012-02-0424-174/+170
| | | | | | | | | | Passes prior to instructon selection are now split into separate configurable stages. Header dependencies are simplified. The bulk of this diff is simply removal of the silly DisableVerify flags. Sorry for the target header churn. Attempting to stabilize them. llvm-svn: 149754
* Move TargetPassConfig implementation into Passes.cppAndrew Trick2012-02-042-305/+312
| | | | llvm-svn: 149753
* Make TargetPassConfig an ImmutablePass so CodeGenPasses can query optionsAndrew Trick2012-02-043-15/+37
| | | | llvm-svn: 149752
* Object: avoid undefined behavior when bounds-checkingDylan Noblesmith2012-02-041-8/+22
| | | | | | | | | | Don't form an out of bounds pointer just to test if it would be out of bounds. Also perform the same bounds checking for all the previous mapped structures. llvm-svn: 149750
* Emit new property tag.Devang Patel2012-02-041-1/+29
| | | | llvm-svn: 149737
* Update llvm debug version to support new structure and tag for Objective-C ↵Devang Patel2012-02-041-1/+1
| | | | | | property's debug info. llvm-svn: 149736
* Introduce DIObjCProperty. This will be used to encode objective-c property.Devang Patel2012-02-042-0/+20
| | | | llvm-svn: 149732
* [fast-isel] HandlePHINodesInSuccessorBlocks() can promite i8 and i16 types too.Chad Rosier2012-02-041-2/+2
| | | | llvm-svn: 149730
* Add new tag and an attribute to support debug info for objective-c property.Devang Patel2012-02-031-0/+2
| | | | llvm-svn: 149724
* Trim headers.Jakob Stoklund Olesen2012-02-031-8/+0
| | | | llvm-svn: 149722
* Delete some dead code.Jakob Stoklund Olesen2012-02-031-5/+0
| | | | llvm-svn: 149717
* [fast-isel] Add support for URem.Chad Rosier2012-02-031-8/+10
| | | | llvm-svn: 149716
* Handle register mask operands in setPhysRegsDeadExcept().Jakob Stoklund Olesen2012-02-031-0/+12
| | | | | | | | | | | Calls that use register mask operands don't have implicit defs for returned values. The register mask operand handles the call clobber, but it always behaves like a set of dead defs. Add live implicit defs for any implicitly defined physregs that are actually used. llvm-svn: 149715
* [fast-isel] Rename isZExt to isSigned. No functional change intended.Chad Rosier2012-02-031-13/+14
| | | | llvm-svn: 149714
* [fast-isel] Add support for UDIV.Chad Rosier2012-02-031-8/+10
| | | | llvm-svn: 149712
* ArrayRef'ize MI::setPhysRegsDeadExcept().Jakob Stoklund Olesen2012-02-031-3/+3
| | | | llvm-svn: 149709
* Handle all live physreg defs in the same place.Jakob Stoklund Olesen2012-02-032-44/+47
| | | | | | | | | | | SelectionDAG has 4 different ways of passing physreg defs to users. Collect all of the uses at the same time, and pass all of them to MI->setPhysRegsDeadExcept() to mark the remaining defs dead. The setPhysRegsDeadExcept() function will soon add the required implicit-defs to instructions with register mask operands. llvm-svn: 149708
* [fast-isel] Add support for FPToUI. Also add test cases for FPToSI.Chad Rosier2012-02-031-6/+8
| | | | llvm-svn: 149706
* Initialize all common codegen passes before configuration so we can use ↵Andrew Trick2012-02-031-0/+7
| | | | | | their PassIDs. llvm-svn: 149705
* [fast-isel] Add support for selecting UIToFP.Chad Rosier2012-02-031-6/+8
| | | | llvm-svn: 149704
* Simplify some GEP checks in the verifier.Duncan Sands2012-02-031-4/+2
| | | | llvm-svn: 149698
* The type-legalizer often scalarizes code. One of the common patterns is ↵Nadav Rotem2012-02-031-0/+34
| | | | | | | | | extract-and-truncate. In this patch we optimize this pattern and convert the sequence into extract op of a narrow type. This allows the BUILD_VECTOR dag optimizations to construct efficient shuffle operations in many cases. llvm-svn: 149692
* Remove getShuffleVPERMILPImmediate function, getShuffleSHUFImmediate ↵Craig Topper2012-02-031-30/+1
| | | | | | performs the same calculation. llvm-svn: 149683
* Remove unnecessary qualification on 256-bit vector handling in ↵Craig Topper2012-02-031-2/+2
| | | | | | LowerBUILD_VECTOR. Condition was already guaranteed by earlier code. llvm-svn: 149680
* Add auto upgrade support for x86 pcmpgt/pcmpeq intrinics removed in r149367.Craig Topper2012-02-031-3/+40
| | | | llvm-svn: 149678
* Added TargetPassConfig. The first little step toward configuring codegen passes.Andrew Trick2012-02-0323-198/+451
| | | | | | | | | | | Allows command line overrides to be centralized in LLVMTargetMachine.cpp. LLVMTargetMachine can intercept common passes and give precedence to command line overrides. Allows adding "internal" target configuration options without touching TargetOptions. Encapsulates the PassManager. Provides a good point to initialize all CodeGen passes so that Pass ID's can be used in APIs. Allows modifying the target configuration hooks without rebuilding the world. llvm-svn: 149672
* whitespaceAndrew Trick2012-02-037-32/+32
| | | | llvm-svn: 149671
* Add a new MachineJumpTableInfo entry type, EK_GPRel64BlockAddress, which isAkira Hatanaka2012-02-0310-3/+45
| | | | | | | | needed to emit a 64-bit gp-relative relocation entry. Make changes necessary for emitting jump tables which have entries with directive .gpdword. This patch does not implement the parts needed for direct object emission or JIT. llvm-svn: 149668
* Incorporate suggestions Chad, Jakob and Evan's suggestions on r149957.Lang Hames2012-02-031-22/+33
| | | | llvm-svn: 149655
* Narrow test further. Make bot and test happy.Jim Grosbach2012-02-031-1/+3
| | | | llvm-svn: 149650
* Tidy up. Trailing whitespace.Jim Grosbach2012-02-031-55/+55
| | | | llvm-svn: 149649
* Restrict InstCombine from converting varargs to or from fixed args.Jim Grosbach2012-02-031-0/+7
| | | | | | More targetted fix replacing d0e277d272d517ca1cda368267d199f0da7cad95. llvm-svn: 149648
* Revert "Disable InstCombine unsafe folding bitcasts of calls w/ varargs."Jim Grosbach2012-02-031-5/+14
| | | | | | This reverts commit d0e277d272d517ca1cda368267d199f0da7cad95. llvm-svn: 149647
* Require non-NULL register masks.Jakob Stoklund Olesen2012-02-024-11/+5
| | | | | | | It doesn't seem worthwhile to give meaning to a NULL register mask pointer. It complicates all the code using register mask operands. llvm-svn: 149646
* Add pseudo-registers for pairs, triples, and quads of D registers.Jakob Stoklund Olesen2012-02-021-15/+70
| | | | | | | | | | | | | | | | | | | | | | | | | | | NEON loads and stores accept single and double spaced pairs, triples, and quads of D registers. This patch adds new register classes to accurately model those constraints: Dn, Dn+1 Dn, Dn+2 ---------------------- DPair DPairSpc DTriple DTripleSpc DQuad DQuadSpc Also extend the existing QQ and QQQQ register classes to contains all Q pairs and quads instead of just the aligned ones. These new register classes will make it possible to accurately model constraints on NEON loads and stores, and we can get rid of all the NEON pseudo-instructions. The late scheduler will be able to accurately model instruction dependencies from the explicit operands. This more than doubles the number of ARM registers, but the backend passes are quite good at handling this. The llc -O0 compile time only regresses by 1.5%. Future work on register mask operands will recover this regression. llvm-svn: 149640
* BBVectorize: Simplify code, no functionality change.Benjamin Kramer2012-02-021-9/+3
| | | | | | Also silences warnings about bodyless for loops. llvm-svn: 149612
* Minor changes from review.Hal Finkel2012-02-021-19/+17
| | | | | | As suggested by Nick Lewycky, the tree traversal queues have been changed to SmallVectors and the associated loops have been rotated. Also, an 80-col violation was fixed. llvm-svn: 149607
* Minor change in signature of the getZeroVector() Elena Demikhovsky2012-02-021-30/+21
| | | | llvm-svn: 149601
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