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* [ARM] Support fixup for Thumb2 modified immediatePeter Smith2017-06-054-3/+47
| | | | | | | | | | | | | | | | | | | | | | | | | | | This change adds a new fixup fixup_t2_so_imm for the t2_so_imm_asmoperand "T2SOImm". The fixup permits code such as: .L1: sub r3, r3, #.L2 - .L1 .L2: to assemble in Thumb2 as well as in ARM state. The operand predicate isT2SOImm() explicitly doesn't match expressions containing :upper16: and :lower16: as expressions with these operators must match the movt and movw instructions. The test mov r0, foo2 in thumb2-diagnostics is moved to a new file as the fixup delays the error message till after the assembler has quit due to the other errors. As the mov instruction shares the t2_so_imm_asmoperand mov instructions with a non constant expression now match t2MOVi rather than t2MOVi16 so the error message is slightly different. Fixes PR28647 Differential Revision: https://reviews.llvm.org/D33492 llvm-svn: 304702
* [InstCombine] Fix extractelement use before defSven van Haastregt2017-06-051-1/+1
| | | | | | | | | | | | This fixes a bug that can cause extractelements with operands that haven't been defined yet to be inserted at a wrong point when optimising insertelements. Patch by Karl Hylen. Differential Revision: https://reviews.llvm.org/D33449 llvm-svn: 304701
* Revert "[sanitizer-coverage] one more flavor of coverage: ↵Renato Golin2017-06-051-43/+9
| | | | | | | | -fsanitize-coverage=inline-8bit-counters. Experimental so far, not documenting yet." This reverts commit r304630, as it broke ARM/AArch64 bots for 2 days. llvm-svn: 304698
* [AMDGPU] Fix SIFoldOperands crash with clampStanislav Mekhanoshin2017-06-051-1/+2
| | | | | | | | | Fixes bug #33302. Pass did not account that Src1 of max instruction can be an immediate. Differential Revision: https://reviews.llvm.org/D33884 llvm-svn: 304696
* [InstSimplify] Use llvm::all_of instead of a manual loop. NFCCraig Topper2017-06-041-3/+2
| | | | llvm-svn: 304692
* IR: When creating a global variable, assert that its type is valid.Peter Collingbourne2017-06-041-0/+4
| | | | llvm-svn: 304690
* [X86][SSE] Change BUILD_VECTOR interleaving ordering to improve ↵Simon Pilgrim2017-06-041-18/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | coalescing/combine opportunities We currently generate BUILD_VECTOR as a tree of UNPCKL shuffles of the same type: e.g. for v4f32: Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0> : unpcklps 1, 3 ==> Y: <?, ?, 3, 1> Step 2: unpcklps X, Y ==> <3, 2, 1, 0> The issue is because we are not placing sequential vector elements together early enough, we fail to recognise many combinable patterns - consecutive scalar loads, extractions etc. Instead, this patch unpacks progressively larger sequential vector elements together: e.g. for v4f32: Step 1: unpcklps 0, 2 ==> X: <?, ?, 1, 0> : unpcklps 1, 3 ==> Y: <?, ?, 3, 2> Step 2: unpcklpd X, Y ==> <3, 2, 1, 0> This does mean that we are creating UNPCKL shuffle of different value types, but the relevant combines that benefit from this are quite capable of handling the additional BITCASTs that are now included in the shuffle tree. Differential Revision: https://reviews.llvm.org/D33864 llvm-svn: 304688
* [LV] Make scalarizeInstruction() non-virtual. NFC.Ayal Zaks2017-06-041-2/+1
| | | | | | | | | | Following the request made in https://reviews.llvm.org/D32871, scalarizeInstruction() which is no longer overridden by InnerLoopUnroller is hereby made non-virtual in InnerLoopVectorizer. Should have been part of r297580 originally. llvm-svn: 304685
* [ConstantFolding] Combine an if statement into an earlier one that checked ↵Craig Topper2017-06-041-7/+3
| | | | | | the same condition. NFC llvm-svn: 304681
* [ConstantFolding][X86] Replace an LLVM_FALLTHROUGH with a break because it ↵Craig Topper2017-06-041-1/+2
| | | | | | | | really shouldn't fallthrough. This is actually NFC because the next case starts with the same if statement as this case did. So the result will be the same and it will fallthrough to the end of the switch. But there's no reason to rely on that so we should just break. llvm-svn: 304680
* [ConstantFolding] Properly support constant folding of vector powi ↵Craig Topper2017-06-041-1/+2
| | | | | | intrinsic. The second argument is not a vector so needs special treatment. llvm-svn: 304679
* [PM] Add GVNSink to the pipeline.Davide Italiano2017-06-031-0/+10
| | | | | | | | | With this, the two pipelines should be in sync again (modulo LoopUnswitch, but Chandler is actively working on that). Differential Revision: https://reviews.llvm.org/D33810 llvm-svn: 304671
* ADT: handle special case of ARM environment for SUSESaleem Abdulrasool2017-06-031-0/+4
| | | | | | | SUSE treats "gnueabi" as "gnueabihf" so make sure that we normalise the environment. llvm-svn: 304670
* [InstCombine] Add support for simplifying ctlz/cttz intrinsics based on ↵Craig Topper2017-06-031-5/+1
| | | | | | known bits. llvm-svn: 304669
* [ConstantFolding] Fix constant folding for vector cttz and ctlz intrinsics ↵Craig Topper2017-06-031-0/+7
| | | | | | to understand that the second argument is still a scalar. llvm-svn: 304668
* [AMDGPU] Untangle SDWA pass from SIShrinkInstructionsStanislav Mekhanoshin2017-06-032-26/+67
| | | | | | | | | | | | Remove dependency of SDWA pass on SIShrinkInstructions. The goal is to move SDWA even higher in the stack to avoid second run of MachineLICM, MachineCSE and SIFoldOperands. Also added handling to preserve original src modifiers. Differential Revision: https://reviews.llvm.org/D33860 llvm-svn: 304665
* [X86][SSE] Add SCALAR_TO_VECTOR(PEXTRW/PEXTRB) support to faux shuffle combiningSimon Pilgrim2017-06-031-9/+31
| | | | | | Generalized existing SCALAR_TO_VECTOR(EXTRACT_VECTOR_ELT) code to support AssertZext + PEXTRW/PEXTRB cases as well. llvm-svn: 304659
* [LazyValueInfo] Use Type::getIntegerBitWidth instead of casting to ↵Craig Topper2017-06-031-2/+1
| | | | | | IntegerType to call getBitWidth. NFC llvm-svn: 304656
* [LazyValueInfo] Make solveBlockValueCast take a CastInst* instead of ↵Craig Topper2017-06-031-18/+18
| | | | | | Instruction*. Makes getOpcode return the appropriate enum without a cast. NFC llvm-svn: 304655
* Added LLVM_FALLTHROUGH to address warning: this statement may fall through. NFC.Galina Kistanova2017-06-031-0/+1
| | | | llvm-svn: 304638
* Added LLVM_FALLTHROUGH to address warning: this statement may fall through. NFC.Galina Kistanova2017-06-031-0/+1
| | | | llvm-svn: 304637
* Added LLVM_FALLTHROUGH to address warning: this statement may fall through. NFC.Galina Kistanova2017-06-032-0/+3
| | | | llvm-svn: 304636
* Added LLVM_FALLTHROUGH to address warning: this statement may fall through. NFC.Galina Kistanova2017-06-032-0/+3
| | | | llvm-svn: 304635
* [WebAssembly] Refactor WasmObjectWriter::writeObjectSam Clegg2017-06-031-402/+483
| | | | | | | | | | The size of this function was getting a little out of. control. Split code for writing each section type into seperate functions. Differential Revision: https://reviews.llvm.org/D33792 llvm-svn: 304634
* [sanitizer-coverage] one more flavor of coverage: ↵Kostya Serebryany2017-06-031-9/+43
| | | | | | -fsanitize-coverage=inline-8bit-counters. Experimental so far, not documenting yet. llvm-svn: 304630
* AMDGPU/GlobalISel: Mark 1-bit integer constants as legalTom Stellard2017-06-031-0/+5
| | | | | | | | | | | | | | | | Summary: These are mostly legal, but will probably need special lowering for some cases. Reviewers: arsenm Reviewed By: arsenm Subscribers: kzhuravl, wdng, nhaehnle, yaxunl, rovka, kristof.beyls, igorb, dstuttard, tpr, llvm-commits, t-tye Differential Revision: https://reviews.llvm.org/D33791 llvm-svn: 304628
* [CodeGen] Fix Windows builds which treat warnings as errors, broken in r304621.Eugene Zelenko2017-06-031-1/+1
| | | | llvm-svn: 304627
* Revert "[CFI] Remove LinkerSubsectionsViaSymbols."Evgeniy Stepanov2017-06-031-12/+23
| | | | | | This reverts commit r304582: breaks cfi-devirt :: anon-namespace.cpp on Darwin. llvm-svn: 304626
* [AMDGPU] Preserve operand order in SIFoldOperandsStanislav Mekhanoshin2017-06-031-3/+18
| | | | | | | | | SIFoldOperands can commute operands even if no folding was done. This change is to preserve IR is no folding was done. Differential Revision: https://reviews.llvm.org/D33802 llvm-svn: 304625
* [PDB] Fix use after free.Zachary Turner2017-06-039-51/+59
| | | | | | | | | | | | | | | | | | | | | | | Previously MappedBlockStream owned its own BumpPtrAllocator that it would allocate from when a read crossed a block boundary. This way it could still return the user a contiguous buffer of the requested size. However, It's not uncommon to open a stream, read some stuff, close it, and then save the information for later. After all, since the entire file is mapped into memory, the data should always be available as long as the file is open. Of course, the exception to this is when the data isn't *in* the file, but rather in some buffer that we temporarily allocated to present this contiguous view. And this buffer would get destroyed as soon as the strema was closed. The fix here is to force the user to specify the allocator, this way it can provide an allocator that has whatever lifetime it chooses. Differential Revision: https://reviews.llvm.org/D33858 llvm-svn: 304623
* LiveRegUnits: Port recent LivePhysRegs bugfixesMatthias Braun2017-06-032-27/+32
| | | | | | | | Adjust code to look more like the code in LivePhysRegs and port over the fix for LivePhysRegs from r304001 and adapt to the new CSR management in MachineRegisterInfo. llvm-svn: 304622
* [CodeGen] Fix some Clang-tidy modernize-use-using and Include What You Use ↵Eugene Zelenko2017-06-031-59/+62
| | | | | | warnings; other minor fixes (NFC). llvm-svn: 304621
* [AMDGPU] V_DIV_FIXUP_F16 is not a commutable operationStanislav Mekhanoshin2017-06-031-1/+2
| | | | | | Differential Revision: https://reviews.llvm.org/D33808 llvm-svn: 304619
* [SLP] Improve comments and naming of functions/variables/members, NFC.Alexey Bataev2017-06-031-91/+59
| | | | | | | | | Fixed some comments, added an additional description of the algorithms, improved readability of the code. Differential revision: https://reviews.llvm.org/D33320 llvm-svn: 304616
* [x86] simplify code for vector icmp pred transforms; NFCISanjay Patel2017-06-021-31/+19
| | | | | | Organizing by transform is smaller and easier to read than a squashed switch with fall-throughs. llvm-svn: 304611
* [sanitizer-coverage] refactor the code to make it easier to add more ↵Kostya Serebryany2017-06-021-55/+74
| | | | | | sections in future. NFC llvm-svn: 304610
* Revert "[SLP] Improve comments and naming of functions/variables/members, NFC."Alexey Bataev2017-06-021-59/+91
| | | | | | This reverts commit 6e311de8b907aa20da9a1a13ab07c3ce2ef4068a. llvm-svn: 304609
* [Statepoint] Be consistent about using deopt naming [NFCI]Philip Reames2017-06-022-4/+4
| | | | | | We'd called this "vm state" in the early days, but have long since standardized on calling it "deopt" in line with the operand bundle tag. Fix a few cases we'd missed. llvm-svn: 304607
* RegisterScavenging: Add ScavengerTest passMatthias Braun2017-06-021-1/+37
| | | | | | | | | This pass allows to run the register scavenging independently of PrologEpilogInserter to allow targeted testing. Also adds some basic register scavenging tests. llvm-svn: 304606
* [RABasic] Properly update the LiveRegMatrix when LR splitting occurQuentin Colombet2017-06-021-4/+30
| | | | | | | | | | | | | | | | | | | | | | Prior to this patch we used to not touch the LiveRegMatrix while doing live-range splitting. In other words, when live-range splitting was occurring, the LiveRegMatrix was not reflecting the changes. This is generally fine because it means the query to the LiveRegMatrix will be conservately correct. However, when decisions are taken based on what is going to happen on the interferences (e.g., when we spill a register and know that it is going to be available for another one), we might hit an assertion that the color used for the assignment is still in use. This patch makes sure the changes on the live-ranges are properly reflected in the LiveRegMatrix, so the assertions don't break. An alternative could have been to remove the assertion, but it would make the invariants of the code and the general reasoning more complicated in my opnion. http://llvm.org/PR33057 llvm-svn: 304603
* [RABasic] Properly initialize the passQuentin Colombet2017-06-022-10/+18
| | | | | | | Use the initializeXXX method to initialize the RABasic pass in the pipeline. This enables us to take advantage of the .mir infrastructure. llvm-svn: 304602
* Fix debug build test failureXinliang David Li2017-06-021-2/+3
| | | | llvm-svn: 304600
* [PartialInlining] Minor cost anaysis tuningXinliang David Li2017-06-021-9/+56
| | | | | | Also added a test option and 2 cost analysis related tests. llvm-svn: 304599
* FunctionAttrs: Skip it if the effective SCC (ignoring optnone functions) is ↵David Blaikie2017-06-021-0/+4
| | | | | | | | | empty Minor optimization but mostly simplifies my debugging so I'm not dealing with empty SCCNodeSets while investigating issues in this optimization. llvm-svn: 304597
* RegisterScavenging: Move scavenging logic from PEI to RegisterScavenging; NFCMatthias Braun2017-06-022-96/+92
| | | | | | | These parts do not depend on any PrologEpilogInserter logic and therefore better fits RegisterScaveging.cpp. llvm-svn: 304596
* Fix build error on gcc.Zachary Turner2017-06-021-1/+1
| | | | llvm-svn: 304595
* [InlineCost] Enable the new switch cost heuristicJun Bum Lim2017-06-021-76/+56
| | | | | | | | | | | | | | | | | | | | Summary: This is to enable the new switch inline cost heuristic (r301649) by removing the old heuristic as well as the flag itself. In my experiment for LLVM test suite and spec2000/2006, +17.82% performance and 8% code size reduce was observed in spec2000/vertex with O3 LTO in AArch64. No significant code size / performance regression was found in O3/O2/Os. No significant complain was reported from the llvm-dev thread. Reviewers: hans, chandlerc, eraman, haicheng, mcrosier, bmakam, eastig, ddibyend, echristo Reviewed By: echristo Subscribers: javed.absar, kristof.beyls, echristo, aemerson, rengolin, mehdi_amini Differential Revision: https://reviews.llvm.org/D32653 llvm-svn: 304594
* [SLP] Improve comments and naming of functions/variables/members, NFC.Alexey Bataev2017-06-021-91/+59
| | | | | | | | | | | | | | Summary: Fixed some comments, added an additional description of the algorithms, improved readability of the code. Reviewers: anemet Subscribers: llvm-commits, mzolotukhin Differential Revision: https://reviews.llvm.org/D33320 llvm-svn: 304593
* [X86] Correctly broadcast NaN-like integers as float on AVX.Ahmed Bougacha2017-06-021-11/+13
| | | | | | | | | | | | | | | | | | | | | | | | Since r288804, we try to lower build_vectors on AVX using broadcasts of float/double. However, when we broadcast integer values that happen to have a NaN float bitpattern, we lose the NaN payload, thereby changing the integer value being broadcast. This is caused by ConstantFP::get, to which we pass the splat i32 as a float (by bitcasting it using bitsToFloat). ConstantFP::get takes a double parameter, so we end up lossily converting a single-precision NaN to double-precision. Instead, avoid any kinds of conversions by directly building an APFloat from the splatted APInt. Note that this also fixes another piece of code (broadcast of subvectors), that currently isn't susceptible to the same problem. Also note that we could really just use APInt and ConstantInt throughout: the constant pool type doesn't matter much. Still, for consistency, use the appropriate type. llvm-svn: 304590
* Fix build error with clang and gcc.Zachary Turner2017-06-021-2/+2
| | | | llvm-svn: 304589
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