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* Fix more code to work properly with vector operands. Based onDan Gohman2010-03-041-5/+5
| | | | | | a patch my Micah Villmow for PR6465. llvm-svn: 97692
* Teach the pic16 target to recognize pic16-*-* triples.John McCall2010-03-041-1/+2
| | | | llvm-svn: 97691
* inline CannotYetSelectIntrinsic into CannotYetSelect and simplify.Chris Lattner2010-03-041-19/+16
| | | | llvm-svn: 97690
* Fix a logic error. An instruction that has a live physical register def ↵Evan Cheng2010-03-031-2/+5
| | | | | | cannot be CSE'ed, but it *can* be used to replace a common subexpression. llvm-svn: 97688
* Remove PHINodeTraits and use MachineInstrExpressionTrait instead.Evan Cheng2010-03-032-39/+2
| | | | llvm-svn: 97687
* Move MachineInstrExpressionTrait::getHashValue() out of line so it can skip ↵Evan Cheng2010-03-031-0/+45
| | | | | | over only virtual register defs. This matches what isEqual() is doing. llvm-svn: 97680
* Re-apply r97667 but with a little bit of thought put into the patch. This ↵Evan Cheng2010-03-031-65/+3
| | | | | | implements a special DenseMapInfo trait for DenseMap<MachineInstr*> that compare the value of the MachineInstr rather than the pointer value. Since the hashing and equality test functions ignore defs it's useful for doing CSE kind optimization. llvm-svn: 97678
* Modified the asm string of 16-bit Thumb MUL instruction so that it prints:Johnny Chen2010-03-031-1/+1
| | | | | | | | MULS <Rdm>, <Rn>, <Rdm> according to A8.6.105 MUL Encoding T1. llvm-svn: 97675
* Revert 97667. It broke a bunch of tests.Dan Gohman2010-03-031-0/+63
| | | | llvm-svn: 97673
* Fix funky indentation and add comments.Evan Cheng2010-03-031-17/+24
| | | | llvm-svn: 97670
* Move DenseMapInfo for MachineInstr* to MachineInstr.hEvan Cheng2010-03-031-63/+0
| | | | llvm-svn: 97667
* Fix a bug in SelectionDAG's ReplaceAllUsesWith in the case whereDan Gohman2010-03-031-4/+45
| | | | | | | | | | CSE and recursive RAUW calls delete a node from the use list, invalidating the use list iterator. There's currently no known way to reproduce this in an unmodified LLVM, however there's no fundamental reason why a SelectionDAG couldn't be formed which would trigger this case. llvm-svn: 97665
* Machine CSE work in progress. It's doing some CSE now. But implicit def of ↵Evan Cheng2010-03-031-24/+61
| | | | | | physical registers are getting in the way. llvm-svn: 97664
* Add MachineRegisterInfo::hasOneUse and hasOneNonDBGUse.Evan Cheng2010-03-032-6/+16
| | | | llvm-svn: 97663
* Fix PR6444, note still doesn't compile libgcc2 all the way, but fixes that ↵Andrew Lenharth2010-03-031-1/+2
| | | | | | error. May not fix it in an ABI complient way. It wasn't clear what gcc does llvm-svn: 97660
* fix incorrect folding of icmp with undef, PR6481.Chris Lattner2010-03-032-5/+4
| | | | llvm-svn: 97659
* Revert...Bill Wendling2010-03-031-3/+3
| | | | | | | --- Reverse-merging r97592 into '.': U lib/CodeGen/TargetLoweringObjectFileImpl.cpp llvm-svn: 97657
* Added 32-bit Thumb instructions LDRT, LDRBT, LDRHT,,LDRSBT, LDRSHT, STRT, STRBT,Johnny Chen2010-03-031-0/+41
| | | | | | and STRHT for disassembly only. llvm-svn: 97655
* add some of the more obscure predicate types to the Chris Lattner2010-03-031-56/+99
| | | | | | Scope accelerator. llvm-svn: 97652
* speed up scope node processing: if the first element of a scopeChris Lattner2010-03-031-38/+141
| | | | | | | | | | | | | entry we're about to process is obviously going to fail, don't bother pushing a scope only to have it immediately be popped. This avoids a lot of scope stack traffic in common cases. Unfortunately, this requires duplicating some of the predicate dispatch. To avoid duplicating the actual logic I pulled each predicate out to its own static function which gets used in both places. llvm-svn: 97651
* introduce a new SwitchTypeMatcher node (which is analogous toChris Lattner2010-03-031-3/+34
| | | | | | | | SwitchOpcodeMatcher) and have DAGISelMatcherOpt form it. This speeds up selection, particularly for X86 which has lots of variants of instructions with only type differences. llvm-svn: 97645
* Make SCEVExpander and LSR more aggressive about hoisting expressions outDan Gohman2010-03-032-51/+248
| | | | | | of loops. llvm-svn: 97642
* Revert r97580; that's not the right way to fix this.Dan Gohman2010-03-031-121/+31
| | | | llvm-svn: 97639
* Work in progress. Finding some cse now.Evan Cheng2010-03-031-4/+88
| | | | llvm-svn: 97635
* remove nvload and two patterns that use it which are Chris Lattner2010-03-031-23/+0
| | | | | | better done by dag combine. llvm-svn: 97633
* Added 32-bit Thumb instructions t2NOP, t2YIELD, t2WFE, t2WFI, t2SEV, and t2DBGJohnny Chen2010-03-031-0/+28
| | | | | | for disassembly only. llvm-svn: 97632
* Use APInt instead of zext value.Bill Wendling2010-03-031-1/+1
| | | | llvm-svn: 97631
* factor the 'in the default address space' check out to a singleChris Lattner2010-03-031-51/+30
| | | | | | | 'dsload' pattern. tblgen doesn't check patterns to see if they're textually identical. This allows better factoring. llvm-svn: 97630
* factor the 'sign extended from 8 bit' patterns better so Chris Lattner2010-03-033-20/+11
| | | | | | | | that they are not destination type specific. This allows tblgen to factor them and the type check is redundant with what the isel does anyway. llvm-svn: 97629
* - Change MachineInstr::isIdenticalTo to take a new option that determines ↵Evan Cheng2010-03-035-38/+34
| | | | | | | | whether it should skip checking defs or at least virtual register defs. This subsumes part of the TargetInstrInfo::isIdentical functionality. - Eliminate TargetInstrInfo::isIdentical and replace it with produceSameValue. In the default case, produceSameValue just checks whether two machine instructions are identical (except for virtual register defs). But targets may override it to check for unusual cases (e.g. ARM pic loads from constant pools). llvm-svn: 97628
* Add an option to enable machine cse (it's not doing anything yet.Evan Cheng2010-03-031-0/+5
| | | | llvm-svn: 97627
* Eliminate unused instruction classes.Evan Cheng2010-03-031-13/+0
| | | | llvm-svn: 97617
* This test case:Bill Wendling2010-03-032-7/+11
| | | | | | | | | | | | | | | | | | | | | long test(long x) { return (x & 123124) | 3; } Currently compiles to: _test: orl $3, %edi movq %rdi, %rax andq $123127, %rax ret This is because instruction and DAG combiners canonicalize (or (and x, C), D) -> (and (or, D), (C | D)) However, this is only profitable if (C & D) != 0. It gets in the way of the 3-addressification because the input bits are known to be zero. llvm-svn: 97616
* Added 32-bit Thumb instructions t2DMB variants, t2DSB variants, and t2ISBsy forJohnny Chen2010-03-031-0/+60
| | | | | | disassembly only. llvm-svn: 97614
* Add Module functions in place of module providers.Erick Tryzelaar2010-03-023-33/+97
| | | | llvm-svn: 97608
* merge two loops over all nodes in the graph into one.Chris Lattner2010-03-021-57/+41
| | | | llvm-svn: 97606
* eliminate PreprocessForRMW now that isel handles it.Chris Lattner2010-03-021-136/+27
| | | | | | We still preprocess calls and fp return stuff. llvm-svn: 97598
* remove 300 lines of code that is now dead in the MSP430 backendChris Lattner2010-03-021-293/+1
| | | | | | | now that isel handles chains more aggressively. This also allows us to make isLegalToFold non-virtual. llvm-svn: 97597
* Fix some issues in WalkChainUsers dealing with Chris Lattner2010-03-023-56/+39
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | CopyToReg/CopyFromReg/INLINEASM. These are annoying because they have the same opcode before an after isel. Fix this by setting their NodeID to -1 to indicate that they are selected, just like what automatically happens when selecting things that end up being machine nodes. With that done, give IsLegalToFold a new flag that causes it to ignore chains. This lets the HandleMergeInputChains routine be the one place that validates chains after a match is successful, enabling the new hotness in chain processing. This smarter chain processing eliminates the need for "PreprocessRMW" in the X86 and MSP430 backends and enables MSP to start matching it's multiple mem operand instructions more aggressively. I currently #if out the dead code in the X86 backend and MSP backend, I'll remove it for real in a follow-on patch. The testcase changes are: test/CodeGen/X86/sse3.ll: we generate better code test/CodeGen/X86/store_op_load_fold2.ll: PreprocessRMW was miscompiling this before, we now generate correct code Convert it to filecheck while I'm at it. test/CodeGen/MSP430/Inst16mm.ll: Add a testcase for mem/mem folding to make anton happy. :) llvm-svn: 97596
* Added 32-bit Thumb instruction CLREX (Clear-Exclusive) for disassembly only.Johnny Chen2010-03-021-0/+10
| | | | llvm-svn: 97595
* Okay. One last attempt:Bill Wendling2010-03-021-3/+3
| | | | | | Place the LSDA into the TEXT section on Mach-O. This saves space. llvm-svn: 97592
* Rename LLVMUseIteratorRef to LLVMUseRef since we don't refer to iterators in ↵Erick Tryzelaar2010-03-021-7/+10
| | | | | | llvm-c. llvm-svn: 97585
* Removed the extra S from the multiclass def T2I_adde_sube_s_irs as well as fromJohnny Chen2010-03-021-14/+14
| | | | | | | the opc string passed in, since it's a given from the class inheritance of T2sI. The fixed the extra 's' in adcss & sbcss when disassembly printing. llvm-svn: 97582
* run HandleMergeInputChains even if we only have one input chain.Chris Lattner2010-03-021-29/+3
| | | | llvm-svn: 97581
* When expanding an expression such as (A + B + C + D), sort the operandsDan Gohman2010-03-021-31/+121
| | | | | | | by loop depth and emit loop-invariant subexpressions outside of loops. This speeds up MultiSource/Applications/viterbi and others. llvm-svn: 97580
* Swap parameters of isSafeToMove and isSafeToReMat for consistency.Evan Cheng2010-03-025-10/+10
| | | | llvm-svn: 97578
* Fix typo.Evan Cheng2010-03-021-1/+1
| | | | llvm-svn: 97577
* Added 32-bit Thumb instructions: CPS, SDIV, UDIV, SXTB16, SXTAB16, UXTAB16, SEL,Johnny Chen2010-03-022-7/+164
| | | | | | | SMMULR, SMMLAR, SMMLSR, TBB, TBH, and 16-bit Thumb instruction CPS for disassembly only. llvm-svn: 97573
* Fix grammar.Devang Patel2010-03-021-1/+1
| | | | | | Thanks Duncan! llvm-svn: 97572
* AL is an optional mnemonic extension for always, except in IT instructions.Johnny Chen2010-03-024-1/+15
| | | | | | | Add printMandatoryPredicateOperand() PrintMethod for IT predicate printing. Ref: A8.3 Conditional execution llvm-svn: 97571
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