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* [WebAssembl] Implement enough of fast-isel to run the comparison tests.Dan Gohman2016-05-111-98/+389
| | | | llvm-svn: 269203
* Use an emplace_back for consistency, NFCVedant Kumar2016-05-111-1/+1
| | | | llvm-svn: 269199
* [BasicAA] Compare GEP indices based on value (Fix PR27418)Vedant Kumar2016-05-111-1/+1
| | | | | | | | | | | | Equivalent GEP indices with different types are treated as different indices altogether, leading to an incorrect AA result. Fix the issue by comparing indices based on their values. Thanks to Mikael Holmén for reporting the issue! Differential Revision: http://reviews.llvm.org/D19935 llvm-svn: 269197
* [mips][ias] Work around incorrect microMIPS relocation evaluation exposed by ↵Daniel Sanders2016-05-111-0/+5
| | | | | | | | | | | | | | | r268900 microMIPS has a special case that is not correctly implemented in LLVM. If we have a symbol 'foo' which is equivalent to '.text+0x10'. The value of an R_MICROMIPS_LO16 relocation using 'foo' is 'foo+0x11' and not 'foo+0x10'. The in-place addend should therefore be 0x11. Work around this by partially reverting the effect of r268900 by keeping the symbol when the STO_MIPS_MICROMIPS flag is set. This fixes SingleSource/Regression/C/PR640 for microMIPS. llvm-svn: 269196
* [Hexagon] Add a debug option to disable all backend optimizationsKrzysztof Parzyszek2016-05-111-1/+4
| | | | llvm-svn: 269192
* [Hexagon] Use offsets relative to FP+8 in .cfi_offset instructionsKrzysztof Parzyszek2016-05-111-5/+19
| | | | | | | | When generating .cfi_offset instructions, make sure that the offset is calculated with respect to the register used to define the CFA (which is currently always FP+8). llvm-svn: 269191
* NFC. Introduce Value::isPointerDereferenceableArtur Pilipenko2016-05-112-12/+28
| | | | | | | | | | Extract a part of isDereferenceableAndAlignedPointer functionality to Value: Reviewed By: hfinkel, sanjoy Differential Revision: http://reviews.llvm.org/D17611 llvm-svn: 269190
* Merge two unreachable cases.Rafael Espindola2016-05-111-2/+1
| | | | llvm-svn: 269189
* Refactor duplicated check for valid declaration linkage. NFC.Rafael Espindola2016-05-112-4/+4
| | | | llvm-svn: 269184
* Delete duplicated verifier test.Rafael Espindola2016-05-111-5/+0
| | | | | | Also add unittest to show we still detect the errors. llvm-svn: 269182
* [mips][ias] Fix missing header that should have been in r269179Daniel Sanders2016-05-111-0/+1
| | | | llvm-svn: 269180
* [mips][ias] Fix N32 and N64 .cprestore directive when inside .set noat region.Daniel Sanders2016-05-113-22/+28
| | | | | | | | | | | | | | | | | | Summary: r268058 unintentionally made the retrieval of the current assembler temporary unconditional. This was fine for the existing tests but it broke the cases where the assembler temporary is not needed (N32/N64 or not PIC) and is unavailable due to a '.set noat' directive. This fixes FreeBSD's libc. Reviewers: emaste, sdardis, seanbruno Subscribers: dsanders, emaste, sdardis, llvm-commits Differential Revision: http://reviews.llvm.org/D20093 llvm-svn: 269179
* Try to fix a msvc warning.Rafael Espindola2016-05-111-0/+1
| | | | llvm-svn: 269178
* [mips][microMIPS] Implement CFC*, CTC* and LDC* instructionsHrvoje Varga2016-05-1110-8/+190
| | | | | | Differential Revision: http://reviews.llvm.org/D19713 llvm-svn: 269176
* clang-format LLToken.h.Rafael Espindola2016-05-111-225/+339
| | | | | | | Having it be special is quite annoying for being able to just run git-clang-format in patches that change it. llvm-svn: 269175
* [X86][AVX512] Updated shuffle comments instruction macros to split writemask ↵Simon Pilgrim2016-05-111-40/+46
| | | | | | | | instructions. NFC This will make it easier to support the different writemask cases in shuffle comments llvm-svn: 269174
* [mips][micromips] Implement DSBH, DSHD, DSLL, DSLL32, DSLLV, DSRA, DSRA32 ↵Hrvoje Varga2016-05-113-12/+160
| | | | | | | | and DSRAV instructions Differential Revision: http://reviews.llvm.org/D16800 llvm-svn: 269169
* Replace PrintLinkage with getLinkagePrintName. NFC.Rafael Espindola2016-05-111-17/+25
| | | | llvm-svn: 269155
* [AArch64] Fix DAG selection for cmps for fp16 typeWeiming Zhao2016-05-111-0/+1
| | | | | | | | | | | | Summary: When emitting comparison for fp16, in addition to promote the LHS and RHS to fp32, we need to change the VT as well. Reviewers: t.p.northover Subscribers: t.p.northover, aemerson, rengolin, llvm-commits Differential Revision: http://reviews.llvm.org/D19922 llvm-svn: 269151
* Delete mayBeOverridden.Rafael Espindola2016-05-111-1/+1
| | | | | | It is the same as isInterposable which seems to be the preferred name. llvm-svn: 269150
* AMDGPU: Make some instructions convergentMatt Arsenault2016-05-111-1/+7
| | | | llvm-svn: 269147
* [PGO] Use WeakAny linkage for __llvm_profile_raw_versionRong Xu2016-05-111-1/+1
| | | | | | | Use WeakAny linkage instead of LinkOnceAny, as the symbol can be removed with LinkOnceAny in O2 (not referenced). llvm-svn: 269146
* AMDGPU: Change private_element_size to 4Matt Arsenault2016-05-111-1/+1
| | | | llvm-svn: 269145
* SDAG: Implement Select instead of SelectImpl in X86Justin Bogner2016-05-101-31/+26
| | | | | | | This is part of the work to have Select return void instead of an SDNode *, which is in turn part of llvm.org/pr26808. llvm-svn: 269144
* [libFuzzer] add a driver file to use AFL on LLVMFuzzerTestOneInputKostya Serebryany2016-05-101-0/+82
| | | | llvm-svn: 269141
* [libfuzzer] Refactoring coverage state-management code.Mike Aizatsky2016-05-104-116/+206
| | | | | | | | | It is now less state-dependent and will allow easier comparing of coverages of different units. Differential Revision: http://reviews.llvm.org/D20085 llvm-svn: 269140
* Revert r269131Easwaran Raman2016-05-103-49/+3
| | | | llvm-svn: 269138
* Propagate branch metadata when some branch probability is missing.Dehao Chen2016-05-101-5/+13
| | | | | | | | | | | | Summary: In sample profile, some branches may have profile missing due to profile inaccuracy. We want existing branch probability still valid after propagation. Reviewers: hfinkel, davidxl, spatel Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D19948 llvm-svn: 269137
* SDAG: Make SelectCodeCommon return voidJustin Bogner2016-05-101-25/+41
| | | | | | | | | | | This means SelectCode unconditionally returns nullptr now. I'll follow up with a change to make that return void as well, but it seems best to keep that one very mechanical. This is part of the work to have Select return void instead of an SDNode *, which is in turn part of llvm.org/pr26808. llvm-svn: 269136
* AArch64: allow vN to represent 64-bit registers in inline asm.Tim Northover2016-05-101-3/+8
| | | | | | | | Unlike xN/wN, the size of vN is genuinely ambiguous in the assembly, so we should try to infer what was intended from the type. But only down to 64-bits (vN can never represent sN, hN or bN). llvm-svn: 269132
* Reapply r266477 and r266488Easwaran Raman2016-05-103-3/+49
| | | | llvm-svn: 269131
* [PM]: port IR based profUse pass to new pass managerXinliang David Li2016-05-102-10/+33
| | | | llvm-svn: 269129
* Revert "MemCpyOpt: combine local load/store sequences into memcpy."Tim Northover2016-05-101-222/+48
| | | | | | | This reverts commit r269125. It was in my tree when I ran "git svn dcommit". It's really still under review. llvm-svn: 269127
* ARM: report an error when attempting to target a misalgined BLXTim Northover2016-05-101-3/+12
| | | | | | | The CodeGen problem was fixed in r269101, but we still miscompiled assembly that tried the same thing. llvm-svn: 269126
* MemCpyOpt: combine local load/store sequences into memcpy.Tim Northover2016-05-101-48/+222
| | | | | | | | Sort of the BB-local equivalent to idiom-recognizer: if we have a basic-block that really implements a memcpy operation, backends can benefit from seeing this. llvm-svn: 269125
* Loop unroller: set thresholds for optsize and minsize functions to zeroHans Wennborg2016-05-101-2/+2
| | | | | | | | | | | | | | | Before r268509, Clang would disable the loop unroll pass when optimizing for size. That commit enabled it to be able to support unroll pragmas in -Os builds. However, this regressed binary size in one of Chromium's DLLs with ~100 KB. This restores the original behaviour of no unrolling at -Os, but doing it in LLVM instead of Clang makes more sense, and also allows the pragmas to keep working. Differential revision: http://reviews.llvm.org/D20115 llvm-svn: 269124
* Enable loopreroll for sext of loop control only IVLawrence Hu2016-05-101-12/+33
| | | | | | | | | This patch extend loopreroll to allow the instruction chain of loop control only IV has sext. Differential Revision: http://reviews.llvm.org/D19820 llvm-svn: 269121
* SDAG: Avoid relying on the return value of SelectCode in SystemZ. NFCJustin Bogner2016-05-101-12/+20
| | | | | | | | | | This is a bit of a spot fix for now. I'll try to fix this up more comprehensively soon. This is part of the work to have Select return void instead of an SDNode *, which is in turn part of llvm.org/pr26808. llvm-svn: 269120
* Revert r26084: Enable loopreroll for sext of loop control only IVLawrence Hu2016-05-101-33/+12
| | | | llvm-svn: 269119
* [X86] Properly check that EAX is dead when copying EFLAGS.Quentin Colombet2016-05-101-4/+9
| | | | | | | | | | | | This fixes a bug introduced in r267623, where we got smarter and avoided to save EAX before using it. However, we failed to check if any of the subregister of EAX were alive and thus, missed cases where we have to save EAX before using it. The problem may happen on every X86/i386/... platform. This fixes llvm.org/PR27624 llvm-svn: 269115
* [InstSimplify] use computeKnownBits on shift amount operandsSanjay Patel2016-05-101-0/+16
| | | | | | | | | | | | | | Do simplifications common to all shift instructions based on the amount shifted: 1. If the shift amount is known larger than the bitwidth, the result is undefined. 2. If the valid bits of the shift amount are all known to be 0, it's a shift by zero, so the shift operand is the result. Note that we could generalize the shift-by-zero transform into a shift-by-constant if all of the valid bits in the shift amount are known, but that would have to be done in InstCombine rather than here because it would mean we need to create a new shift instruction. Differential Revision: http://reviews.llvm.org/D19874 llvm-svn: 269114
* SDAG: Avoid relying on the return value of SelectCode in Hexagon. NFCJustin Bogner2016-05-101-3/+11
| | | | | | | | | | This is a bit of a spot fix for now. I'll try to fix this up more comprehensively soon. This is part of the work to have Select return void instead of an SDNode *, which is in turn part of llvm.org/pr26808. llvm-svn: 269112
* Cloning: Clean up the interface to the CloneFunction function.Peter Collingbourne2016-05-103-33/+14
| | | | | | | | | | | | | | | | | | | | | Remove the ModuleLevelChanges argument, and the ability to create new subprograms for cloned functions. The latter was added without review in r203662, but it has no in-tree clients (all non-test callers pass false for ModuleLevelChanges [1], so it isn't reachable outside of tests). It also isn't clear that adding a duplicate subprogram to the compile unit is always the right thing to do when cloning a function within a module. If this functionality comes back it should be accompanied with a more concrete use case. Furthermore, all in-tree clients add the returned function to the module. Since that's pretty much the only sensible thing you can do with the function, just do that in CloneFunction. [1] http://llvm-cs.pcc.me.uk/lib/Transforms/Utils/CloneFunction.cpp/rCloneFunction Differential Revision: http://reviews.llvm.org/D18628 llvm-svn: 269110
* [InstCombine] Fold icmp ugt/ult (udiv i32 C2, X), C1.Chad Rosier2016-05-101-3/+21
| | | | | | | | | | This patch adds support for two optimizations: icmp ugt (udiv C2, X), C1 -> icmp ule X, C2/(C1+1) icmp ult (udiv C2, X), C1 -> icmp ugt X, C2/C1 Differential Revision: http://reviews.llvm.org/D20123 llvm-svn: 269109
* ScheduleDAGInstrs: Comment on why subreg defs are not seen as uses; NFCMatthias Braun2016-05-101-0/+4
| | | | | | | | Usually subregister definitions are consider uses of the remaining lanes that did not get defined. Add a comment why the code in ScheduleDAGInstrs does not add use dependencies regardless. llvm-svn: 269107
* [SystemZ] Add support for additional branch extended mnemonicsKit Barton2016-05-101-15/+22
| | | | | | | | | | | | | Added support for extended mnemonics for the following branch instructions and load/store-on-condition opcodes: BR, LOCR, LOCGR, LOC, LOCG, STOC, STOCG Phabricator: http://reviews.llvm.org/D19729 Committing on behalf of Zhan Liau llvm-svn: 269106
* [SCCP] Partially propagate informations when the input is not fully defined.Davide Italiano2016-05-101-0/+3
| | | | | | | | | | With this patch: %r1 = lshr i64 -1, 4294967296 -> undef Before this patch: %r1 = lshr i64 -1, 4294967296 -> 0 llvm-svn: 269105
* Debug Info: Prevent DW_AT_abstract_origin from being emitted twiceAdrian Prantl2016-05-101-7/+0
| | | | | | | | | | | | for the same subprogram. This fixes a bug where DW_AT_abstract_origin is being emitted twice for the same subprogram if a function is both inlined and emitted in the same translation unit, by restoring the pre-r266446 behavior. http://reviews.llvm.org/D20072 llvm-svn: 269103
* ARM: stop emitting blx instructions for most calls on MachO.Tim Northover2016-05-103-14/+5
| | | | | | | | | | | I'm really not sure why we were in the first place, it's the linker's job to convert between BL/BLX as necessary. Even worse, using BLX left Thumb calls that could be locally resolved completely unencodable since all offsets to BLX are multiples of 4. rdar://26182344 llvm-svn: 269101
* [AMDGPU][NFC] Rename SIInsertNops -> SIDebuggerInsertNopsKonstantin Zhuravlyov2016-05-104-19/+21
| | | | | | Differential Revision: http://reviews.llvm.org/D20117 llvm-svn: 269098
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