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* Remove some more C junk from these files.Richard Smith2014-04-202-16/+6
| | | | llvm-svn: 206721
* Don't provide two different definitions of ModRMDecision, OpcodeDecision, ↵Richard Smith2014-04-203-37/+23
| | | | | | and ContextDecision in different source files (depending on #define magic). llvm-svn: 206720
* Don't define llvm::X86Disassembler::InstructionSpecifier in different ways inRichard Smith2014-04-202-12/+8
| | | | | | different source files. llvm-svn: 206719
* Maybe if I touch this file the buildbots will actually rerun configure like ↵Richard Smith2014-04-201-1/+1
| | | | | | they need to... llvm-svn: 206718
* What year is it! This file has no reason to be written in C, and has doubly noRichard Smith2014-04-205-109/+103
| | | | | | | | | | reason to expose a global symbol 'decodeInstruction' nor to pollute the global scope with a bunch of external linkage entities (some of which conflict with others elsewhere in LLVM). This is just the initial transition to C++; more cleanups to follow. llvm-svn: 206717
* Remove some empty statementsAlp Toker2014-04-196-6/+6
| | | | | | Cleanup only. llvm-svn: 206710
* ProfileData: Remove an extra semicolonJustin Bogner2014-04-191-1/+1
| | | | | | Spotted by Nick Lewycky in review, thanks! llvm-svn: 206708
* Revert "blockfreq: Rewrite BlockFrequencyInfoImpl"Duncan P. N. Exon Smith2014-04-194-948/+5
| | | | | | This reverts commit r206704, as expected. llvm-svn: 206707
* Reapply "blockfreq: Rewrite BlockFrequencyInfoImpl"Duncan P. N. Exon Smith2014-04-194-5/+948
| | | | | | | | | | | | | | | | | | | | | This reverts commit r206677, reapplying my BlockFrequencyInfo rewrite. I've done a careful audit, added some asserts, and fixed a couple of bugs (unfortunately, they were in unlikely code paths). There's a small chance that this will appease the failing bots [1][2]. (If so, great!) If not, I have a follow-up commit ready that will temporarily add -debug-only=block-freq to the two failing tests, allowing me to compare the code path between what the failing bots and what my machines (and the rest of the bots) are doing. Once I've triggered those builds, I'll revert both commits so the bots go green again. [1]: http://bb.pgr.jp/builders/ninja-x64-msvc-RA-centos6/builds/1816 [2]: http://llvm-amd64.freebsd.your.org/b/builders/clang-i386-freebsd/builds/18445 <rdar://problem/14292693> llvm-svn: 206704
* Patch by Vadim ChugunovYaron Keren2014-04-194-3/+17
| | | | | | | | | | | Win64 stack unwinder gets confused when execution flow "falls through" after a call to 'noreturn' function. This fixes the "missing epilogue" problem by emitting a trap instruction for IR 'unreachable' on x86_x64-pc-windows. A secondary use for it would be for anyone wanting to make double-sure that 'noreturn' functions, indeed, do not return. llvm-svn: 206684
* Patch by Ray Donnelly to print register names instead of numbers.Yaron Keren2014-04-191-4/+11
| | | | | | http://reviews.llvm.org/D3422 llvm-svn: 206683
* Add parens to appease GCC warning.David Blaikie2014-04-191-4/+4
| | | | llvm-svn: 206678
* Revert "blockfreq: Rewrite BlockFrequencyInfoImpl" (#2)Duncan P. N. Exon Smith2014-04-194-949/+5
| | | | | | | | | | | This reverts commit r206666, as planned. Still stumped on why the bots are failing. Sanitizer bots haven't turned anything up. If anyone can help me debug either of the failures (referenced in r206666) I'll owe them a beer. (In the meantime, I'll be auditing my patch for undefined behaviour.) llvm-svn: 206677
* OnDiskHashTable: Audit types and use offset_type consistentlyJustin Bogner2014-04-191-4/+4
| | | | llvm-svn: 206675
* Check whether functions have any lines associated before emitting coverage ↵Nick Lewycky2014-04-181-0/+17
| | | | | | info for them. This isn't just a size/time saving, gcov may crash on these. llvm-svn: 206671
* Change the ARM assembler to require a :lower16: or :upper16 on non-constantKevin Enderby2014-04-182-5/+29
| | | | | | | | | | | | | | | | | | | | | | expressions for mov instructions instead of silently truncating by default. For the ARM assembler, we want to avoid misleadingly allowing something like "mov r0, <symbol>" especially when we turn it into a movw and the expression <symbol> does not have a :lower16: or :upper16" as part of the expression. We don't want the behavior of silently truncating, which can be unexpected and lead to bugs that are difficult to find since this is an easy mistake to make. This does change the previous behavior of llvm but actually matches an older gnu assembler that would not allow this but print less useful errors of like “invalid constant (0x927c0) after fixup” and “unsupported relocation on symbol foo”. The error for llvm is "immediate expression for mov requires :lower16: or :upper16" with correct location information on the operand as shown in the added test cases. rdar://12342160 llvm-svn: 206669
* Reapply "blockfreq: Rewrite BlockFrequencyInfoImpl" (#2)Duncan P. N. Exon Smith2014-04-184-5/+949
| | | | | | | | | | | | | | | | | | | This reverts commit r206628, reapplying r206622 (and r206626). Two tests are failing only on buildbots [1][2]: i.e., I can't reproduce on Darwin, and Chandler can't reproduce on Linux. Asan and valgrind don't tell us anything, but we're hoping the msan bot will catch it. So, I'm applying this again to get more feedback from the bots. I'll leave it in long enough to trigger builds in at least the sanitizer buildbots (it was failing for reasons unrelated to my commit last time it was in), and hopefully a few others.... and then I expect to revert a third time. [1]: http://bb.pgr.jp/builders/ninja-x64-msvc-RA-centos6/builds/1816 [2]: http://llvm-amd64.freebsd.your.org/b/builders/clang-i386-freebsd/builds/18445 llvm-svn: 206666
* [llvm-symbolizer] Print file/line for a PC even if there is no DIE ↵Alexey Samsonov2014-04-181-9/+20
| | | | | | | | | | | describing it. This is important for symbolizing executables with debug info in unavailable .dwo files. Even if all DIE entries are missing, we can still symbolize an address: function name can be fetched from symbol table, and file/line info can be fetched from line table. llvm-svn: 206665
* ProfileData: Don't forward declare ComputeHash and make it static inlineJustin Bogner2014-04-182-1/+6
| | | | llvm-svn: 206663
* Compress debug sections only when beneficial.David Blaikie2014-04-181-2/+6
| | | | | | | | | Both ZLIB and the debug info compressed section header ("ZLIB" + the size of the uncompressed data) take some constant overhead so in some cases the compressed data is actually larger than the uncompressed data. In these cases, just don't compress or rename the section at all. llvm-svn: 206659
* ProfileData: Add support for the indexed instrprof formatJustin Bogner2014-04-184-17/+245
| | | | | | | | This adds support for an indexed instrumentation based profiling format, which is just a small header and an on disk hash table. This format will be used by clang's -fprofile-instr-use= for PGO. llvm-svn: 206656
* [DWARF parser] Turn DILineInfo into a struct.Alexey Samsonov2014-04-181-54/+46
| | | | | | | | | | Immutable DILineInfo doesn't bring any benefits and complicates code. Also, use std::string instead of SmallString<16> for file and function names - their length can vary significantly. No functionality change. llvm-svn: 206654
* Update the fragments of symbols in compressed sections.David Blaikie2014-04-181-0/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | While unnamed relocations are already cached in side tables in ELFObjectWriter::RecordRelocation, symbols still need their fragments updated to refer to the newly compressed fragment (even if that fragment isn't big enough to fit the offset). Even though we only create temporary symbols in debug info sections this comes up in 32 bit builds where even temporary symbols in mergeable sections (such as debug_str) have to be emitted as named symbols. I tried a few other ways to do this but they all didn't work for various reasons: 1) Canonicalize the MCSymbolData in RecordRelocation, nulling out the Fragment (so it didn't have to be updated by CompressDebugSection). This doesn't work because some code relies on symbols having fragments to indicate that they're defined, I think. 2) Canonicalize the MCSymbolData in RecordRelocation to be "first fragment + absolute offset" so it would be cheaper to just test and update the fragment in CompressDebugSections. This doesn't work because the offset computed in RecordRelocation isn't that of the symbol's fragment, it's the passed in fragment (I haven't figured out what that fragment is - perhaps it's the location where the relocation is to be written). And if the fragment offset has to be computed only for this use we might as well just do it when we need to, in CompressDebugSection. I also added an assert to help catch this a bit more clearly, even though it is UB. The test case improvements would either assert fail and/or valgrind vail without the fix, even if they wouldn't necessarily fail the FileCheck output. llvm-svn: 206653
* [ARM64] Ports the Cortex-A53 Machine Model description from AArch64.Chad Rosier2014-04-183-4/+135
| | | | | | | | | | | | | Summary: This port includes the rudimentary latencies that were provided for the Cortex-A53 Machine Model in the AArch64 backend. It also changes the SchedAlias for COPY in the Cyclone model to an explicit WriteRes mapping to avoid conflicts in other subtargets. Differential Revision: http://reviews.llvm.org/D3427 Patch by Dave Estes <cestes@codeaurora.org>! llvm-svn: 206652
* [LCG] Fix the bugs that Ben pointed out in code review (and the MSan botChandler Carruth2014-04-181-3/+7
| | | | | | | caught). Sad that we don't have warnings for these things, but bleh, no idea how to fix that. llvm-svn: 206646
* [DWARF parser] Respect address ranges specified in compile unit DIE.Alexey Samsonov2014-04-181-0/+7
| | | | | | | | | | | When address ranges for compile unit are specified in compile unit DIE itself, there is no need to collect ranges from children subprogram DIEs. This change speeds up llvm-symbolizer on Clang-produced binaries with full debug info. For instance, symbolizing a first address in a 1Gb binary is now 2x faster (1s vs. 2s). llvm-svn: 206641
* Remove a couple of redundant copies of SmallVector::operator==.Benjamin Kramer2014-04-182-29/+3
| | | | | | No functionality change. llvm-svn: 206635
* [X86] Improve buildFromShuffleMostly for AVXAdam Nemet2014-04-181-6/+39
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For a 256-bit BUILD_VECTOR consisting mostly of shuffles of 256-bit vectors, both the BUILD_VECTOR and its operands may need to be legalized in multiple steps. Consider: (v8f32 (BUILD_VECTOR (extract_vector_elt (v8f32 %vreg0,) Constant<1>), (extract_vector_elt %vreg0, Constant<2>), (extract_vector_elt %vreg0, Constant<3>), (extract_vector_elt %vreg0, Constant<4>), (extract_vector_elt %vreg0, Constant<5>), (extract_vector_elt %vreg0, Constant<6>), (extract_vector_elt %vreg0, Constant<7>), %vreg1)) a. We can't build a 256-bit vector efficiently so, we need to split it into two 128-bit vecs and combine them with VINSERTX128. b. Operands like (extract_vector_elt (v8f32 %vreg0), Constant<7>) needs to be split into a VEXTRACTX128 and a further extract_vector_elt from the resulting 128-bit vector. c. The extract_vector_elt from b. is lowered into a shuffle to the first element and a movss. Depending on the order in which we legalize the BUILD_VECTOR and its operands[1], buildFromShuffleMostly may be faced with: (v4f32 (BUILD_VECTOR (extract_vector_elt (vector_shuffle<1,u,u,u> (extract_subvector %vreg0, Constant<4>), undef), Constant<0>), (extract_vector_elt (vector_shuffle<2,u,u,u> (extract_subvector %vreg0, Constant<4>), undef), Constant<0>), (extract_vector_elt (vector_shuffle<3,u,u,u> (extract_subvector %vreg0, Constant<4>), undef), Constant<0>), %vreg1)) In order to figure out the underlying vector and their identity we need to see through the shuffles. [1] Note that the order in which operations and their operands are legalized is only guaranteed in the first iteration of LegalizeDAG. Fixes <rdar://problem/16296956> llvm-svn: 206634
* DebugInfo: Remove some initializer lists to make MSVC happy again.Benjamin Kramer2014-04-181-3/+3
| | | | llvm-svn: 206632
* Add range access to MCAssembler's symbol collection.David Blaikie2014-04-184-45/+33
| | | | llvm-svn: 206631
* Revert "blockfreq: Rewrite BlockFrequencyInfoImpl" (#2)Duncan P. N. Exon Smith2014-04-184-949/+5
| | | | | | | | | This reverts commit r206622 and the MSVC fixup in r206626. Apparently the remotely failing tests are still failing, despite my attempt to fix the nondeterminism in r206621. llvm-svn: 206628
* Fixing MSVC after r206622?Duncan P. N. Exon Smith2014-04-181-0/+2
| | | | llvm-svn: 206626
* Better comments to explain buffered/unbuffered processor resources.Andrew Trick2014-04-181-4/+8
| | | | llvm-svn: 206625
* [DWARF parser] Refactor fetching DIE address ranges.Alexey Samsonov2014-04-187-64/+72
| | | | | | | | | | Add a helper method to get address ranges specified in a DIE (either by DW_AT_low_pc/DW_AT_high_pc, or by DW_AT_ranges). Use it to untangle and simplify the code. No functionality change. llvm-svn: 206624
* Reapply "blockfreq: Rewrite BlockFrequencyInfoImpl"Duncan P. N. Exon Smith2014-04-184-5/+947
| | | | | | | | | | | | | | This reverts commit r206556, effectively reapplying commit r206548 and its fixups in r206549 and r206550. In an intervening commit I've added target triples to the tests that were failing remotely [1] (but passing locally). I'm hoping the mystery is solved? I'll revert this again if the tests are still failing remotely. [1]: http://bb.pgr.jp/builders/ninja-x64-msvc-RA-centos6/builds/1816 llvm-svn: 206622
* ARM64: disable generation of .loh directives outside MachO.Tim Northover2014-04-181-1/+2
| | | | | | Part of PR19455. llvm-svn: 206611
* ARM64: don't emit .subsections_via_symbols on ELF.Tim Northover2014-04-181-7/+9
| | | | | | Part of PR19455. llvm-svn: 206610
* ARM64: add extra NEG pattern.Tim Northover2014-04-181-0/+2
| | | | llvm-svn: 206609
* AArch64/ARM64: add non-scalar lowering for more FCVT operations.Tim Northover2014-04-182-2/+12
| | | | llvm-svn: 206591
* AArch64/ARM64: improve spotting of EXT instructions from VECTOR_SHUFFLE.Tim Northover2014-04-181-5/+7
| | | | | | | We couldn't cope if the first mask element was UNDEF before, which isn't ideal. llvm-svn: 206588
* [msan] Add -msan-instrumentation-with-call-threshold.Evgeniy Stepanov2014-04-181-42/+110
| | | | | | | | | This flag replaces inline instrumentation for checks and origin stores with calls into MSan runtime library. This is a workaround for PR17409. Disabled by default. llvm-svn: 206585
* [LCG] Remove all of the complexity stemming from supporting copying.Chandler Carruth2014-04-181-42/+21
| | | | | | | | | | | | | | Reality is that we're never going to copy one of these. Supporting this was becoming a nightmare because nothing even causes it to compile most of the time. Lots of subtle errors built up that wouldn't have been caught by any "normal" testing. Also, make the move assignment actually work rather than the bogus swap implementation that would just infloop if used. As part of that, factor out the graph pointer updates into a helper to share between move construction and move assignment. llvm-svn: 206583
* [LCG] Add support for building persistent and connected SCCs to theChandler Carruth2014-04-181-4/+118
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | LazyCallGraph. This is the start of the whole point of this different abstraction, but it is just the initial bits. Here is a run-down of what's going on here. I'm planning to incorporate some (or all) of this into comments going forward, hopefully with better editing and wording. =] The crux of the problem with the traditional way of building SCCs is that they are ephemeral. The new pass manager however really needs the ability to associate analysis passes and results of analysis passes with SCCs in order to expose these analysis passes to the SCC passes. Making this work is kind-of the whole point of the new pass manager. =] So, when we're building SCCs for the call graph, we actually want to build persistent nodes that stick around and can be reasoned about later. We'd also like the ability to walk the SCC graph in more complex ways than just the traditional postorder traversal of the current CGSCC walk. That means that in addition to being persistent, the SCCs need to be connected into a useful graph structure. However, we still want the SCCs to be formed lazily where possible. These constraints are quite hard to satisfy with the SCC iterator. Also, using that would bypass our ability to actually add data to the nodes of the call graph to facilite implementing the Tarjan walk. So I've re-implemented things in a more direct and embedded way. This immediately makes it easy to get the persistence and connectivity correct, and it also allows leveraging the existing nodes to simplify the algorithm. I've worked somewhat to make this implementation more closely follow the traditional paper's nomenclature and strategy, although it is still a bit obtuse because it isn't recursive, using an explicit stack and a tail call instead, and it is interruptable, resuming each time we need another SCC. The other tricky bit here, and what actually took almost all the time and trials and errors I spent building this, is exactly *what* graph structure to build for the SCCs. The naive thing to build is the call graph in its newly acyclic form. I wrote about 4 versions of this which did precisely this. Inevitably, when I experimented with them across various use cases, they became incredibly awkward. It was all implementable, but it felt like a complete wrong fit. Square peg, round hole. There were two overriding aspects that pushed me in a different direction: 1) We want to discover the SCC graph in a postorder fashion. That means the root node will be the *last* node we find. Using the call-SCC DAG as the graph structure of the SCCs results in an orphaned graph until we discover a root. 2) We will eventually want to walk the SCC graph in parallel, exploring distinct sub-graphs independently, and synchronizing at merge points. This again is not helped by the call-SCC DAG structure. The structure which, quite surprisingly, ended up being completely natural to use is the *inverse* of the call-SCC DAG. We add the leaf SCCs to the graph as "roots", and have edges to the caller SCCs. Once I switched to building this structure, everything just fell into place elegantly. Aside from general cleanups (there are FIXMEs and too few comments overall) that are still needed, the other missing piece of this is support for iterating across levels of the SCC graph. These will become useful for implementing #2, but they aren't an immediate priority. Once SCCs are in good shape, I'll be working on adding mutation support for incremental updates and adding the pass manager that this analysis enables. llvm-svn: 206581
* X86: Pattern match scalar loads + vcvtph2ps into just vcvtph2ps.Benjamin Kramer2014-04-181-0/+6
| | | | | | | vcvtph2ps only reads the lower 64 bits of the address passed to the intrinsic. llvm-svn: 206579
* Revert r206565 (and r206566 which updated tests).Chandler Carruth2014-04-181-11/+4
| | | | | | | | | | | | | | This commit was attributed to a different person from the person who posted the patch to the list, and the person who posted it the list claimed when they did that they were not the author, but that the author was yet a third person. I don't know what is going on here, but reverting until the attribution is clear and the author has explicitly contributed the patch. Also, the review hasn't really involved any of the MC maintainers and that seems questionable too. llvm-svn: 206576
* AArch64/ARM64: spot a greater variety of concat_vector operations.Tim Northover2014-04-181-14/+72
| | | | | | | | | | Code mostly copied from AArch64, just tidied up a trifle and plumbed into the ARM64 way of doing things. This also enables the AArch64 tests which inspired the previous untested commits. llvm-svn: 206574
* ARM64: implement cunning optimisation from AArch64Tim Northover2014-04-181-0/+53
| | | | | | | | A vector extract followed by a dup can become a single instruction even if the types don't match. AArch64 handled this in ISelLowering, but a few reasonably simple patterns can take care of it in TableGen, so that's where I've put it. llvm-svn: 206573
* ARM64: spot a vector_shuffle that maps to INS and expand.Tim Northover2014-04-181-0/+64
| | | | | | | Tests will be coming very shortly when all the optimisations needed to support AArch64's neon-copy.ll file are committed. llvm-svn: 206572
* ARM64: nick some AArch64 patterns for extract/insert -> INS.Tim Northover2014-04-181-0/+37
| | | | | | | Tests will be committed shortly when all optimisations needed to support AArch64's neon-copy.ll file are supported. llvm-svn: 206571
* AArch64/ARM64: emit all vector FP comparisons as such.Tim Northover2014-04-181-5/+42
| | | | | | | | | | | | ARM64 was scalarizing some vector comparisons which don't quite map to AArch64's compare and mask instructions. AArch64's approach of sacrificing a little efficiency to emulate them with the limited set available was better, so I ported it across. More "inspired by" than copy/paste since the backend's internal expectations were a bit different, but the tests were invaluable. llvm-svn: 206570
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