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* [ConstantRange] Add unsignedMulMayOverflow()Nikita Popov2019-04-111-0/+20
| | | | | | | | | | Same as the other ConstantRange overflow checking methods, but for unsigned mul. In this case there is no cheap overflow criterion, so using umul_ov for the implementation. Differential Revision: https://reviews.llvm.org/D60574 llvm-svn: 358228
* [PGO] Better handling of profile hash mismatchRong Xu2019-04-111-6/+20
| | | | | | | | | | | We currently assume profile hash conflicts will be caught by an upfront check and we assert for the cases that escape the check. The assumption is not always true as there are chances of conflict. This patch prints a warning and skips annotating the function for the escaped cases,. Differential Revision: https://reviews.llvm.org/D60154 llvm-svn: 358225
* [AArch64][GlobalISel] Flesh out vector load/store support for more types.Amara Emerson2019-04-111-0/+8
| | | | | | | Some of these were legalizing into smaller vector types unnecessarily, others were simply not supported yet. llvm-svn: 358223
* [AArch64][GlobalISel] Legalization and ISel support for load/stores of ↵Amara Emerson2019-04-113-9/+67
| | | | | | | | | | | | | | | | vectors of pointers. Loads and store of values with type like <2 x p0> currently don't get imported because SelectionDAG has no knowledge of pointer types. To leverage the existing support for vector load/stores, we can bitcast the value to have s64 element types instead. We do this as a custom legalization. This patch also adds support for general loads of <2 x s64>, and relaxes some type conditions on selecting G_BITCAST. Differential Revision: https://reviews.llvm.org/D60534 llvm-svn: 358221
* [X86] Restrict vselect handling in scalarizeExtEltFP to only case to pre ↵Craig Topper2019-04-111-0/+4
| | | | | | | | | | type legalization where the setcc result type is vXi1. If the vector setcc has been legalized then we will need to convert a vector boolean of 0 or -1 to a scalar boolean of 0 or 1. The added test case previously crashed in 32-bit mode by creating a setcc with an i64 condition that type legalization couldn't expand. llvm-svn: 358218
* [X86] Add patterns for using movss/movsd for atomic load/store of f32/64. ↵Craig Topper2019-04-112-70/+51
| | | | | | | | | | | | | | Remove atomic fadd pseudos use isel patterns instead. This patch adds patterns for turning bitcasted atomic load/store into movss/sd. It also removes the pseudo instructions for atomic RMW fadd. Instead just adding isel patterns for folding an atomic load into addss/sd. And relying on the new movss/sd store pattern to handle the write part. This also makes the fadd patterns use VEX and EVEX instructions when AVX or AVX512F are enabled. Differential Revision: https://reviews.llvm.org/D60394 llvm-svn: 358215
* Recommit r358211 "[X86] Use FILD/FIST to implement i64 atomic load on 32-bit ↵Craig Topper2019-04-113-20/+75
| | | | | | | | | | | | targets with X87, but no SSE2" With correct test checks this time. If we have X87, but not SSE2 we can atomicaly load an i64 value into the significand of an 80-bit extended precision x87 register using fild. We can then use a fist instruction to convert it back to an i64 integ This matches what gcc and icc do for this case and removes an existing FIXME. llvm-svn: 358214
* Revert r358211 "[X86] Use FILD/FIST to implement i64 atomic load on 32-bit ↵Craig Topper2019-04-113-75/+20
| | | | | | | | targets with X87, but no SSE2" I seem to have messed up the test checks. llvm-svn: 358212
* [X86] Use FILD/FIST to implement i64 atomic load on 32-bit targets with X87, ↵Craig Topper2019-04-113-20/+75
| | | | | | | | | | | | but no SSE2 If we have X87, but not SSE2 we can atomicaly load an i64 value into the significand of an 80-bit extended precision x87 register using fild. We can then use a fist instruction to convert it back to an i64 integer and store it to a stack temporary. From there we can do two 32-bit loads to get the value into integer registers without worrying about atomicness. This matches what gcc and icc do for this case and removes an existing FIXME. Differential Revision: https://reviews.llvm.org/D60156 llvm-svn: 358211
* Revert "Use llvm::lower_bound. NFC"Ali Tamur2019-04-117-23/+28
| | | | | | | | | This reverts commit rL358161. This patch have broken the test: llvm/test/tools/llvm-exegesis/X86/uops-CMOV16rm-noreg.s llvm-svn: 358199
* [ConstantFold] ExtractConstantBytes - handle shifts on large integer typesSimon Pilgrim2019-04-111-14/+16
| | | | | | | | Use APInt instead of getZExtValue from the ConstantInt until we can confirm that the shift amount is in range. Reduced from OSS-Fuzz #14169 - https://bugs.chromium.org/p/oss-fuzz/issues/detail?id=14169 llvm-svn: 358192
* [DAGCombiner] refactor narrowing of extracted vector binop; NFCSanjay Patel2019-04-111-20/+19
| | | | | | | There's a TODO comment about handling patterns with insert_subvector, and we do want to match that. llvm-svn: 358187
* [X86] SimplifyDemandedVectorElts - add X86ISD::VPERMV3 mask supportSimon Pilgrim2019-04-111-1/+1
| | | | | | Completes SimplifyDemandedVectorElts's basic variable shuffle mask support which should help D60512 + D60562 llvm-svn: 358186
* [RISCV] Diagnose invalid second input register operand when using %tprel_addRoger Ferrer Ibanez2019-04-111-2/+26
| | | | | | | | | | | | | | | | | | | RISCVMCCodeEmitter::expandAddTPRel asserts that the second operand must be x4/tp. As we are not currently checking this in the RISCVAsmParser, the assert is easy to trigger due to wrong assembly input. This patch does a late check of this constraint. An alternative could be using a singleton register class for x4/tp similar to the current one for sp. Unfortunately it does not result in a good diagnostic. Because add is an overloaded mnemonic, if no matching is possible, the diagnostic of the first failing alternative seems to be used as the diagnostic itself. This means that this case the %tprel_add is diagnosed as an invalid operand (because the real add instruction only has 3 operands). Differential Revision: https://reviews.llvm.org/D60528 llvm-svn: 358183
* [X86] Add MM register mapping from CodeView to MC register idLuo, Yuanke2019-04-111-0/+9
| | | | | | | Differential Revision: https://reviews.llvm.org/D60437 Change-Id: I2183a6d825d0284b22705d423b88882992b236c5 llvm-svn: 358179
* YAMLIO: Fix serialization of strings with embedded nulsPavel Labath2019-04-111-6/+6
| | | | | | | | | | | | | | | | | | | | | | Summary: A bug/typo in Output::scalarString caused us to round-trip a StringRef through a const char *. This meant that any strings with embedded nuls were unintentionally cut short at the first such character. (It also could have caused accidental buffer overruns, but it seems that all StringRefs coming into this functions were formed from null-terminated strings.) This patch fixes the bug and adds an appropriate test. Reviewers: sammccall, jhenderson Subscribers: kristina, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D60505 llvm-svn: 358176
* [X86] SimplifyDemandedVectorElts - add X86ISD::VPERMV mask supportSimon Pilgrim2019-04-111-0/+8
| | | | llvm-svn: 358174
* [DAGCombiner][x86] scalarize inserted vector FP opsSanjay Patel2019-04-111-0/+58
| | | | | | | | | | | | | | | | | | | | | | | // bo (build_vec ...undef, x, undef...), (build_vec ...undef, y, undef...) --> // build_vec ...undef, (bo x, y), undef... The lifetime of the nodes in these examples is different for variables versus constants, but they are all build vectors briefly, so I'm proposing to catch them in this form to handle all of the leading examples in the motivating test file. Before we have build vectors, we might have insert_vector_element. After that, we might have scalar_to_vector and constant pool loads. It's going to take more work to ensure that FP vector operands are getting simplified with undef elements, so this transform can apply more widely. In a non-loose FP environment, we are likely simplifying FP elements to NaN values rather than undefs. We also need to allow more opcodes down this path. Eg, we don't handle FP min/max flavors yet. Differential Revision: https://reviews.llvm.org/D60514 llvm-svn: 358172
* [AArch64] Add lowering pattern for llvm.aarch64.neon.vcvtfxs2fp.f16.i64Diogo N. Sampaio2019-04-111-0/+2
| | | | | | | | | | | | | | | | Summary: Add lowering pattern for llvm.aarch64.neon.vcvtfxs2fp.f16.i64 Reviewers: pbarrio, DavidSpickett, LukeGeeson Reviewed By: LukeGeeson Subscribers: javed.absar, kristof.beyls, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D60259 llvm-svn: 358171
* [X86] SimplifyDemandedVectorElts - add X86ISD::VPERMILPV mask supportSimon Pilgrim2019-04-111-1/+2
| | | | llvm-svn: 358170
* [X86] SimplifyDemandedVectorElts - add X86ISD::VPERMIL2 mask supportSimon Pilgrim2019-04-111-2/+2
| | | | llvm-svn: 358167
* [X86] SimplifyDemandedVectorElts - add VPPERM supportSimon Pilgrim2019-04-111-0/+9
| | | | | | We need to add support for all variable shuffle mask ops, but VPPERM is the only one that already has test coverage. llvm-svn: 358165
* [ValueTracking] Change if-else chain into switch in computeKnownBitsFromAssumeSander de Smalen2019-04-111-8/+18
| | | | | | | | | | | This is a follow-up patch to D60504 to further improve performance issues in computeKnownBitsFromAssume. The patch is NFC, but may improve compile-time performance if the compiler isn't clever enough to do the optimization itself. llvm-svn: 358163
* Test commit accessOliver Stannard2019-04-111-0/+1
| | | | llvm-svn: 358162
* Use llvm::lower_bound. NFCFangrui Song2019-04-117-28/+23
| | | | llvm-svn: 358161
* [RISCV] Put data smaller than eight bytes to small data sectionShiva Chen2019-04-113-0/+123
| | | | | | | | | | | Because of gp = sdata_start_address + 0x800, gp with signed twelve-bit offset could covert most of the small data section. Linker relaxation could transfer the multiple data accessing instructions to a gp base with signed twelve-bit offset instruction. Differential Revision: https://reviews.llvm.org/D57493 llvm-svn: 358150
* [DWARF] Set discriminator to 0 for DW_LNS_copyFangrui Song2019-04-111-5/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | Summary: Make DW_LNS_copy set the discriminator register to 0, to conform to DWARF 4 & 5: "Then it sets the discriminator register to 0, and sets the basic_block, prologue_end and epilogue_begin registers to false." Because all of DW_LNE_end_sequence, DN_LNS_copy, and special opcodes reset discriminator to 0, we can move discriminator=0 to appendRowToMatrix. Also, make DW_LNS_copy print before appending the row, as it is similar to a address+=0,line+=0 special opcode, which prints before appending the row. Reviewers: dblaikie, probinson, aprantl Reviewed By: dblaikie Subscribers: danielcdh, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D60364 llvm-svn: 358148
* Fix a hang when lowering __builtin_dynamic_object_sizeErik Pilkington2019-04-101-4/+18
| | | | | | | | | | | | | If the ObjectSizeOffsetEvaluator fails to fold the object size call, then it may litter some unused instructions in the function. When done repeatably in InstCombine, this results in an infinite loop. Fix this by tracking the set of instructions that were inserted, then removing them on failure. rdar://49172227 Differential revision: https://reviews.llvm.org/D60298 llvm-svn: 358146
* [AArch64][GlobalISel] Make <2 x p0> = G_BUILD_VECTOR legal.Amara Emerson2019-04-101-0/+1
| | | | | | The existing isel support already works for p0 once the legalizer accepts it. llvm-svn: 358144
* [AArch64][GlobalISel] Add legalizer support for <8 x s16> and <16 x s8> G_ADD.Amara Emerson2019-04-101-1/+1
| | | | llvm-svn: 358143
* [AArch64][GlobalISel] Scalarize vector SDIV.Amara Emerson2019-04-102-1/+3
| | | | llvm-svn: 358142
* [X86] Teach foldMaskedShiftToScaledMask to look through an any_extend from ↵Craig Topper2019-04-101-22/+44
| | | | | | | | | | | | | | i32 to i64 between the and & shl foldMaskedShiftToScaledMask tries to reorder and & shl to enable the shl to fold into an LEA. But if there is an any_extend between them it doesn't work. This patch modifies the code to look through any_extend from i32 to i64 when the and mask only uses bits that weren't from the extended part. This will prevent a regression from D60358 caused by 64-bit SHL being narrowed to 32-bits when their upper bits aren't demanded. Differential Revision: https://reviews.llvm.org/D60532 llvm-svn: 358139
* [X86] Make _Int instructions the preferred instructon for the assembly ↵Craig Topper2019-04-106-147/+152
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | parser and disassembly parser to remove inconsistencies between VEX and EVEX. Many of our instructions have both a _Int form used by intrinsics and a form used by other IR constructs. In the EVEX space the _Int versions usually cover all the capabilities include broadcasting and rounding. While the other version only covers simple register/register or register/load forms. For this reason in EVEX, the non intrinsic form is usually marked isCodeGenOnly=1. In the VEX encoding space we were less consistent, but usually the _Int version was the isCodeGenOnly version. This commit makes the VEX instructions match the EVEX instructions. This was done by manually studying the AsmMatcher table so its possible I missed some cases, but we should be closer now. I'm thinking about using the isCodeGenOnly bit to simplify the EVEX2VEX tablegen code that disambiguates the _Int and non _Int versions. Currently it checks register class sizes and Record the memory operands come from. I have some other changes I was looking into for D59266 that may break the memory check. I had to make a few scheduler hacks to keep the _Int versions from being treated differently than the non _Int version. Differential Revision: https://reviews.llvm.org/D60441 llvm-svn: 358138
* [X86] Replace some if statements in isel address matching that should never ↵Craig Topper2019-04-101-8/+10
| | | | | | | | | | | | | | be true with asserts. And move them earlier before we looked through operands that don't change size. NFC These ifs were ensuring we don't have to handle types larger than 64 bits probably because we use getZExtValue in several places below them. None of the callers of this code pass types larger than 64-bits so we can just assert instead of branching in release code. I've also moved them earlier since we're just looking through operations that don't effect bit width. This is prep work for some refactoring I plan to do to the (and (shl)) handling code. llvm-svn: 358123
* [X86AsmPrinter] refactor to limit use of Modifier. NFCNick Desaulniers2019-04-101-47/+57
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: The Modifier memory operands is used in 2 cases of memory references (H & P ExtraCodes). Rather than pass around the likely nullptr Modifier, refactor the handling of the Modifier out from printOperand(). The refactorings in this patch: - Don't forward declare printOperand, move its definition up. - The diff makes it look like there's a change to printPCRelImm (narrator: there's not). - Create printModifiedOperand() - Move logic for Modifier to there from printOperand - Use printModifiedOperand in 3 call sites that actually create Modifiers. - Remove now unused Modifier parameter from printOperand - Remove default parameter from printLeaMemReference as it only has 1 call site that explicitly passes a parameter. - Remove default parameter from printMemReference, make call lone call site explicitly pass nullptr. - Drop Modifier parameter from printIntelMemReference, as Intel style memory references don't support the Modifiers in question. This will allow future changes to printOperand() to make it a pure virtual method on the base AsmPrinter class, allowing for more generic handling of some architecture generic constraints. X86AsmPrinter was the only derived class of AsmPrinter to have additional parameters on its printOperand function. Reviewers: craig.topper, echristo Reviewed By: echristo Subscribers: hiraditya, llvm-commits, srhines Tags: #llvm Differential Revision: https://reviews.llvm.org/D60526 llvm-svn: 358122
* [llvm] Non-functional change: declared a local variable as const.Ali Tamur2019-04-101-1/+1
| | | | llvm-svn: 358120
* [X86] X86ScheduleBdVer2: use !listsplat operator to cleanup loadres calculationRoman Lebedev2019-04-101-4/+7
| | | | | | | | | | | | | The problem is that one can't concatenate an empty list (implied all-ones) with non-empty list here. The result will be the non-empty list, and it won't match the length of the ExePorts list. The problems begin when LoadRes != 1 here, which is the case in PdWriteResYMMPair, and more importantly i think it will be the case for PdWriteResExPair. llvm-svn: 358118
* [TableGen] Introduce !listsplat 'binary' operatorRoman Lebedev2019-04-104-3/+56
| | | | | | | | | | | | | | | | | | | | | | | | | | Summary: ``` ``!listsplat(a, size)`` A list value that contains the value ``a`` ``size`` times. Example: ``!listsplat(0, 2)`` results in ``[0, 0]``. ``` I plan to use this in X86ScheduleBdVer2.td for LoadRes handling. This is a little bit controversial because unlike every other binary operator the types aren't identical. Reviewers: stoklund, javed.absar, nhaehnle, craig.topper Reviewed By: javed.absar Subscribers: llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D60367 llvm-svn: 358117
* Revert rL357745: [SelectionDAG] Compute known bits of CopyFromRegDavid Green2019-04-102-23/+3
| | | | | | | | | | Certain optimisations from ConstantHoisting and CGP rely on Selection DAG not seeing through to the constant in other blocks. Revert this patch while we come up with a better way to handle that. I will try to follow this up with some better tests. llvm-svn: 358113
* llvm-undname: Fix another crash-on-invalidNico Weber2019-04-101-2/+0
| | | | | | | | | | | | | | | | | | | | | | | | This fixes a regression from https://reviews.llvm.org/D60354. We used to SymbolNode *Symbol = demangleEncodedSymbol(MangledName, QN); if (Symbol) { Symbol->Name = QN; } but changed that to SymbolNode *Symbol = demangleEncodedSymbol(MangledName, QN); if (Error) return nullptr; Symbol->Name = QN; and one branch somewhere returned a nullptr without setting Error. Looking at the code changed in r340083 and r340710 that branch looks like a remnant from an earlier attempt to demangle RTTI descriptors that has since been rewritten -- so just remove this branch. It shouldn't change behavior for correctly mangled symbols. llvm-svn: 358112
* GlobalISel: Move computeValueLLTsMatt Arsenault2019-04-102-30/+30
| | | | | | | | | Call lowering should use this directly instead of going through the EVT version, but more work is needed to deal with this (mostly the passing of the IR type pointer instead of the relevant properties in ArgInfo). llvm-svn: 358111
* GlobalISel: Fix invoke lowering creating invalid type registersMatt Arsenault2019-04-101-2/+3
| | | | | | | Unlike the call handling, this wasn't checking for void results and creating a register with the invalid LLT llvm-svn: 358110
* GlobalISel: Support legalizing G_CONSTANT with irregular breakdownMatt Arsenault2019-04-101-25/+32
| | | | llvm-svn: 358109
* [AArch64] Teach getTestBitOperand to look through ANY_EXTENDSCraig Topper2019-04-101-0/+6
| | | | | | | | This patch teach getTestBitOperand to look through ANY_EXTENDs when the extended bits aren't used. The test case changed here is based what D60358 did to test16 in tbz-tbnz.ll. So this patch will avoid that regression. Differential Revision: https://reviews.llvm.org/D60482 llvm-svn: 358108
* GlobalISel: Handle odd breakdowns for bit opsMatt Arsenault2019-04-101-40/+42
| | | | llvm-svn: 358105
* [AsmPrinter] refactor to remove remove AsmVariant. NFCNick Desaulniers2019-04-1026-176/+101
| | | | | | | | | | | | | | | | | | | | | | | | | Summary: The InlineAsm::AsmDialect is only required for X86; no architecture makes use of it and as such it gets passed around between arch-specific and general code while being unused for all architectures but X86. Since the AsmDialect is queried from a MachineInstr, which we also pass around, remove the additional AsmDialect parameter and query for it deep in the X86AsmPrinter only when needed/as late as possible. This refactor should help later planned refactors to AsmPrinter, as this difference in the X86AsmPrinter makes it harder to make AsmPrinter more generic. Reviewers: craig.topper Subscribers: jholewinski, arsenm, dschuff, jyknight, dylanmckay, sdardis, nemanjai, jvesely, nhaehnle, javed.absar, sbc100, jgravelle-google, eraman, hiraditya, aheejin, kbarton, fedor.sergeev, asb, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, jrtc27, zzheng, edward-jones, atanasyan, rogfer01, MartinMosbeck, brucehoult, the_o, PkmX, jocewei, jsji, llvm-commits, peter.smith, srhines Tags: #llvm Differential Revision: https://reviews.llvm.org/D60488 llvm-svn: 358101
* [InstCombine] Handle ssubo always overflowNikita Popov2019-04-101-3/+3
| | | | | | | | | Following D60483 and D60497, this adds support for AlwaysOverflows handling for ssubo. This is the last case we can handle right now. Differential Revision: https://reviews.llvm.org/D60518 llvm-svn: 358100
* [InstCombine] ssubo X, C -> saddo X, -CNikita Popov2019-04-101-0/+21
| | | | | | | | | | | | ssubo X, C is equivalent to saddo X, -C. Make the transformation in InstCombine and allow the logic implemented for saddo to fold prior usages of add nsw or sub nsw with constants. Patch by Dan Robertson. Differential Revision: https://reviews.llvm.org/D60061 llvm-svn: 358099
* Improve compile-time performance in computeKnownBitsFromAssume.Sander de Smalen2019-04-101-217/+214
| | | | | | | | | | | | | | This patch changes the order of pattern matching by first testing a compare instruction's predicate, before doing the pattern match for the whole expression tree. Patch by Paul Walker. Reviewed By: spatel Differential Revision: https://reviews.llvm.org/D60504 llvm-svn: 358097
* [X86][AVX] getTargetConstantBitsFromNode - extract bits from ↵Simon Pilgrim2019-04-101-0/+13
| | | | | | X86ISD::SUBV_BROADCAST llvm-svn: 358096
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