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* [SelectionDAG] Don't promote mask operands of MGATHER and MLOAD to setcc ↵Craig Topper2017-12-051-2/+10
| | | | | | | | result type while widening the result. Just widen the mask. The mask will be promoted if necessary when operands are promoted. It's possible the mask type is legal, but the setcc result type is a different. We shouldn't promote to the setcc result type unless the mask needs to be promoted. llvm-svn: 319850
* [SelectionDAG] Don't call GetWidenedVector for mask operands of MLOAD/MSTORE.Craig Topper2017-12-051-13/+6
| | | | | | GetWidenedVector does't guarantee the widened elements are zero which would break the intended behavior of the operation. llvm-svn: 319849
* Revert r319794: [PGO] detect infinite loop and form MST properly: memory ↵Xinliang David Li2017-12-052-57/+15
| | | | | | leak problem llvm-svn: 319841
* [SafepointIRVerifier] Allow deriving pointers from unrelocated baseAnna Thomas2017-12-051-45/+122
| | | | | | | | | | | | | | | | | | | | | | | | | | Summary: This patch allows to use derived pointers (GEPs/bitcasts) of unrelocated base pointers. We care only about the uses of these derived pointers. It is acheived by two changes: 1. When we have enough information to say if the pointer is unrelocated at some point or not, we walk all BBs to remove from their Contributions all valid defs of unrelocated pointers (GEP with unrelocated base or bitcast of unrelocated pointer). 2. When it comes to verification we just ignore instructions that were removed at stage 1. Patch by Daniil Suchkov! Reviewers: anna, reames, apilipenko, mkazantsev Reviewed By: anna, mkazantsev Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D40289 llvm-svn: 319838
* [AArch64] Do not abort if overflow check does not use EQ or NE.Joel Galenson2017-12-051-3/+2
| | | | | | | | | | As suggested by Eli Friedman, instead of aborting if an overflow check uses something other than SETEQ or SETNE, simply do not apply the optimization. Differential Revision: https://reviews.llvm.org/D39147 llvm-svn: 319837
* [X86][AVX512] Tag BLENDM instruction scheduler classesSimon Pilgrim2017-12-051-28/+45
| | | | llvm-svn: 319833
* [ModRefInfo] Initialize ArgMask to MRI_NoModRef.Alina Sbirlea2017-12-051-1/+1
| | | | llvm-svn: 319831
* [X86][AVX512] Tag GATHER/SCATTER instruction scheduler classesSimon Pilgrim2017-12-052-7/+11
| | | | | NOTE: At the moment these use the WriteLoad/WriteStore classes, which severely underestimates the costs. This needs to be reviewed. llvm-svn: 319829
* [DWARFv5] Emit v5 line table header.Paul Robinson2017-12-051-32/+84
| | | | | | Differential Revision: https://reviews.llvm.org/D40741 llvm-svn: 319827
* AMDGPU: Fix SDWA crash on inline asmMatt Arsenault2017-12-051-1/+2
| | | | | | | | This was only searching for explicit defs, and asserting for any implicit or variadic instruction defs, like inline asm. llvm-svn: 319826
* Re-commit r319490 "XOR the frame pointer with the stack cookie when ↵Hans Wennborg2017-12-056-5/+55
| | | | | | | | | | | | | | | | | | protecting the stack" The patch originally broke Chromium (crbug.com/791714) due to its failing to specify that the new pseudo instructions clobber EFLAGS. This commit fixes that. > Summary: This strengthens the guard and matches MSVC. > > Reviewers: hans, etienneb > > Subscribers: hiraditya, JDevlieghere, vlad.tsyrklevich, llvm-commits > > Differential Revision: https://reviews.llvm.org/D40622 llvm-svn: 319824
* [X86][AVX512] Tag VPSLLDQ/VPSRLDQ instruction scheduler classesSimon Pilgrim2017-12-051-9/+20
| | | | llvm-svn: 319822
* Modify ModRefInfo values using static inline method abstractions [NFC].Alina Sbirlea2017-12-0515-110/+113
| | | | | | | | | | | | | | | | | Summary: The aim is to make ModRefInfo checks and changes more intuitive and less error prone using inline methods that abstract the bit operations. Ideally ModRefInfo would become an enum class, but that change will require a wider set of changes into FunctionModRefBehavior. Reviewers: sanjoy, george.burgess.iv, dberlin, hfinkel Subscribers: nlopes, llvm-commits Differential Revision: https://reviews.llvm.org/D40749 llvm-svn: 319821
* [SystemZ] Validate shifted compare value in adjustForTestUnderMaskUlrich Weigand2017-12-051-0/+2
| | | | | | | | | | | When folding a shift into a test-under-mask comparison, make sure that there is no loss of precision when creating the shifted comparison value. This usually never happens, except for certain always-true comparisons in unoptimized code. Fixes PR35529. llvm-svn: 319818
* [X86][AVX512] Tag VPTRUNC/VPMOVSX/VPMOVZX instruction scheduler classesSimon Pilgrim2017-12-051-90/+106
| | | | llvm-svn: 319815
* [WebAssembly] Make stack-pointer imports mutable.Dan Gohman2017-12-051-40/+47
| | | | | | | | | | | | This is not currently valid by the wasm spec, however: - It replaces doing set_global on an immutable global, which is also not valid. - It's expected be valid in the near future: https://github.com/WebAssembly/threads/blob/master/proposals/threads/Globals.md - This only occurs before linking, so a fully linked object will be valid. llvm-svn: 319810
* AMDGPU: Fix infinite loop with dbg_valueMatt Arsenault2017-12-051-1/+4
| | | | | | | | | Surprisingly SIOptimizeExecMaskingPreRA can infinite loop in some case with DBG_VALUE. Most tests using dbg_value are run at -O0, so don't run this pass. This seems to only happen when the value argument is undef. llvm-svn: 319808
* [CVP] Remove some {s|u}sub.with.overflow checks.Joel Galenson2017-12-051-8/+17
| | | | | | | | This uses ConstantRange::makeGuaranteedNoWrapRegion's newly-added handling for subtraction to allow CVP to remove some subtraction overflow checks. Differential Revision: https://reviews.llvm.org/D40039 llvm-svn: 319807
* [ConstantRange] Support subtraction in makeGuaranteedNoWrapRegion.Joel Galenson2017-12-051-28/+52
| | | | | | | | Previously ConstantRange::makeGuaranteedNoWrapRegion only handled addition. This adds support for subtraction. Differential Revision: https://reviews.llvm.org/D40036 llvm-svn: 319806
* [X86][X87] Tag FCMOV instruction scheduler classesSimon Pilgrim2017-12-054-16/+22
| | | | llvm-svn: 319804
* Test commit.Joel Galenson2017-12-051-1/+1
| | | | | | I removed a space at the end of a comment. NFC. llvm-svn: 319803
* [SelectionDAG] Remove the code that handles SETCC with a scalar result type ↵Craig Topper2017-12-052-15/+1
| | | | | | | | | | from vector widening. There's no such thing as a setcc with vector operands and scalar result. And if we're trying to widen the result we would have to already be looking at a vector result type. So this patch renames the VSETCC function as the SETCC function and delete the original SETCC function. llvm-svn: 319799
* [SelectionDAG] Remove unused method declaration.Craig Topper2017-12-051-1/+0
| | | | | | The method implementation was removed in r318982. llvm-svn: 319798
* [WebAssembly] Implement WASM_STACK_POINTER.Dan Gohman2017-12-054-20/+26
| | | | | | | Use the .stack_pointer directive to implement WASM_STACK_POINTER for specifying a global variable to be the stack pointer. llvm-svn: 319797
* [WebAssembly] Don't emit .import_global for the wasm target.Dan Gohman2017-12-051-1/+2
| | | | | | | .import_global is used by the ELF-based target and not needed by the wasm target. llvm-svn: 319796
* [PGO] detect infinite loop and form MST properlyXinliang David Li2017-12-052-15/+57
| | | | | | Differential Revision: http://reviews.llvm.org/D40702 llvm-svn: 319794
* Delete temp file if rename fails.Rafael Espindola2017-12-052-5/+23
| | | | | | | | | | | | | | | | | | | Without this when lld failed to replace the output file it would leave the temporary behind. The problem is that the existing logic is - cancel the delete flag - rename We have to cancel first to avoid renaming and then crashing and deleting the old version. What is missing then is deleting the temporary file if the rename fails. This can be an issue on both unix and windows, but I am not sure how to cause the rename to fail reliably on unix. I think it can be done on ZFS since it has an ACL system similar to what windows uses, but adding support for checking that in llvm-lit is probably not worth it. llvm-svn: 319786
* [X86][AVX512] Tag VNNIW instruction scheduler classesSimon Pilgrim2017-12-051-15/+18
| | | | llvm-svn: 319784
* [X86][AVX512] Drop some default NoItinerary arguments that aren't needed any ↵Simon Pilgrim2017-12-051-9/+10
| | | | | | more llvm-svn: 319782
* [x86][AVX512] Lowering kunpack intrinsics to LLVM IRJina Nahias2017-12-053-3/+54
| | | | | | | | | This patch, together with a matching clang patch (https://reviews.llvm.org/D39719), implements the lowering of X86 kunpack intrinsics to IR. Differential Revision: https://reviews.llvm.org/D39720 Change-Id: I4088d9428478f9457f6afddc90bd3d66b3daf0a1 llvm-svn: 319778
* [DAGCombine] Move AND nodes to multiple load leavesSam Parker2017-12-051-0/+123
| | | | | | | | | | | | | Search from AND nodes to find whether they can be propagated back to loads, so that the AND and load can be combined into a narrow load. We search through OR, XOR and other AND nodes and all bar one of the leaves are required to be loads or constants. The exception node then needs to be masked off meaning that the 'and' isn't removed, but the loads(s) are narrowed still. Differential Revision: https://reviews.llvm.org/D39604 llvm-svn: 319773
* [X86][AVX512] Tag VPMADD52/VPSADBW instruction scheduler classesSimon Pilgrim2017-12-051-22/+25
| | | | llvm-svn: 319772
* [DAGCombine] Handle big endian correctly in CombineConsecutiveLoadsBjorn Pettersson2017-12-051-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: Found out, at code inspection, that there was a fault in DAGCombiner::CombineConsecutiveLoads for big-endian targets. A BUILD_PAIR is always having the least significant bits of the composite value in element 0. So when we are doing the checks for consecutive loads, for big endian targets, we should check if the load to elt 1 is at the lower address and the load to elt 0 is at the higher address. Normally this bug only resulted in missed oppurtunities for doing the load combine. I guess that in some rare situation it could lead to faulty combines, but I've not seen that happen. Note that this patch actually will trigger load combine for some big endian regression tests. One example is test/CodeGen/PowerPC/anon_aggr.ll where we now get t76: i64,ch = load<LD8[FixedStack-9] instead of t37: i32,ch = load<LD4[FixedStack-10]> t35: i32,ch = load<LD4[FixedStack-9]> t41: i64 = build_pair t37, t35 before legalization. Then the legalization will split the LD8 into two loads, so the end result is the same. That should verify that the transfomation is correct now. Reviewers: niravd, hfinkel Reviewed By: niravd Subscribers: nemanjai, llvm-commits Differential Revision: https://reviews.llvm.org/D40444 llvm-svn: 319771
* [X86][AVX512] Add missing scalar CMPSS/CMPSD logic scheduler classesSimon Pilgrim2017-12-051-16/+21
| | | | llvm-svn: 319770
* Bail out of a SimplifyCFG switch table opt at undef values.Mikael Holmen2017-12-051-1/+1
| | | | | | | | | | | | | | | | | | | Summary: A true or false result is expected from a comparison, but it seems the possibility of undef was overlooked, which could lead to a failed assert. This is fixed by this patch by bailing out if we encounter undef. The bug is old and the assert has been there since the end of 2014, so it seems this is unusual enough to forego optimization. Patch by JesperAntonsson. Reviewers: spatel, eeckstein, hans Reviewed By: hans Subscribers: uabelho, llvm-commits Differential Revision: https://reviews.llvm.org/D40639 llvm-svn: 319768
* [X86][AVX512] Cleanup bit logic scheduler classesSimon Pilgrim2017-12-051-21/+24
| | | | llvm-svn: 319767
* [DAGCombine] isLegalNarrowLoad function (NFC)Sam Parker2017-12-051-42/+60
| | | | | | | | | Pull the checks upon the load out from ReduceLoadWidth into their own function. Differential Revision: https://reviews.llvm.org/D40833 llvm-svn: 319766
* [X86][AVX512] Tag scalar CVT and CMP instruction scheduler classesSimon Pilgrim2017-12-052-130/+150
| | | | llvm-svn: 319765
* [InstCombine] Don't crash on out of bounds shiftsIgor Laevsky2017-12-051-13/+17
| | | | | | Differential Revision: https://reviews.llvm.org/D40649 llvm-svn: 319761
* [X86][AVX512] Tag VPCMP/VPCMPU instruction scheduler classesSimon Pilgrim2017-12-051-42/+60
| | | | | | Move hardcoded itinerary out to the instruction declarations. Not sure that IIC_SSE_ALU_F32P is the best schedule for integer comparisons, but I'm not going to change it right now. llvm-svn: 319760
* [X86][AVX512] Cleanup VPCMP scheduler classesSimon Pilgrim2017-12-051-27/+30
| | | | | | Move hardcoded itinerary out to the instruction declarations. Not sure that IIC_SSE_ALU_F32P is the best schedule for integer comparisons, but I'm not going to change it right now. llvm-svn: 319758
* [X86][AVX512] Tag VFIXUPIMM instructions scheduler classesSimon Pilgrim2017-12-051-23/+30
| | | | llvm-svn: 319757
* [SystemZ] set 'guessInstructionProperties = 0' and set flags as needed.Jonas Paulsson2017-12-056-123/+131
| | | | | | | | | | | | | | | | | | | | This has proven a healthy exercise, as many cases of incorrect instruction flags were corrected in the process. As part of this, IntrWriteMem was added to several SystemZ instrinsics. Furthermore, a bug was exposed in TwoAddress with this change (as incorrect hasSideEffects flags were removed and instructions could now be sunk), and the test case for that bugfix (r319646) is included here as test/CodeGen/SystemZ/twoaddr-sink.ll. One temporary test regression (one extra copy) which will hopefully go away in upcoming patches for similar cases: test/CodeGen/SystemZ/vec-trunc-to-i1.ll Review: Ulrich Weigand. https://reviews.llvm.org/D40437 llvm-svn: 319756
* [Regalloc] Generate and store multiple regalloc hints.Jonas Paulsson2017-12-053-54/+100
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | MachineRegisterInfo used to allow just one regalloc hint per virtual register. This patch extends this to a vector of regalloc hints, which is filled in by common code with sorted copy hints. Such hints will make for more ID copies that can be removed. NB! This improvement is currently (and hopefully temporarily) *disabled* by default, except for SystemZ. The only reason for this is the big impact this has on tests, which has unfortunately proven unmanageable. It was a long while since all the tests were updated and just waiting for review (which didn't happen), but now targets have to enable this themselves instead. Several targets could get a head-start by downloading the tests updates from the Phabricator review. Thanks to those who helped, and sorry you now have to do this step yourselves. This should be an improvement generally for any target! The target may still create its own hint, in which case this has highest priority and is stored first in the vector. If it has target-type, it will not be recomputed, as per the previous behaviour. The temporary hook enableMultipleCopyHints() will be removed as soon as all targets return true. Review: Quentin Colombet, Ulrich Weigand. https://reviews.llvm.org/D38128 llvm-svn: 319754
* Re-commit "[cmake] Enable zlib support on windows"Pavel Labath2017-12-051-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | This recommits r319533 which was broken llvm-config --system-libs output. The reason was that I used find_libraries for searching for the z library. This returns absolute paths, and when these paths made it into llvm-config, it made it produce nonsensical flags. To fix this, I hand-roll a search for the library in the same way that we search for the terminfo library a couple of lines below. This is a bit less flexible than the find_library option, as it does not allow the user to specify the path to the library at configure time (which is important on windows, as zlib is unlikely to be found in any of the standard places cmake searches), but I was able to guide the build to find it with appropriate values of LIB and INCLUDE environment variables. Reviewers: compnerd, rnk, beanz, rafael Subscribers: llvm-commits, mgorny Differential Revision: https://reviews.llvm.org/D40779 llvm-svn: 319751
* [Support/TarWriter] - Don't allow TarWriter to add the same file more than once.George Rimar2017-12-051-0/+4
| | | | | | | | | | | | | | This is for PR35460. Currently when LLD adds files to TarWriter it may pass the same file multiple times. For example it happens for clang reproduce file which specifies archive (.a) files more than once in command line. Patch makes TarWriter to ignore files with the same path, so it will add only the first one to archive. Differential revision: https://reviews.llvm.org/D40606 llvm-svn: 319750
* [X86] Fix a bug in handling GRXX subclasses in Domain Reassignment passGuy Blank2017-12-051-4/+4
| | | | | | | | | | | When trying to determine the correct Mask register class corresponding to a GPR register class, not all register classes were handled. This caused an assertion to be raised on some scenarios. Differential Revision: https://reviews.llvm.org/D40290 llvm-svn: 319745
* [SelectionDAG] Use WidenTargetBoolean in WidenVecRes_MLOAD and ↵Craig Topper2017-12-051-29/+2
| | | | | | | | WidenVecOp_MSTORE instead of implementing it manually and incorrectly. The CONCAT_VECTORS operand get its type from getSetCCResultType, but if the mask type and the setcc have different scalar sizes this creates an illegal CONCAT_VECTORS operation. The concat type should be 2x the mask type, and then an extend should be added if needed. llvm-svn: 319744
* [X86] Use vector widening to support sign extend from i1 when the dest type ↵Craig Topper2017-12-051-20/+31
| | | | | | | | | | is not 512-bits and vlx is not enabled. Previously we used a wider element type and truncated. But its more efficient to keep the element type and drop unused elements. If BWI isn't supported and we have a i16 or i8 type, we'll extend it to be i32 and still use a truncate. llvm-svn: 319740
* Revert r319691: [globalisel][tablegen] Split atomic load/store into separate ↵Daniel Sanders2017-12-056-61/+17
| | | | | | | | opcode and enable for AArch64. Some concerns were raised with the direction. Revert while we discuss it and look into an alternative llvm-svn: 319739
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