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* [mips] Remove unused NotN64 predicateDaniel Sanders2014-02-191-2/+0
| | | | llvm-svn: 201682
* Fix AVX512 vector sqrt assembly strings.Cameron McInally2014-02-191-4/+4
| | | | llvm-svn: 201681
* Revert r201622 and r201608.Daniel Jasper2014-02-1920-209/+121
| | | | | | | This causes the LLVMgold plugin to segfault. More information on the replies to r201608. llvm-svn: 201669
* X86 CodeGenPrep: sink shufflevectors before shiftsTim Northover2014-02-193-0/+93
| | | | | | | | | | | | | | | | | On x86, shifting a vector by a scalar is significantly cheaper than shifting a vector by another fully general vector. Unfortunately, because SelectionDAG operates on just one basic block at a time, the shufflevector instruction that reveals whether the right-hand side of a shift *is* really a scalar is often not visible to CodeGen when it's needed. This adds another handler to CodeGenPrepare, to sink any useful shufflevector instructions down to the basic block where they're used, predicated on a target hook (since on other architectures, doing so will often just introduce extra real work). rdar://problem/16063505 llvm-svn: 201655
* Remove special FP opcode maps and instead add enough MRM_XX formats to ↵Craig Topper2014-02-195-126/+161
| | | | | | handle all the FP operations. This increases format by 1 bit, but decreases opcode map by 1 bit so the TSFlags size doesn't change. llvm-svn: 201649
* Reduce size of map field in X86 TSFlags since it now requires less bits.Craig Topper2014-02-192-28/+28
| | | | llvm-svn: 201646
* Put some of the X86 formats in a more logical order.Craig Topper2014-02-192-36/+36
| | | | llvm-svn: 201645
* Remove A6/A7 opcode maps. They can all be handled with a TB map, opcode of ↵Craig Topper2014-02-197-100/+52
| | | | | | 0xa6/0xa7, and adding MRM_C0/MRM_E0 forms. Removes 376K from the disassembler tables. llvm-svn: 201641
* MCAsmParser: support required parametersSaleem Abdulrasool2014-02-191-12/+59
| | | | | | | | | | | This enhances the macro parser to parse and handle parameter qualifications, which is needed to support required formal parameters in macro definitions. A required parameter may not be defaulted (though providing a default value is accepted with a warning). This improves GAS compatibility. Partially addresses PR9248. llvm-svn: 201630
* MCAsmParser: change representation of MCAsmMacroParameterSaleem Abdulrasool2014-02-191-18/+22
| | | | | | | | | | Rather than using std::pair, create a structure to represent the type. This is a preliminary refactoring to enable required parameter handling. Additional state is needed to indicate required parameters. This has a minor side effect of improving readability by providing more accurate names compared to first and second. llvm-svn: 201629
* Now that llvm always does the right thing with private, use it.Rafael Espindola2014-02-191-11/+5
| | | | llvm-svn: 201625
* Avoid an infinite cycle with private linkage and -f{data|function}-sections.Rafael Espindola2014-02-192-5/+6
| | | | | | | | | | When outputting an object we check its section to find its name, but when looking for the section with -ffunction-section we look for the symbol name. Break the loop by requesting a name with the private prefix when constructing the section name. This matches the behavior before r201608. llvm-svn: 201622
* Fix PR18743.Rafael Espindola2014-02-1820-119/+206
| | | | | | | | | | | | | | | | | | | | | | | | The IR @foo = private constant i32 42 is valid, but before this patch we would produce an invalid MachO from it. It was invalid because it would use an L label in a section where the liker needs the labels in order to atomize it. One way of fixing it would be to just reject this IR in the backend, but that would not be very front end friendly. What this patch does is use an 'l' prefix in sections that we know the linker requires symbols for atomizing them. This allows frontends to just use private and not worry about which sections they go to or how the linker handles them. One small issue with this strategy is that now a symbol name depends on the section, which is not available before codegen. This is not a problem in practice. The reason is that it only happens with private linkage, which will be ignored by the non codegen users (llvm-nm and llvm-ar). llvm-svn: 201608
* Rename a DebugLoc variable to DbgLoc and a DataLayout to DL.Rafael Espindola2014-02-184-355/+384
| | | | | | This is quiet a bit less confusing now that TargetData was renamed DataLayout. llvm-svn: 201606
* Consistently check 'IsCode' when allocating sections in RuntimeDyld (viaLang Hames2014-02-182-2/+6
| | | | | | | | | | | | | | findOrEmitSection). Vaidas Gasiunas's patch, r201259, fixed one instance where we were always allocating sections as text. This patch fixes the remaining buggy call sites. No test case: This isn't breaking anything that I know of, it's just inconsistent. <rdar://problem/15943542> llvm-svn: 201605
* [AArch64] Expanded sin, cos, pow with FP vector types inputsAna Pazos2014-02-181-0/+10
| | | | llvm-svn: 201601
* Rename some member variables from TD to DL.Rafael Espindola2014-02-1815-114/+114
| | | | | | TargetData was renamed DataLayout back in r165242. llvm-svn: 201581
* XCore target: Handle common linkageRobert Lytton2014-02-182-7/+10
| | | | llvm-svn: 201563
* XCore target: addMemOperand as necessaryRobert Lytton2014-02-183-49/+109
| | | | | | | | | BuildMI instructions were not including MachineMemOperand information. This was discovered by 'SingleSource/Benchmarks/Stanford/Oscar' failing due to a FrameIndex load incorrectly being hoisted by postra-machine-licm. No other tests have been found to fail. llvm-svn: 201562
* XCore target: Fix llvm.eh.return and EH info register handlingRobert Lytton2014-02-184-47/+123
| | | | llvm-svn: 201561
* GlobalMerge: move "-global-merge" option to the pass itself.Tim Northover2014-02-182-6/+9
| | | | | | | It's rather odd to have the flag enabling and disabling this pass only affect a single target. llvm-svn: 201559
* X86: use vpsllvd (& friends) for 16-bit shifts on HaswellTim Northover2014-02-181-0/+14
| | | | llvm-svn: 201558
* Add PS prefix to some classes I missed in r201538.Craig Topper2014-02-181-2/+2
| | | | llvm-svn: 201551
* Add a bunch of OpSize32 tags to 64-bit mode only instructions to match their ↵Craig Topper2014-02-184-28/+31
| | | | | | 32-bit mode counterparts for cases where there is also a OpSize16 instruction. llvm-svn: 201550
* AVX-512: Fixed size of mask registersElena Demikhovsky2014-02-181-4/+6
| | | | llvm-svn: 201546
* Fix a typo about lowering AArch64 va_copy.Jiangning Liu2014-02-181-1/+1
| | | | llvm-svn: 201541
* Add an x86 prefix encoding for instructions that would decode to a different ↵Craig Topper2014-02-188-175/+175
| | | | | | instruction with 0xf2/f3/66 were in front of them, but don't themselves have a prefix. For now this doesn't change any bbehavior, but plan to use it to fix some bugs in the disassembler. llvm-svn: 201538
* Fix the arm assembler so that this malformed instruction:Kevin Enderby2014-02-171-1/+2
| | | | | | | | | | | | | | | | | | ldrd r6, r7 [r2, #15] simply gives an error and does not triggers an assertion. As Jim points out, the diagnostic is really strange here, but fixing that would be more complicated. The missing comma results in the parser expecting a construct like r2[2], which is the vector index thing the error message is talking about. That's not what the user intended, though, and there's nothing else in the instruction that looks at all like a vector. Yet more fallout from not having a real parser here and trying to do context-free generic matching for addressing modes. rdar://15097243 llvm-svn: 201531
* Add support for assigning to . in AsmParser.Anders Waldenborg2014-02-171-8/+6
| | | | | | | | | This is implemented by handling assignments to the '.' pseudo symbol as ".org" directives. Differential Revision: http://llvm-reviews.chandlerc.com/D2625 llvm-svn: 201530
* Fix diassembler handling of rex.b when mod=00/01/10 and bbb=101. Mod=00 ↵Craig Topper2014-02-171-4/+3
| | | | | | should ignore the base register entirely. Mod=01/10 should treat this as R13 plus displacment. Fixes PR18860. llvm-svn: 201507
* AVX-512: implemented zext fron i1 to i16Elena Demikhovsky2014-02-171-1/+3
| | | | llvm-svn: 201502
* fix for null VectorizedValue assertion in the SLP Vectorizer (in function ↵Gerolf Hoflehner2014-02-171-2/+4
| | | | | | vectorizeTree()). radar://16064178 llvm-svn: 201501
* MCAsmParser: better handling for named argumentsSaleem Abdulrasool2014-02-171-15/+56
| | | | | | | | | | | | | | | | | | | Until this point only macro definition with named parameters were parsed but the names were ignored. This adds support for using that information for named parameter instantiation. In order to support the full semantics of the keyword arguments, the arguments are no longer lazily initialised since the keyword arguments can be specified out of order and partially if they are defaulted. Prepopulate the arguments with the default value for any defaulted parameters, and then parse the specified arguments. This simplies some of the handling of the arguments in the inner loop since empty arguments simply increment the parameter index and move on. Note that keyword and positional arguments cannot be mixed. llvm-svn: 201499
* Use 16 byte stack alignment for NaCl on ARMMark Seaborn2014-02-163-6/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | NaCl's ARM ABI uses 16 byte stack alignment, so set that in ARMSubtarget.cpp. Using 16 byte alignment exposes an issue in code generation in which a varargs function leaves a 4 byte gap between the values of r1-r3 saved to the stack and the following arguments that were passed on the stack. (Previously, this code only needed to support 4 byte and 8 byte alignment.) With this issue, llc generated: varargs_func: sub sp, sp, #16 push {lr} sub sp, sp, #12 add r0, sp, #16 // Should be 20 stm r0, {r1, r2, r3} ldr r0, .LCPI0_0 // Address of va_list add r1, sp, #16 str r1, [r0] bl external_func Fix the bug by checking for "Align > 4". Also simplify the code by using OffsetToAlignment(), and update comments. Differential Revision: http://llvm-reviews.chandlerc.com/D2677 llvm-svn: 201497
* SCEVExpander: Try hard not to create derived induction variables in other loopsArnold Schwaighofer2014-02-161-25/+136
| | | | | | | | | | | | | | | | | | | During LSR of one loop we can run into a situation where we have to expand the start of a recurrence of a loop induction variable in this loop. This start value is a value derived of the induction variable of a preceeding loop. SCEV has cannonicalized this value to a different recurrence than the recurrence of the preceeding loop's induction variable (the type and/or step direction) has changed). When we come to instantiate this SCEV we created a second induction variable in this preceeding loop. This patch tries to base such derived induction variables of the preceeding loop's induction variable. This helps twolf on arm and seems to help scimark2 on x86. Reapply with a fix for the case of a value derived from a pointer. radar://15970709 llvm-svn: 201496
* Remove dead code, we already require cmake 2.8.8.Rafael Espindola2014-02-161-5/+0
| | | | llvm-svn: 201495
* Remove unnecessary typename.Rafael Espindola2014-02-161-6/+6
| | | | | | Thanks to Elena Demikhovsky for noticing. llvm-svn: 201494
* AVX-512: simpyfied BUILD_VECTOR for masks; fixed cmp/test sequenceElena Demikhovsky2014-02-162-70/+28
| | | | llvm-svn: 201487
* fixed typo in comment as my test commitGerolf Hoflehner2014-02-161-1/+1
| | | | llvm-svn: 201486
* Add a DIELoc class to cover the DW_FORM_exprloc set of expressionsEric Christopher2014-02-165-73/+180
| | | | | | | | | | | | | alongside DIEBlock and replace uses accordingly. Use DW_FORM_exprloc in DWARF4 and later code. Update testcases. Adding a DIELoc instead of using extra forms inside DIEBlock so that we can keep location expressions separate from other uses. No direct use at the moment, however, it's not a lot of code and using a separately named class keeps it somewhat more obvious what's going on in various locations. llvm-svn: 201481
* MCAsmParser: relax declaration parsingSaleem Abdulrasool2014-02-161-1/+4
| | | | | | | | The Linux kernel defines empty macros for compatibility with ARM UAL syntax. The comma after the name is optional, and if present can be safely lexed. This improves compatibility with the GNU assembler. llvm-svn: 201474
* ARM IAS: (partially) support .arch_extension directiveSaleem Abdulrasool2014-02-161-0/+82
| | | | | | | | | | | | This adds a partial implementation of the .arch_extension directive to the integrated ARM assembler. There are a number of limitations to this implementation arising from the target backend support rather than the implementation itself. Namely, iWMMXT (v1 and v2), Maverick, and XScale support is not present in the ARM backend. Currently, there is no check for A-class only (needed for virt), and no ARMv6k detection (needed for os and sec). The remainder of the extensions are fully supported. llvm-svn: 201471
* DebugInfo: Deduplicate entries in the fission address tableDavid Blaikie2014-02-153-18/+20
| | | | | | | | | | | | This broke in r185459 while TLS support was being generalized to handle non-symbol TLS representations. I thought about/tried having an enum rather than a bool to track the TLS-ness of the address table entry, but namespaces and naming seemed more hassle than it was worth for only one caller that needed to specify this. llvm-svn: 201469
* DwarfDebug: Remove dead code.David Blaikie2014-02-151-7/+3
| | | | llvm-svn: 201467
* Revert "SCEVExpander: Try hard not to create derived induction variables in ↵Arnold Schwaighofer2014-02-151-127/+25
| | | | | | | | other loops" This reverts commit r201465. It broke an arm bot. llvm-svn: 201466
* SCEVExpander: Try hard not to create derived induction variables in other loopsArnold Schwaighofer2014-02-151-25/+127
| | | | | | | | | | | | | | | | | During LSR of one loop we can run into a situation where we have to expand the start of a recurrence of a loop induction variable in this loop. This start value is a value derived of the induction variable of a preceeding loop. SCEV has cannonicalized this value to a different recurrence than the recurrence of the preceeding loop's induction variable (the type and/or step direction) has changed). When we come to instantiate this SCEV we created a second induction variable in this preceeding loop. This patch tries to base such derived induction variables of the preceeding loop's induction variable. This helps twolf on arm and seems to help scimark2 on x86. radar://15970709 llvm-svn: 201465
* Add opcode extension forms of MOV8ri/MOV16ri/MOV32ri.Craig Topper2014-02-151-0/+10
| | | | llvm-svn: 201463
* DebugInfo: Implement DW_AT_stmt_list for type unitsDavid Blaikie2014-02-143-2/+22
| | | | | | | | | Type units will share the statement list of their defining compile unit. This is a tradeoff that reduces .o debug info size at the cost of some linked debug info size (since the contents of those string tables won't be deduplicated along with the type unit) which seems right for now. llvm-svn: 201445
* DwarfUnit: Remove unnecessarily explicit/out of line virtual dtors.David Blaikie2014-02-142-6/+0
| | | | | | | These types have an out of line virtual function each (emitHeader at least) so they won't have weak vtables - no need for more than that. llvm-svn: 201444
* DwarfUnit: Remove unnecessary (void)t; that was previously used to suppress ↵David Blaikie2014-02-141-1/+0
| | | | | | -Wunused-member-variable llvm-svn: 201442
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