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* [NVPTX] Add support for addrspacecast in global variable initializers, ↵Justin Holewinski2014-04-092-4/+69
| | | | | | including emitting generic() when casting to address space 0. llvm-svn: 205906
* [NVPTX] Add query support for read-write images and managed variablesJustin Holewinski2014-04-094-3/+52
| | | | | | This also fixes a bug in the annotation cache where the cache will not be cleared between modules if multiple modules are compiled in the same process. llvm-svn: 205905
* Fix some doc and comment typosAlp Toker2014-04-0911-17/+17
| | | | llvm-svn: 205899
* [ARM64] Change SYS without a register to an alias to make disassembling more ↵Bradley Smith2014-04-093-22/+10
| | | | | | consistant. llvm-svn: 205898
* [ARM64] Correctly disassemble ISB operand as ISB not DBarrier.Bradley Smith2014-04-091-1/+6
| | | | llvm-svn: 205897
* [ARM64] Properly support both apple and standard syntax for FMOVBradley Smith2014-04-091-11/+10
| | | | llvm-svn: 205896
* [ARM64] Flag setting logical/add/sub immediate instructions don't use SP.Bradley Smith2014-04-091-4/+14
| | | | llvm-svn: 205895
* [ARM64] Conditional branches must always print their condition code, even AL.Bradley Smith2014-04-091-2/+1
| | | | llvm-svn: 205894
* [ARM64] Fix disassembly logic for extended loads/stores with 32-bit registers.Bradley Smith2014-04-091-2/+2
| | | | llvm-svn: 205893
* [ARM64] When printing a pre-indexed address with #0, the ', #0' is not optional.Bradley Smith2014-04-094-13/+67
| | | | llvm-svn: 205892
* [ARM64] Add missing shifted register MVN alias to ORNBradley Smith2014-04-092-0/+13
| | | | llvm-svn: 205891
* [ARM64] SXTW/UXTW are only valid aliases for 32-bit operations.Bradley Smith2014-04-091-1/+3
| | | | llvm-svn: 205890
* [ARM64] Fix canonicalisation of MOVs. MOV is too complex to be modelled by a ↵Bradley Smith2014-04-093-19/+93
| | | | | | dumb alias. llvm-svn: 205889
* [ARM64] Fixup ADR/ADRP parsing such that they accept immediates and all ↵Bradley Smith2014-04-092-41/+68
| | | | | | labels types llvm-svn: 205888
* [ARM64] Ensure sp is decoded as SP, not XZR in LD1 instructions.Bradley Smith2014-04-091-2/+2
| | | | llvm-svn: 205887
* [ARM64] Tighten up the special casing in emitting arithmetic extends. UXTW ↵Bradley Smith2014-04-091-2/+4
| | | | | | should only be translated when the instruction uses WSP, not SP. Vice versa for UXTX and 64-bit instructions. llvm-svn: 205886
* [ARM64] Rename LR to the UAL-compliant 'X30'.Bradley Smith2014-04-092-2/+2
| | | | llvm-svn: 205885
* [ARM64] Rename FP to the UAL-compliant 'X29'.Bradley Smith2014-04-092-2/+2
| | | | llvm-svn: 205884
* [ARM64] Add a PostEncoderMethod to FCMP - the Rm field should canonically be ↵Bradley Smith2014-04-092-1/+15
| | | | | | zero but should be decoded/disassembled with any value. llvm-svn: 205883
* [ARM64] SCVTF and FCVTZS/U are undefined if scale<5> == 0.Bradley Smith2014-04-092-8/+24
| | | | llvm-svn: 205882
* [ARM64] EXT and EXTR instructions on v8i8 and W regs respectively must have ↵Bradley Smith2014-04-091-1/+5
| | | | | | the top bit of their immediate clear. llvm-svn: 205881
* [ARM64] Scaled fixed-point FCVTZSs should also have bit 29 set to zero.Bradley Smith2014-04-091-1/+1
| | | | llvm-svn: 205880
* [ARM64] UBFM/BFM is undefined on w registers when imms<5> or immr<5> is 1.Bradley Smith2014-04-091-0/+6
| | | | llvm-svn: 205879
* [ARM64] Floating point to fixed point scaled conversions are only available ↵Bradley Smith2014-04-092-14/+22
| | | | | | on fcvtzs and fcvtzu. llvm-svn: 205878
* [ARM64] Port over the PostEncoderMethod fix for SMULH/UMULH from AArch64.Bradley Smith2014-04-092-1/+18
| | | | llvm-svn: 205877
* [ARM64] Add missing tlbi operands and error for extra/missing register on ↵Bradley Smith2014-04-092-0/+32
| | | | | | tlbi aliases. llvm-svn: 205876
* [ARM64] Rework system register parsing to overcome SPSel clash in MSR variants.Bradley Smith2014-04-092-141/+74
| | | | llvm-svn: 205875
* [ARM64] Port over the PostEncoderMethod from AArch64 for exclusive loads and ↵Bradley Smith2014-04-092-4/+32
| | | | | | stores, so the unused register fields are set to all-ones canonically but are recognised with any value. llvm-svn: 205874
* [ARM64] Use PStateMapper to ensure that MSRcpsr operands are validated ↵Bradley Smith2014-04-091-2/+7
| | | | | | during disassembly. llvm-svn: 205873
* [ARM64] Remove PrefetchOp and use ARM64PRFM instead.Bradley Smith2014-04-093-81/+14
| | | | llvm-svn: 205872
* [ARM64] Add WZR to isGPR32Register, since every use needs to check for this ↵Bradley Smith2014-04-091-4/+3
| | | | | | anyway. llvm-svn: 205871
* [ARM64] Remove ARM64SYS.Bradley Smith2014-04-091-665/+0
| | | | llvm-svn: 205870
* [ARM64] Move CPSRField and DBarrier operands over to AArch64-style ↵Bradley Smith2014-04-092-50/+45
| | | | | | disassembly and assembly. This removes the last users of namespace ARM64SYS. llvm-svn: 205869
* [ARM64] Switch the decoder, disassembler, instprinter and asmparser over to ↵Bradley Smith2014-04-097-347/+107
| | | | | | using AArch64-style system registers, and fix up test failures discovered in the process. llvm-svn: 205868
* [ARM64] Move ARM64BaseInfo.{cpp,h} into a Utils/ subdirectory, a la AArch64. ↵Bradley Smith2014-04-0917-13/+56
| | | | | | These files are required in the decoder, disassembler and parser, and a layering violation was imminent. llvm-svn: 205867
* [ARM64] Copy the named immediate operand mapping logic and enums from ↵Bradley Smith2014-04-093-0/+1822
| | | | | | AArch64. AArch64's named immediate mapping and parsing is much more advanced than ARM64's. No functionality change - they're currently living side by side while I switch uses over. llvm-svn: 205866
* [ARM64] Shifted register ALU ops are reserved if sf=0 and imm6<5>=1, and ↵Bradley Smith2014-04-091-9/+20
| | | | | | also (for add/sub only) if shift=11. llvm-svn: 205865
* [ARM64] Add support for NV condition code (exists only for valid ↵Bradley Smith2014-04-092-27/+11
| | | | | | assembly/disassembly, equivilant to AL) llvm-svn: 205864
* [ARM64] Add missing 1Q -> 1q vector kind aliasBradley Smith2014-04-091-0/+2
| | | | llvm-svn: 205863
* [ARM64] Add parsing for vector lists such as {v0.8b-v3.8b}Bradley Smith2014-04-091-19/+43
| | | | llvm-svn: 205862
* [ARM64] Correctly alias LSL to UXTW for 32bit instruction variants, rather ↵Bradley Smith2014-04-091-3/+3
| | | | | | than UXTX llvm-svn: 205861
* [ARM64] STRHro and STRBro were not being decoded at all.Bradley Smith2014-04-091-0/+2
| | | | llvm-svn: 205860
* [ARM64] MOVK with sf=0 and hw<1>=1 is unallocated. Shift amount for ADD/SUB ↵Bradley Smith2014-04-091-0/+6
| | | | | | instructions is unallocated if shift > 4. llvm-svn: 205859
* [ARM64] Register-offset loads and stores with the 'option' field equal to ↵Bradley Smith2014-04-091-14/+5
| | | | | | 00x or 10x are undefined. llvm-svn: 205858
* Revert "YAMLIO: Encode ambiguous hex strings explicitly"Filipe Cabecinhas2014-04-091-4/+1
| | | | | | | | This reverts commit r205839. It broke several tests in lld. llvm-svn: 205857
* SLPVectorizer: Only vectorize intrinsics whose operands are widened equallyArnold Schwaighofer2014-04-092-26/+10
| | | | | | | | | The vectorizer only knows how to vectorize intrinics by widening all operands by the same factor. Patch by Tyler Nowicki! llvm-svn: 205855
* AVX-512: insert element to mask vector; store i1 dataElena Demikhovsky2014-04-093-1/+77
| | | | | | | Implemented INSERT_VECTOR_ELT operation for v16i1 and v8i1 vectors; Implemented "store" for i1 type llvm-svn: 205850
* Re-commit: [mips] abs.[ds], and neg.[ds] should be allowed regardless of ↵Daniel Sanders2014-04-093-80/+7
| | | | | | | | | | | | | | | | | | | -enable-no-nans-fp-math Summary: They behave in accordance with the Has2008 and ABS2008 configuration bits of the processor which are used to select between the 1985 and 2008 versions of IEEE 754. In 1985 mode, these instructions are arithmetic (i.e. they raise invalid operation exceptions when given NaN), in 2008 mode they are non-arithmetic (i.e. they are copies). nmadd.[ds], and nmsub.[ds] are still subject to -enable-no-nans-fp-math because the ISA spec does not explicitly state that they obey Has2008 and ABS2008. Fixed the issue with the previous version of this patch (r205628). A pre-existing 'let Predicate =' statement was removing some predicates that were necessary for FP64 to behave correctly. Reviewers: matheusalmeida Reviewed By: matheusalmeida Differential Revision: http://llvm-reviews.chandlerc.com/D3274 llvm-svn: 205844
* YAMLIO: Encode ambiguous hex strings explicitlyDavid Majnemer2014-04-091-1/+4
| | | | | | | | | | YAMLIO would turn a BinaryRef into the string 0000000004000000. However, the leading zero causes parsers to interpret it as being an octal number instead of a hexadecimal one. Instead, escape such strings as needed. llvm-svn: 205839
* Delinearize: Extend informationin -analyze outputTobias Grosser2014-04-091-0/+4
| | | | llvm-svn: 205838
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