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* Remove unused Target argument from AsmParser construction methods.Jim Grosbach2011-08-163-6/+6
| | | | | | The argument is unused, and is a layering violation in any case. llvm-svn: 137735
* Instead of always leaving the work to the generic legalizer whenBruno Cardoso Lopes2011-08-161-0/+96
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | there is no support for native 256-bit shuffles, be more smart in some cases, for example, when you can extract specific 128-bit parts and use regular 128-bit shuffles for them. Example: For this shuffle: shufflevector <4 x i64> %a, <4 x i64> %b, <4 x i32> <i32 1, i32 0, i32 7, i32 6> This was expanded to: vextractf128 $1, %ymm1, %xmm2 vpextrq $0, %xmm2, %rax vmovd %rax, %xmm1 vpextrq $1, %xmm2, %rax vmovd %rax, %xmm2 vpunpcklqdq %xmm1, %xmm2, %xmm1 vpextrq $0, %xmm0, %rax vmovd %rax, %xmm2 vpextrq $1, %xmm0, %rax vmovd %rax, %xmm0 vpunpcklqdq %xmm2, %xmm0, %xmm0 vinsertf128 $1, %xmm1, %ymm0, %ymm0 ret Now we get: vshufpd $1, %xmm0, %xmm0, %xmm0 vextractf128 $1, %ymm1, %xmm1 vshufpd $1, %xmm1, %xmm1, %xmm1 vinsertf128 $1, %xmm1, %ymm0, %ymm0 llvm-svn: 137733
* Remove unnecessary version check.Devang Patel2011-08-161-2/+1
| | | | llvm-svn: 137728
* ARM .align NOP padding uses different encoding pre-ARMv6.Jim Grosbach2011-08-161-14/+37
| | | | | | Patch by Kristof Beyls and James Malloy. llvm-svn: 137723
* Revert r137562 because it caused PR10674Nadav Rotem2011-08-161-7/+0
| | | | llvm-svn: 137719
* Add a mechanism for optimisation plugins to register passes that all front ↵David Chisnall2011-08-161-0/+15
| | | | | | | | ends can use without needing to be aware of the plugin (or the plugin be aware of the front end). Before 3.0, I'd like to add a mechanism for automatically loading a set of plugins from a config file. API suggestions welcome... llvm-svn: 137717
* A few places where we want to skip the landingpad instruction for insertion.Bill Wendling2011-08-163-2/+8
| | | | llvm-svn: 137712
* Fix handling of double precision loads and stores when Mips1 is targeted. Akira Hatanaka2011-08-166-167/+73
| | | | | | | | | | | | | | | Mips1 does not support double precision loads or stores, therefore two single precision loads or stores must be used in place of these instructions. This patch treats double precision loads and stores as if they are legal instructions until MCInstLowering, instead of generating the single precision instructions during instruction selection or Prolog/Epilog code insertion. Without the changes made in this patch, llc produces code that has the same problem described in r137484 or bails out when MipsInstrInfo::storeRegToStackSlot or loadRegFromStackSlot is called before register allocation. llvm-svn: 137711
* Define function MipsMCInstLower::LowerOperand. Akira Hatanaka2011-08-162-25/+29
| | | | llvm-svn: 137707
* Add parameter Offset to MipsMCInstLower::LowerSymbolOperand. Akira Hatanaka2011-08-162-5/+5
| | | | llvm-svn: 137706
* Revert a bit of r137667; the logic in question can safely handle atomic ↵Eli Friedman2011-08-161-4/+4
| | | | | | load/store. llvm-svn: 137702
* After talking with Bill, it seems like the LandingPad handling here is likelyEli Friedman2011-08-161-4/+1
| | | | | | to be wrong (or at least somewhat suspect). Leave a FIXME for Bill. llvm-svn: 137694
* Minor comment fixes.Eli Friedman2011-08-162-5/+7
| | | | llvm-svn: 137693
* Update SimplifyCFG for atomic operations.Eli Friedman2011-08-151-10/+26
| | | | | | | | This commit includes a mention of the landingpad instruction, but it's not changing the behavior around it. I think the current behavior is correct, though. Bill, can you double-check that? llvm-svn: 137691
* Add comments and test for atomic load/store and mem2reg.Eli Friedman2011-08-151-0/+4
| | | | llvm-svn: 137690
* Refactor.Devang Patel2011-08-152-49/+68
| | | | llvm-svn: 137689
* Specify a necessary fixed bit for VLD3DUP, and otherwise rearrange the ↵Owen Anderson2011-08-153-20/+27
| | | | | | Thumb2 NEON decoding hooks to bring us closer to correctness. llvm-svn: 137686
* While I'm here, remove the "_alt" hacks to a series of INSERT_SUBREG andBruno Cardoso Lopes2011-08-151-15/+25
| | | | | | also add the AVX versions of the 128-bit patterns llvm-svn: 137685
* Reorder declarations of vmovmskp* and also put the necessary AVXBruno Cardoso Lopes2011-08-151-31/+35
| | | | | | | predicate and TB encoding fields. This fix the encoding for the attached testcase. This fixes PR10625. llvm-svn: 137684
* Continue to hoist uses of getCompileUnit() up. The goal is to get rid of ↵Devang Patel2011-08-152-21/+24
| | | | | | uses of getCompileUnit(). llvm-svn: 137683
* In places where it's using "getFirstNonPHI", skip the landingpad instruction ↵Bill Wendling2011-08-151-5/+8
| | | | | | if necessary. llvm-svn: 137679
* MCTargetAsmParser target match predicate support.Jim Grosbach2011-08-153-2/+5
| | | | | | | | Allow a target assembly parser to do context sensitive constraint checking on a potential instruction match. This will be used, for example, to handle Thumb2 IT block parsing. llvm-svn: 137675
* Add a finalize() hook, that'll let DIBuilder construct compile unit lazily.Devang Patel2011-08-151-0/+4
| | | | llvm-svn: 137673
* Don't sink the instruction to before a landingpad instruction.Bill Wendling2011-08-151-1/+1
| | | | llvm-svn: 137672
* This is somewhat déjà-vu, but avoid using getCompileUnit() as much as ↵Devang Patel2011-08-152-14/+14
| | | | | | possible. llvm-svn: 137668
* Update inter-procedural optimizations for atomic load/store.Eli Friedman2011-08-154-10/+16
| | | | llvm-svn: 137667
* Update instcombine for atomic load/store.Eli Friedman2011-08-153-31/+39
| | | | llvm-svn: 137664
* Refactor. Variables are part of compile unit so let CompileUnit create new ↵Devang Patel2011-08-154-123/+129
| | | | | | variable. llvm-svn: 137663
* Add some comments here because the lack of a check for volatile/atomic here ↵Eli Friedman2011-08-151-0/+4
| | | | | | is a bit unusual. llvm-svn: 137662
* Fix PR10656. It's only profitable to use 128-bit inserts and extractsBruno Cardoso Lopes2011-08-151-4/+6
| | | | | | | when AVX mode is one. Otherwise is just more work for the type legalizer. llvm-svn: 137661
* There is no need to maintain a set to keep track of variables that use ↵Devang Patel2011-08-152-8/+2
| | | | | | location expressions. In such cases, AT_location attribute's value will be a label. llvm-svn: 137659
* Fix warning.Devang Patel2011-08-152-2/+2
| | | | llvm-svn: 137658
* Simplify. Let DbgVariable keep track of variable's DBG_VALUE machine ↵Devang Patel2011-08-152-55/+24
| | | | | | instruction. llvm-svn: 137656
* Duncan pointed out that the LandingPadInst might read memory. (It might alsoBill Wendling2011-08-153-6/+4
| | | | | | write to memory.) Marking it as such makes some checks for immobility go away. llvm-svn: 137655
* Fix llvm::CloneModule to correctly clone globals. Patch per bug report by ↵Eli Friedman2011-08-151-14/+13
| | | | | | Simon Moll on llvmdev. llvm-svn: 137654
* Fix predicates methods on Instruction to handle atomic load/store correctly.Eli Friedman2011-08-151-7/+15
| | | | llvm-svn: 137652
* Misc analysis passes that need to be aware of atomic load/store.Eli Friedman2011-08-154-19/+50
| | | | llvm-svn: 137650
* Atomic load/store support in LICM.Eli Friedman2011-08-152-10/+18
| | | | llvm-svn: 137648
* Enforce the constraint that Rt must be even on LDRD/STRD instructions in ARM ↵Owen Anderson2011-08-151-0/+15
| | | | | | | | mode. Update tests to reflect this fact. Patch by James Molloy. llvm-svn: 137647
* Remove dead classes.Owen Anderson2011-08-151-33/+0
| | | | llvm-svn: 137643
* The "landingpad" instruction will never be "trivially" dead.Bill Wendling2011-08-151-0/+4
| | | | llvm-svn: 137642
* Fix incorrect encoding of UMAAL and friends. Patch by James Molloy.Owen Anderson2011-08-151-2/+2
| | | | llvm-svn: 137641
* Simplify mapping to variable from its abstract variable info.Devang Patel2011-08-152-29/+18
| | | | | | When a variable is inlined multiple places, abstract variable keeps name, location, type etc.. info and all other concreate instances of the variable directly refers to abstract variable. llvm-svn: 137637
* Fix decoding LDRSB and LDRSH in Thumb1 mode. Patch by James Molloy.Owen Anderson2011-08-151-6/+7
| | | | llvm-svn: 137636
* Fix problems decoding the to/from-lane NEON memory instructions, and add a ↵Owen Anderson2011-08-152-4/+486
| | | | | | comprehensive NEON decoding testcase. llvm-svn: 137635
* Refactor.Devang Patel2011-08-152-5/+11
| | | | llvm-svn: 137632
* Refactor.Devang Patel2011-08-152-15/+9
| | | | llvm-svn: 137631
* Don't try to sink the landingpad instruction. It's immobile.Bill Wendling2011-08-151-2/+3
| | | | llvm-svn: 137629
* The landingpad instruction isn't loop-invariant.Bill Wendling2011-08-151-0/+3
| | | | llvm-svn: 137628
* Mark the SCC as "might unwind" if we run into a 'resume' instruction.Bill Wendling2011-08-151-2/+3
| | | | llvm-svn: 137627
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