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* [codeview] Set the Nested and Scoped ClassOptions based on the scope chainReid Kleckner2016-07-021-12/+31
| | | | | | These are set on both the declaration record and the definition record. llvm-svn: 274410
* LoadStoreVectorizer: Fix warning about extra semicolonMatt Arsenault2016-07-011-2/+2
| | | | llvm-svn: 274406
* TII: Fix inlineasm size counting comments as instsMatt Arsenault2016-07-011-7/+11
| | | | | | | The main problem was counting comments on their own line as instructions. llvm-svn: 274405
* PeepholeOptimizer: Relax assertMatt Arsenault2016-07-011-2/+4
| | | | | | Allow implicit defs llvm-svn: 274402
* [CodeView] Include the offset of nested membersDavid Majnemer2016-07-011-4/+5
| | | | | | | | | | | | | Given something like: struct S { int a; struct { int b; }; }; We would fail to give 'b' offset 4. Instead, we would give it the offset it has inside of it's struct. llvm-svn: 274400
* [CodeView] Pretty print anonymous scopesDavid Majnemer2016-07-011-14/+31
| | | | | | | | A namespace without a name should be written out as `anonymous namespace' while a tag type without a name should be written out as <unnamed-tag>. llvm-svn: 274399
* AMDGPU: Add feature for unaligned accessMatt Arsenault2016-07-015-12/+32
| | | | llvm-svn: 274398
* AMDGPU: Expand unaligned accesses earlyMatt Arsenault2016-07-012-21/+48
| | | | | | | | Due to visit order problems, in the case of an unaligned copy the legalized DAG fails to eliminate extra instructions introduced by the expansion of both unaligned parts. llvm-svn: 274397
* [msan] Fix __msan_maybe_ for non-standard type sizes.Evgeniy Stepanov2016-07-011-1/+1
| | | | | | | | | | | Fix incorrect calculation of the type size for __msan_maybe_warning_N call that resulted in an invalid (narrowing) zext instruction and "Assertion `castIsValid(op, S, Ty) && "Invalid cast!"' failed." Only happens in very large functions (with more than 3500 MSan checks) operating on integer types that are not power-of-two. llvm-svn: 274395
* AMDGPU: Improve load/store of illegal types.Matt Arsenault2016-07-013-113/+102
| | | | | | | | | | There was a combine before to handle the simple copy case. Split this into handling loads and stores separately. We might want to change how this handles some of the vector extloads, since this can result in large code size increases. llvm-svn: 274394
* [codeview] Don't record UDTs for anonymous structsReid Kleckner2016-07-011-0/+4
| | | | | | | | MSVC makes up names for these anonymous structs, but we don't (yet). Eventually Clang should use getTypedefNameForAnonDecl() to put some name in the debug info, and we can update the test case when that happens. llvm-svn: 274391
* Address two correctness issues in LoadStoreVectorizerAlina Sbirlea2016-07-011-3/+10
| | | | | | | | | | | | | | Summary: GetBoundryInstruction returns the last instruction as the instruction which follows or end(). Otherwise the last instruction in the boundry set is not being tested by isVectorizable(). Partially solve reordering of instructions. More extensive solution to follow. Reviewers: tstellarAMD, llvm-commits, jlebar Subscribers: escha, arsenm, mzolotukhin Differential Revision: http://reviews.llvm.org/D21934 llvm-svn: 274389
* [Hexagon] Revert r274381: that was actually wrongKrzysztof Parzyszek2016-07-011-1/+1
| | | | llvm-svn: 274384
* [Hexagon] Use MachineOperand::readsReg instead of isUseKrzysztof Parzyszek2016-07-011-1/+1
| | | | llvm-svn: 274381
* [pdb] Check the display name for <unnamed-tag>, not the linkage nameReid Kleckner2016-07-011-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | This issue was encountered on libcmt.pdb, which has a type record that looks like this: Struct (0x1094) { TypeLeafKind: LF_STRUCTURE (0x1505) MemberCount: 3 Properties [ (0x200) HasUniqueName (0x200) ] FieldList: <field list> (0x1093) DerivedFrom: 0x0 VShape: 0x0 SizeOf: 4 Name: <unnamed-tag> LinkageName: .?AU<unnamed-tag>@@ } The checks for startswith/endswith "<unnamed-tag>" should look at the display name, not the linkage name. llvm-svn: 274376
* [codeview] Assert that our CV type records are validReid Kleckner2016-07-011-3/+27
| | | | | | | | | | | We were asserting that our type records were valid when emitting assembly, but not when emitting an object file. I've been seeing lots of LNK1285 errors (corrupt PDB) during incremental debug self-host builds with the MSVC linker, and hopefully this will catch some of them earlier. llvm-svn: 274373
* AMDGPU/SI: Enable testing several variants for si schedulerMatt Arsenault2016-07-011-2/+2
| | | | | | | | | | Enable testing different scheduling variants if sgpr usage is very high. It was previously disabled because of a bug in handleMove, but it has been fixed since. Patch by Axel Davy llvm-svn: 274372
* Revert r274347 "[ARM] Refactor Thumb2 mul instruction descs"Hans Wennborg2016-07-011-144/+327
| | | | | | This caused PR28387: Assertion "#operands for dag node doesn't match .td file!" llvm-svn: 274367
* CodeGen: Use MachineInstr& in RegisterCoalescer, NFCDuncan P. N. Exon Smith2016-07-011-38/+37
| | | | | | | Remove a few more implicit iterator to pointer conversions by preferring MachineInstr&. llvm-svn: 274363
* fix documentation comments; NFCSanjay Patel2016-07-011-13/+12
| | | | llvm-svn: 274362
* CodeGen: Avoid implicit conversions in TargetInstrInfo, NFCDuncan P. N. Exon Smith2016-07-011-2/+2
| | | | | | | Avoid implicit conversions from MachineBasicBlock::iterator to MachineInstr* in TargetInstrInfo. llvm-svn: 274361
* CodeGen: Use MachineInstr& in ScheduleDAGIntrs, NFCDuncan P. N. Exon Smith2016-07-011-43/+43
| | | | | | | | | | | | | Use MachineInstr& to avoid implicit conversions from MachineBasicBlock::iterator to MachineInstr*. In one case, this could use a range-based for loop, but the other loops iterated in reverse order. One of the reverse-loops checked the MachineInstr* for nullptr, a condition that is provably unreachable. (And even if my proof has a flaw, UBSan would catch the bug.) llvm-svn: 274360
* Do not count debug instructions when counting number of uses to reorder ↵Dehao Chen2016-07-011-0/+2
| | | | | | | | | | | | | | frame objects. Summary: The code generation should be independent of the debug info. Reviewers: zansari, davidxl, mkuper, majnemer Subscribers: majnemer, llvm-commits Differential Revision: http://reviews.llvm.org/D21911 llvm-svn: 274357
* CodeGen: Avoid iterator conversion in UnreachableBlockElim, NFCDuncan P. N. Exon Smith2016-07-011-3/+1
| | | | | | | Avoid an unnecessary (and implicit) iterator to pointer conversion in UnreachableBlockElim by using the post-increment operator. llvm-svn: 274355
* CodeGen: Use MachineInstr& in SlotIndexes.cpp, NFCDuncan P. N. Exon Smith2016-07-011-18/+13
| | | | | | | Avoid implicit conversions from iterator to pointer by preferring MachineInstr& and using range-based for loops. llvm-svn: 274354
* CodeGen: Use MachineInstr& in RegAllocFast, NFCDuncan P. N. Exon Smith2016-07-011-31/+33
| | | | | | | | | Use MachineInstr& instead of MachineInstr* in RegAllocFast to avoid implicit conversions from MachineInstrBundleIterator. RAFast::spillAll and RAFast::spillVirtReg still take iterators, since their argument may be an end iterator from MachineBasicBlock::getFirstTerminator. llvm-svn: 274353
* [ARM] Refactor Thumb2 mul instruction descsSam Parker2016-07-011-327/+144
| | | | | | | | | No functional changes. Just created wrapper classes around the 3 and 4 reg mult and mac instruction classes. Differential Revision: http://reviews.llvm.org/D21549 llvm-svn: 274347
* function_refify. NFC.Benjamin Kramer2016-07-011-8/+5
| | | | | | While there use emplace_back to create an expensive pair. llvm-svn: 274344
* Resubmit r268719 - AMDGPU/SI: Add amdgpu_kernel calling convention. Part 2.Nikolay Haustov2016-07-012-5/+10
| | | | | | | | | | | | | | | | | | | This was reverted in r268740 because of problems with corresponding Clang change. Clang change was updated and resubmitted in r274220. Check calling convention in AMDGPUMachineFunction::isKernel This will be used for AMDGPU_HSA_KERNEL symbol type in output ELF. Also, in the future unused non-kernels may be optimized. Reviewers: tstellarAMD, arsenm Subscribers: arsenm, joker.eph, llvm-commits Differential Revision: http://reviews.llvm.org/D19917 llvm-svn: 274341
* [AMDGPU] Assembler: support SDWA for VOPC instructionsSam Kolton2016-07-013-45/+113
| | | | | | | | | | | | Summary: dst_sel and dst_unused disabled for VOPC as they have no effect on result Reviewers: artem.tamazov, tstellarAMD, vpykhtin Subscribers: arsenm, kzhuravl Differential Revision: http://reviews.llvm.org/D21376 llvm-svn: 274340
* Update libdeps; AMDGPUCodeGen requires LLVMVectorize.NAKAMURA Takumi2016-07-011-1/+1
| | | | llvm-svn: 274339
* [CodeGen] Cleanup getVectorShuffle a bit to take advantage of its new ↵Craig Topper2016-07-011-16/+16
| | | | | | ArrayRef argument and its begin/end iterators. Also use 'int' type for number of elements and loop iterators to remove several typecasts. No functional change intended. llvm-svn: 274338
* [CodeGen,Target] Remove the version of DAG.getVectorShuffle that takes a ↵Craig Topper2016-07-019-61/+59
| | | | | | | | pointer to a mask array. Convert all callers to use the ArrayRef version. No functional change intended. For the most part this simplifies all callers. There were two places in X86 that needed an explicit makeArrayRef to shorten a statically sized array. llvm-svn: 274337
* Add support for allowing us to create uniquely identified "COMDAT" or "ELFEric Christopher2016-07-012-11/+17
| | | | | | | | | | | | | Group" sections while lowering. In particular, for ELF sections this is useful for creating function-specific groups that get merged into the same named section. Also use const Twine& instead of StringRef for the getELF functions while we're here. Differential Revision: http://reviews.llvm.org/D21743 llvm-svn: 274336
* 80-column and comment fixups.Eric Christopher2016-07-011-5/+8
| | | | llvm-svn: 274335
* [PM] refactor LoopAccessInfo code part-2Xinliang David Li2016-07-015-25/+25
| | | | | | Differential Revision: http://reviews.llvm.org/D21636 llvm-svn: 274334
* [MBP] method interface cleanupXinliang David Li2016-07-011-25/+20
| | | | | | | Make worklist and ehworklist member of the class so that they don't need to be passed around. llvm-svn: 274333
* AMDGPU: Add option to run the load/store vectorizerMatt Arsenault2016-07-011-0/+16
| | | | llvm-svn: 274329
* [codeview] Add DISubprogram::ThisAdjustmentReid Kleckner2016-07-018-65/+93
| | | | | | | | | | | | | | | | | | | | | Summary: This represents the adjustment applied to the implicit 'this' parameter in the prologue of a virtual method in the MS C++ ABI. The adjustment is always zero unless multiple inheritance is involved. This increases the size of DISubprogram by 8 bytes, unfortunately. The adjustment really is a signed 32-bit integer. If this size increase is too much, we could probably win it back by splitting out a subclass with info specific to virtual methods (virtuality, vindex, thisadjustment, containingType). Reviewers: aprantl, dexonsmith Subscribers: aaboud, amccarth, llvm-commits Differential Revision: http://reviews.llvm.org/D21614 llvm-svn: 274325
* LoadStoreVectorizer: improvements: better pointer analysisMatt Arsenault2016-07-011-5/+26
| | | | | | | | | If OpB has an ADD NSW/NUW, we can use that to prove that adding 1 to OpA won't wrap if OpA + 1 == OpB. Patch by Fiona Glaser llvm-svn: 274324
* LoadStoreVectorizer: Don't increase alignment with no align setMatt Arsenault2016-07-011-2/+18
| | | | | | | If no alignment was set on the load/stores, it would vectorize to the new type even though this increases the default alignment. llvm-svn: 274323
* LoadStoreVectorizer: Check TTI for vec reg bit widthMatt Arsenault2016-07-011-16/+28
| | | | llvm-svn: 274322
* LoadStoreVectorizer: Fix assert when merging pointer opsMatt Arsenault2016-07-011-3/+17
| | | | | | | This needs to use inttoptr/ptrtoint if combining an int and pointer load. If a pointer is used always do an integer load. llvm-svn: 274321
* Revert "code hoisting pass based on GVN"Duncan P. N. Exon Smith2016-07-015-748/+0
| | | | | | | | | | | | This reverts commit r274305, since it breaks self-hosting: http://lab.llvm.org:8080/green/job/clang-stage1-configure-RA_build/22349/ http://lab.llvm.org:8011/builders/clang-x86_64-linux-selfhost-modules/builds/17232 Note that the blamelist on lab.llvm.org:8011 is incorrect. The previous build was r274299, but somehow r274305 wasn't included in the blamelist: http://lab.llvm.org:8011/builders/clang-x86_64-linux-selfhost-modules llvm-svn: 274320
* CodeGen: Use MachineInstr& in LiveVariables API, NFCDuncan P. N. Exon Smith2016-07-017-56/+56
| | | | | | | | | Change all the methods in LiveVariables that expect non-null MachineInstr* to take MachineInstr& and update the call sites. This clarifies the API, and designs away a class of iterator to pointer implicit conversions. llvm-svn: 274319
* LoadStoreVectorizer: Use AA metadataMatt Arsenault2016-07-011-8/+5
| | | | | | | This was not passing the full instruction with metadata to the alias query. llvm-svn: 274318
* CodeGen: Remove implicit iterator conversions in PHIElimination, NFCDuncan P. N. Exon Smith2016-07-011-7/+7
| | | | llvm-svn: 274317
* CodeGen: Use MachineInstr& in PostRASchedulerList, NFCDuncan P. N. Exon Smith2016-07-011-6/+6
| | | | | | Remove another unnecessary iterator to pointer conversion. llvm-svn: 274315
* AMDGPU: Implement getLoadStoreVecRegBitWidthMatt Arsenault2016-07-012-0/+23
| | | | llvm-svn: 274312
* CodeGen: Use MachineInstr& in PostRAHazardRecognizer, NFCDuncan P. N. Exon Smith2016-07-011-6/+4
| | | | | | | | Convert a loop to a range-based for, using MachineInstr& instead of MachineInstr* and removing an implicit conversion from iterator to pointer. llvm-svn: 274311
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