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* Allow known and unknown probabilities coexist in MBB's successor list.Cong Hou2015-12-011-8/+17
| | | | | | | | | | Previously it is not allowed for each MBB to have successors with both known and unknown probabilities. However, this may be too strict as at this stage we could not always guarantee that. It is better to remove this restriction now, and I will work on validating MBB's successors' probabilities first (for example, check if the sum is approximate one). llvm-svn: 254402
* [AArch64] Add ARMv8.2-A Statistical Profiling ExtensionOliver Stannard2015-12-019-1/+170
| | | | | | | | | | | | The Statistical Profiling Extension is an optional extension to ARMv8.2-A. Since it is an optional extension, I have added the FeatureSPE subtarget feature to control it. The assembler-visible parts of this extension are the new "psb csync" instruction, which is equivalent to "hint #17", and a number of system registers. Differential Revision: http://reviews.llvm.org/D15021 llvm-svn: 254401
* [ARM] Add ARMv8.2-A to TargetParserOliver Stannard2015-12-016-1/+20
| | | | | | | | | | | | Add ARMv8.2-A to TargetParser, so that it can be used by the clang command-line options and the .arch directive. Most testing of this will be done in clang, checking that the command-line options that this enables work. Differential Revision: http://reviews.llvm.org/D15037 llvm-svn: 254400
* [ARM] Add subtarget features for ARMv8.2-AOliver Stannard2015-12-014-3/+20
| | | | | | | | | | | | | | This adds subtarget features for ARMv8.2-A, which builds on (and requires the features from) ARMv8.1-A. Most assembler-visible features of ARMv8.2-A are system instructions, and are all required parts of the architecture, so just depend on the HasV8_2aOps subtarget feature. There is also one large, optional feature, which adds 16-bit floating point versions of all existing floating-point instructions (VFP and SIMD), this is represented by the FeatureFullFP16 subtarget feature. Differential Revision: http://reviews.llvm.org/D15036 llvm-svn: 254399
* Introduce a range version of std::find, and use in SCEVSanjoy Das2015-12-011-2/+1
| | | | | | | | | | Reviewers: dblaikie, pcc Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D15064 llvm-svn: 254391
* Introduce a range version of std::any_of, and use it in SCEVSanjoy Das2015-12-011-4/+3
| | | | | | | | | | Reviewers: dblaikie, pcc Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D15063 llvm-svn: 254390
* [X86] Fix patterns for memory forms of FP FSUBR and FDIVR. They need to have ↵Craig Topper2015-12-011-39/+69
| | | | | | | | memory on the left hand side of the fsub/fdiv operations in their patterns. Not sure how to test this. I noticed by inspection in the isel tables where the same pattern tried to produce DIV and DIVR or SUB and SUBR. llvm-svn: 254388
* [X86] Use range-based for loops. NFCCraig Topper2015-12-011-6/+6
| | | | llvm-svn: 254387
* [X86] Use array_lengthof instead of calculating manually. Also change index ↵Craig Topper2015-12-011-7/+7
| | | | | | types to size_t to match. llvm-svn: 254386
* [Hexagon] Use std::begin() and std::end() instead of doing the same ↵Craig Topper2015-12-011-2/+1
| | | | | | manually. NFC llvm-svn: 254385
* [Hexagon] Use array_lengthof and const correct and type correct the array ↵Craig Topper2015-12-011-7/+5
| | | | | | and array size. NFC llvm-svn: 254384
* Use array_lengthof instead of manually calculating it. NFCCraig Topper2015-12-011-2/+2
| | | | llvm-svn: 254383
* [Hexagon] Use ArrayRef to avoid needing to calculate an array size. ↵Craig Topper2015-12-011-16/+11
| | | | | | Interestingly the original code may have had a bug because it was passing the byte size of a uint16_t array instead of the number of entries. llvm-svn: 254382
* [ARM] Use range-based for loops to avoid the need for calculating an array ↵Craig Topper2015-12-011-6/+5
| | | | | | size that I would have otherwise cconverted to array_lengthof. NFC llvm-svn: 254381
* Use array_lengthof instead of manually calculating it. NFCCraig Topper2015-12-011-3/+2
| | | | llvm-svn: 254380
* [Windows] Partially revert r254363 until I can test the right fix.Davide Italiano2015-12-011-2/+6
| | | | | | Reported by: David Blaikie llvm-svn: 254378
* Replace all weight-based interfaces in MBB with probability-based ↵Cong Hou2015-12-0115-318/+207
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | interfaces, and update all uses of old interfaces. (This is the second attempt to submit this patch. The first caused two assertion failures and was reverted. See https://llvm.org/bugs/show_bug.cgi?id=25687) The patch in http://reviews.llvm.org/D13745 is broken into four parts: 1. New interfaces without functional changes (http://reviews.llvm.org/D13908). 2. Use new interfaces in SelectionDAG, while in other passes treat probabilities as weights (http://reviews.llvm.org/D14361). 3. Use new interfaces in all other passes. 4. Remove old interfaces. This patch is 3+4 above. In this patch, MBB won't provide weight-based interfaces any more, which are totally replaced by probability-based ones. The interface addSuccessor() is redesigned so that the default probability is unknown. We allow unknown probabilities but don't allow using it together with known probabilities in successor list. That is to say, we either have a list of successors with all known probabilities, or all unknown probabilities. In the latter case, we assume each successor has 1/N probability where N is the number of successors. An assertion checks if the user is attempting to add a successor with the disallowed mixed use as stated above. This can help us catch many misuses. All uses of weight-based interfaces are now updated to use probability-based ones. Differential revision: http://reviews.llvm.org/D14973 llvm-svn: 254377
* RegisterPressure: If we do not collect dead defs the list must be emptyMatthias Braun2015-12-011-5/+1
| | | | llvm-svn: 254372
* RegisterPressure: Remove support for recede()/advance() at MBB boundariesMatthias Braun2015-12-011-18/+5
| | | | | | | Nobody was checking the returnvalue of recede()/advance() so we can simply replace this code with asserts. llvm-svn: 254371
* RegisterPressure: Split RegisterOperands analysis code from result object; NFCMatthias Braun2015-12-011-43/+60
| | | | | | | This is in preparation to expose the RegisterOperands class as RegisterPressure API. llvm-svn: 254368
* Revert r254348: "Replace all weight-based interfaces in MBB with ↵Hans Wennborg2015-12-0115-202/+316
| | | | | | | | | | probability-based interfaces, and update all uses of old interfaces." and the follow-up r254356: "Fix a bug in MachineBlockPlacement that may cause assertion failure during BranchProbability construction." Asserts were firing in Chromium builds. See PR25687. llvm-svn: 254366
* [Windows] Follow-up r254363, remove return.Davide Italiano2015-12-011-3/+1
| | | | llvm-svn: 254364
* [Windows] Simplify assertion code. NFC.Davide Italiano2015-12-012-8/+3
| | | | llvm-svn: 254363
* Squelch unused variable warning in SIRegisterInfo.cpp.Matt Arsenault2015-12-011-1/+2
| | | | | | Patch by Justin Lebar llvm-svn: 254362
* Fix a bug in MachineBlockPlacement that may cause assertion failure during ↵Cong Hou2015-12-011-3/+7
| | | | | | | | BranchProbability construction. The root cause is the rounding behavior in BranchProbability construction. We may consider to use truncation instead in the future. llvm-svn: 254356
* [safestack] Protect byval function arguments.Evgeniy Stepanov2015-12-012-48/+117
| | | | | | | Detect unsafe byval function arguments and move them to the unsafe stack. llvm-svn: 254353
* Extend debug info for function parameters in SDAG.Evgeniy Stepanov2015-12-011-16/+11
| | | | | | | | | | | | | SDAG currently can emit debug location for function parameters when an llvm.dbg.declare points to either a function argument SSA temp, or to an AllocaInst. This change extends this logic by adding a fallback case when neither of the above is true. This is required for SafeStack, which may copy the contents of a byval function argument into something that is not an alloca, and then describe the target as the new location of the said argument. llvm-svn: 254352
* [safestack] Fix handling of array allocas.Evgeniy Stepanov2015-12-011-5/+17
| | | | | | | | The current code does not take alloca array size into account and, as a result, considers any access past the first array element to be unsafe. llvm-svn: 254350
* Replace all weight-based interfaces in MBB with probability-based ↵Cong Hou2015-12-0115-316/+198
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | interfaces, and update all uses of old interfaces. The patch in http://reviews.llvm.org/D13745 is broken into four parts: 1. New interfaces without functional changes (http://reviews.llvm.org/D13908). 2. Use new interfaces in SelectionDAG, while in other passes treat probabilities as weights (http://reviews.llvm.org/D14361). 3. Use new interfaces in all other passes. 4. Remove old interfaces. This patch is 3+4 above. In this patch, MBB won't provide weight-based interfaces any more, which are totally replaced by probability-based ones. The interface addSuccessor() is redesigned so that the default probability is unknown. We allow unknown probabilities but don't allow using it together with known probabilities in successor list. That is to say, we either have a list of successors with all known probabilities, or all unknown probabilities. In the latter case, we assume each successor has 1/N probability where N is the number of successors. An assertion checks if the user is attempting to add a successor with the disallowed mixed use as stated above. This can help us catch many misuses. All uses of weight-based interfaces are now updated to use probability-based ones. Differential revision: http://reviews.llvm.org/D14973 llvm-svn: 254348
* This reverts commit r254336 and r254344.Rafael Espindola2015-11-302-79/+80
| | | | | | They broke a bot and I am debugging why. llvm-svn: 254347
* Disable a consistency check.Rafael Espindola2015-11-301-5/+1
| | | | | | Trying to figure out why it fails on a bot but passes locally. llvm-svn: 254344
* [X86][FMA4] Prefer FMA4 to FMASimon Pilgrim2015-11-301-3/+4
| | | | | | | | | | | | | | | | We currently output FMA instructions on targets which support both FMA4 + FMA (i.e. later Bulldozer CPUS bdver2/bdver3/bdver4). This patch flips this so FMA4 is preferred; this is for several reasons: 1 - FMA4 is non-destructive reducing the need for mov instructions. 2 - Its more straighforward to commute and fold inputs (although the recent work on FMA has reduced this difference). 3 - All supported targets have FMA4 performance equal or better to FMA - Piledriver (bdver2) in particular has half the throughput when executing FMA instructions. Its looks like no future AMD processor lines will support FMA4 after the Bulldozer series so we're not causing problems for later CPUs. Differential Revision: http://reviews.llvm.org/D14997 llvm-svn: 254339
* Start deciding earlier what to link.Rafael Espindola2015-11-302-80/+83
| | | | | | | | | | | | | | | | | | | | | | A traditional linker is roughly split in symbol resolution and "copying stuff". The two tasks are badly mixed in lib/Linker. This starts splitting them apart. With this patch there are no direct call to linkGlobalValueBody or linkGlobalValueProto. Everything is linked via WapValue. This also includes a few fixes: * A GV goes undefined if the comdat is dropped (comdat11.ll). * We error if an internal GV goes undefined (comdat13.ll). * We don't link an unused comdat. The first two match the behavior of an ELF linker. The second one is equivalent to running globaldce on the input. llvm-svn: 254336
* Have 'optnone' respect the -fast-isel=false option.Paul Robinson2015-11-302-4/+9
| | | | | | | | This is primarily useful for debugging optnone v. ISel issues. Differential Revision: http://reviews.llvm.org/D14792 llvm-svn: 254335
* AMDGPU: Fix unused functionMatt Arsenault2015-11-301-5/+0
| | | | llvm-svn: 254333
* AMDGPU: Error if too many user SGPRs usedMatt Arsenault2015-11-302-0/+8
| | | | llvm-svn: 254332
* AMDGPU: Rework how private buffer passed for HSAMatt Arsenault2015-11-309-102/+594
| | | | | | | | | | | | | | | | If we know we have stack objects, we reserve the registers that the private buffer resource and wave offset are passed and use them directly. If not, reserve the last 5 SGPRs just in case we need to spill. After register allocation, try to pick the next available registers instead of the last SGPRs, and then insert copies from the inputs to the reserved registers in the progloue. This also only selectively enables all of the input registers which are really required instead of always enabling them. llvm-svn: 254331
* AMDGPU: Rename enums to be consistent with HSA code object terminologyMatt Arsenault2015-11-305-50/+49
| | | | llvm-svn: 254330
* AMDGPU: Remove SIPrepareScratchRegsMatt Arsenault2015-11-3012-249/+123
| | | | | | | | | | | | | | | | | | | | | | It does not work because of emergency stack slots. This pass was supposed to eliminate dummy registers for the spill instructions, but the register scavenger can introduce more during PrologEpilogInserter, so some would end up left behind if they were needed. The potential for spilling the scratch resource descriptor and offset register makes doing something like this overly complicated. Reserve registers to use for the resource descriptor and use them directly in eliminateFrameIndex. Also removes creating another scratch resource descriptor when directly selecting scratch MUBUF instructions. The choice of which registers are reserved is temporary. For now it attempts to pick the next available registers after the user and system SGPRs. llvm-svn: 254329
* AMDGPU: Use assert zext for workgroup sizesMatt Arsenault2015-11-302-10/+24
| | | | llvm-svn: 254328
* [ARM] For old thumb ISA like v4t, we cannot use PC directly in pop.Quentin Colombet2015-11-301-18/+5
| | | | | | Fix the epilogue emission to account for that. llvm-svn: 254325
* [SimplifyLibCalls] Transform log(exp2(y)) to y*log(2) under fast-math.Davide Italiano2015-11-301-1/+9
| | | | llvm-svn: 254317
* [X86] Add RIP to GR64_TCW64David Majnemer2015-11-301-1/+1
| | | | | | | | | The MachineVerifier wants to check that the register operands of an instruction belong to the instruction's register class. RIP-relative control flow instructions violated this by referencing RIP. While this was fixed for SysV, it was never fixed for Win64. llvm-svn: 254315
* Enable shrink wrapping for PPC64Kit Barton2015-11-301-6/+14
| | | | | | | | | | | Re-enable shrink wrapping for PPC64 Little Endian. One minor modification to PPCFrameLowering::findScratchRegister was necessary to handle fall-thru blocks (blocks with no terminator) correctly. Tested with all LLVM test, clang tests, and the self-hosting build, with no problems found. PHabricator: http://reviews.llvm.org/D14778 llvm-svn: 254314
* Fix another llvm.ctors merging bug.Rafael Espindola2015-11-301-2/+3
| | | | | | | We were not looking past casts to see if an element should be included or not. llvm-svn: 254313
* [WebAssembly] Fix a few minor compiler warnings. NFC.Dan Gohman2015-11-301-7/+7
| | | | llvm-svn: 254311
* fix formatting; NFCSanjay Patel2015-11-301-6/+7
| | | | llvm-svn: 254310
* [Hexagon] NFC Reordering headers.Colin LeMahieu2015-11-301-1/+1
| | | | llvm-svn: 254307
* AMDGPU: Don't reserve SCRATCH_PTR input registerMatt Arsenault2015-11-301-12/+4
| | | | | | This hasn't been doing anything since using relocations was added. llvm-svn: 254304
* Silencing a 32-bit to 64-bit implicit conversion warning; NFC.Aaron Ballman2015-11-301-1/+1
| | | | llvm-svn: 254302
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