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* Fix Windows build (typo in disk_space() implementation)Mehdi Amini2016-04-011-1/+1
| | | | | From: Mehdi Amini <mehdi.amini@apple.com> llvm-svn: 265087
* [LoopVectorize] Don't unconditionally print vectorization diagnosticsAkira Hatanaka2016-04-011-21/+3
| | | | | | | | | | | | | | | | | when compiling with LTO. r244523 a new class DiagnosticInfoOptimizationRemarkAnalysisAliasing for optimization analysis remarks related to pointer aliasing without guarding it in isDiagnosticEnabled in LLVMContext.cpp. This caused the diagnostic message to be printed unconditionally when compiling with LTO. This commit cleans up isDiagnosticEnabled and makes sure all the vectorization optimization remarks are guarded. rdar://problem/25382153 llvm-svn: 265084
* Add disk_space() to llvm::fsMehdi Amini2016-04-012-1/+44
| | | | | | | | | | Summary: Adapted from Boost::filesystem. (This is a reapply by reverting commit r265080 and fixing the WinAPI part) Differential Revision: http://reviews.llvm.org/D18467 From: Mehdi Amini <mehdi.amini@apple.com> llvm-svn: 265082
* Revert "Add disk_space() to llvm::fs"Mehdi Amini2016-04-012-44/+1
| | | | | | | | This reverts commit r265074 and r265068. Breaks windows build From: Mehdi Amini <mehdi.amini@apple.com> llvm-svn: 265080
* Move the DebugEmissionKind enum from DIBuilder into DICompileUnit.Adrian Prantl2016-03-319-9/+62
| | | | | | | | | | | | | This mostly cosmetic patch moves the DebugEmissionKind enum from DIBuilder into DICompileUnit. DIBuilder is not the right place for this enum to live in — a metadata consumer should not have to include DIBuilder.h. I also added a Verifier check that checks that the emission kind of a DICompileUnit is actually legal. http://reviews.llvm.org/D18612 <rdar://problem/25427165> llvm-svn: 265077
* Follow-up to r265036: I got these iterators mixed upHans Wennborg2016-03-311-2/+2
| | | | llvm-svn: 265076
* Use const ref instead of value for Twine in the disk_space() APIMehdi Amini2016-03-312-2/+2
| | | | | | | Thanks Rui for noticing! From: Mehdi Amini <mehdi.amini@apple.com> llvm-svn: 265074
* Add disk_space() to llvm::fsMehdi Amini2016-03-312-1/+44
| | | | | | | | | | Summary: Adapted from Boost::filesystem. (This is a reapply by reverting commit r265062 and fixing the WinAPI part) Differential Revision: http://reviews.llvm.org/D18467 From: Mehdi Amini <mehdi.amini@apple.com> llvm-svn: 265068
* Object: Correctly read thin archives containing absolute paths.Peter Collingbourne2016-03-311-3/+8
| | | | | | Differential Revision: http://reviews.llvm.org/D18666 llvm-svn: 265065
* [AsmPrinter] Print aliases in topological orderTim Shen2016-03-311-1/+18
| | | | | | | | | | Print aliases in topological order, that is, for any alias a = b, b must be printed before a. This is because on some targets (e.g. PowerPC) linker expects aliases in such an order to generate correct TOC information. GCC also prints aliases in topological order. llvm-svn: 265064
* Fix PR26940 where compiles times regressed massively.Chandler Carruth2016-03-311-33/+30
| | | | | | | | | | | | | | | Patch by Jonas Paulsson. Original description: Bugfix in buildSchedGraph() to make -dag-maps-huge-region work properly I found that the reduction of the maps did in fact never happen in this test case. This was because *all* the stores / loads were made with addresses from arguments and they thus became "unknown" stores / loads. Fixed by removing continue statements and making sure that the test for reduction always takes place. Differential Revision: http://reviews.llvm.org/D18673 llvm-svn: 265063
* Revert "Add disk_space() to llvm::fs"Mehdi Amini2016-03-312-44/+1
| | | | | | | | | Breaks windows bot. This reverts commit r265050. This reverts commit r265055. From: Mehdi Amini <mehdi.amini@apple.com> llvm-svn: 265062
* Preserve blockaddress use edges in the module splitter.Evgeniy Stepanov2016-03-311-45/+46
| | | | | | | | "blockaddress" can not apply to an external function. All blockaddress constant uses must belong to the same module as the definition of the target function. llvm-svn: 265061
* [NVPTX] Infer __nvvm_reflect as nounwind, readnoneDavid Majnemer2016-03-312-1/+14
| | | | | | | | | | This patch simply mirrors the attributes we give to @llvm.nvvm.reflect to the __nvvm_reflect libdevice call. This shaves about 30% of the code in libdevice away because of CSE opportunities. It's also helps us figure out that libdevice implementations of transcendental functions don't have side-effects. llvm-svn: 265060
* fix typo; NFCSanjay Patel2016-03-311-2/+1
| | | | llvm-svn: 265054
* [AArch64] Allow loads with imp-def to be handled in getMemOpBaseRegImmOfsWidth()Jun Bum Lim2016-03-311-1/+1
| | | | | | | | | | | | | | Summary: This change will allow loads with imp-def to be clustered in machine-scheduler pass. areMemAccessesTriviallyDisjoint() can also handle loads with imp-def. Reviewers: mcrosier, jmolloy, t.p.northover Subscribers: aemerson, rengolin, mcrosier, llvm-commits Differential Revision: http://reviews.llvm.org/D18665 llvm-svn: 265051
* Add disk_space() to llvm::fsMehdi Amini2016-03-312-1/+44
| | | | | | | | | | | | | Summary: Adapted from Boost::filesystem. Reviewers: bruno, silvas Subscribers: tberghammer, danalbert, llvm-commits, srhines Differential Revision: http://reviews.llvm.org/D18467 From: Mehdi Amini <mehdi.amini@apple.com> llvm-svn: 265050
* [PowerPC] Add a late MI-level pass for QPX load/splat simplificationHal Finkel2016-03-315-4/+170
| | | | | | | | | | | | | | | Chapter 3 of the QPX manual states that, "Scalar floating-point load instructions, defined in the Power ISA, cause a replication of the source data across all elements of the target register." Thus, if we have a load followed by a QPX splat (from the first lane), the splat is redundant. This adds a late MI-level pass to remove the redundant splats in some of these cases (specifically when both occur in the same basic block). This optimization is scheduled just prior to post-RA scheduling. It can't happen before anything that might replace the load with some already-computed quantity (i.e. store-to-load forwarding). llvm-svn: 265047
* Revert r265039 "[X86] Merge adjacent stack adjustments in ↵Hans Wennborg2016-03-311-19/+12
| | | | | | | | | | eliminateCallFramePseudoInstr (PR27140)" I think it might have caused these build breakages: http://lab.llvm.org:8011/builders/clang-x86-win2008-selfhost/builds/7234/steps/build%20stage%202/logs/stdio http://lab.llvm.org:8011/builders/sanitizer-windows/builds/19566/steps/run%20tests/logs/stdio llvm-svn: 265046
* Preserve extern_weak linkage in CloneModule.Evgeniy Stepanov2016-03-311-10/+15
| | | | | | | Only force "extern" linkage if the function used to be a definition in the source module. Declarations keep their original linkage. llvm-svn: 265043
* [ARM] Expand v1i64 and v2i64 ctpop.Benjamin Kramer2016-03-311-0/+2
| | | | | | | The default is legal, which results in 'Cannot select' errors. This is triggered during selfhost due to a recent cost model change. llvm-svn: 265040
* [X86] Merge adjacent stack adjustments in eliminateCallFramePseudoInstr ↵Hans Wennborg2016-03-311-12/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | (PR27140) For code such as: void f(int, int); void g() { f(1, 2); } compiled for 32-bit X86 Linux, Clang would previously generate: subl $12, %esp subl $8, %esp pushl $2 pushl $1 calll f addl $16, %esp addl $12, %esp retl This patch fixes that by merging adjacent stack adjustments in eliminateCallFramePseudoInstr(). Differential Revision: http://reviews.llvm.org/D18627 llvm-svn: 265039
* Change eliminateCallFramePseudoInstr() to return an iteratorHans Wennborg2016-03-3131-88/+74
| | | | | | | | | | | | | | | | | | | | | This will become necessary in a subsequent change to make this method merge adjacent stack adjustments, i.e. it might erase the previous and/or next instruction. It also greatly simplifies the calls to this function from Prolog- EpilogInserter. Previously, that had a bunch of logic to resume iteration after the call; now it just continues with the returned iterator. Note that this changes the behaviour of PEI a little. Previously, it attempted to re-visit the new instruction created by eliminateCallFramePseudoInstr(). That code was added in r36625, but I can't see any reason for it: the new instructions will obviously not be pseudo instructions, they will not have FrameIndex operands, and we have already accounted for the stack adjustment. Differential Revision: http://reviews.llvm.org/D18627 llvm-svn: 265036
* [lanai] isBrImm should accept any non-constant immediate.Jacques Pienaar2016-03-311-17/+6
| | | | | | | | isBrImm should accept any non-constant immediate. Previously it was only accepting LanaiMCExpr ones which was wrong. Differential Revision: http://reviews.llvm.org/D18571 llvm-svn: 265032
* [PPC] basic support for Power 9 direct move instructionsEhsan Amiri2016-03-311-2/+17
| | | | | | | | http://reviews.llvm.org/D18097 Initial support does not include any patterns to generate this instructions llvm-svn: 265031
* [PGO] use emplace_back. NFC.Rong Xu2016-03-311-1/+1
| | | | | | Use emplace_back instead of push_back for simplicity. llvm-svn: 265030
* [x86] use SSE/AVX ops for non-zero memsets (PR27100)Sanjay Patel2016-03-311-5/+7
| | | | | | | | | | | | | | Move the memset check down to the CPU-with-slow-SSE-unaligned-memops case: this allows fast targets to take advantage of SSE/AVX instructions and prevents slow targets from stepping into a codegen sinkhole while trying to splat a byte into an XMM reg. Follow-on bugs exposed by the current codegen are: https://llvm.org/bugs/show_bug.cgi?id=27141 https://llvm.org/bugs/show_bug.cgi?id=27143 Differential Revision: http://reviews.llvm.org/D18566 llvm-svn: 265029
* Minor code cleanup /NFCXinliang David Li2016-03-311-4/+6
| | | | llvm-svn: 265025
* Don't use potentially invalidated iteratorStephan Bergmann2016-03-311-2/+4
| | | | | | | | | | | | If the lhs is evaluated before the rhs, FuncletI's operator-> can trigger the assert(isHandleInSync() && "invalid iterator access!"); at include/llvm/ADT/DenseMap.h:1061. (Happens e.g. when compiled with GCC 6.) Differential Revision: http://reviews.llvm.org/D18440 llvm-svn: 265024
* [PowerPC] Correctly compute 64-bit offsets in fast iselUlrich Weigand2016-03-311-6/+5
| | | | | | | | | | | | | | | | | | | | | PPCSimplifyAddress contains this code: IntegerType *OffsetTy = ((VT == MVT::i32) ? Type::getInt32Ty(*Context) : Type::getInt64Ty(*Context)); to determine the type to be used for an index register, if one needs to be created. However, the "VT" here is the type of the data being loaded or stored, *not* the type of an address. This means that if a data element of type i32 is accessed using an index that does not not fit into 32 bits, a wrong address is computed here. Note that PPCFastISel is only ever used on 64-bit currently, so the type of an address is actually *always* MVT::i64. Other parts of the code, even in this same PPCSimplifyAddress routine, already rely on that fact. Thus, this patch changes the code to simply unconditionally use Type::getInt64Ty(*Context) as OffsetTy. llvm-svn: 265023
* [PowerPC] Basic support for P9 atomic loads and storesNemanja Ivanovic2016-03-317-0/+66
| | | | | | | | | | This patch corresponds to review: http://reviews.llvm.org/D18032 This patch provides asm implementation for the following instructions: lwat, ldat, stwat, stdat, ldmx, mcrxrx llvm-svn: 265022
* [AArch64] Handle missing store pair opportunityJun Bum Lim2016-03-311-22/+23
| | | | | | | | | | | | | | | | | | | | Summary: This change will handle missing store pair opportunity where the first store instruction stores zero followed by the non-zero store. For example, this change will convert : str wzr, [x8] str w1, [x8, #4] into: stp wzr, w1, [x8] Reviewers: jmolloy, t.p.northover, mcrosier Subscribers: flyingforyou, aemerson, rengolin, mcrosier, llvm-commits Differential Revision: http://reviews.llvm.org/D18570 llvm-svn: 265021
* [PowerPC] Remove incorrect use of COPY_TO_REGCLASS in fast iselUlrich Weigand2016-03-313-20/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The fast isel pass currently emits a COPY_TO_REGCLASS node to convert from a F4RC to a F8RC register class during conversion of a floating-point number to integer. There is actually no support in the common code instruction printers to emit COPY_TO_REGCLASS nodes, so the PowerPC back-end has special code there to simply ignore COPY_TO_REGCLASS. This is correct *if and only if* the source and destination registers of COPY_TO_REGCLASS are the same (except for the different register class). But nothing guarantees this to be the case, and if the register allocator does end up allocating source and destination to different registers after all, the back-end simply generates incorrect code. I've included a test case that shows such incorrect code generation. However, it seems that COPY_TO_REGCLASS is actually not intended to be used at the MI layer at all. It is used during SelectionDAG, but always lowered to a plain COPY before emitting MI. Other back-end's fast isel passes never emit COPY_TO_REGCLASS at all. I suspect it is simply wrong for the PowerPC back-end to emit it here. This patch changes the PowerPC back-end to directly emit COPY instead of COPY_TO_REGCLASS and removes the special handling in the instruction printers. Differential Revision: http://reviews.llvm.org/D18605 llvm-svn: 265020
* [mips] Range check simm16Daniel Sanders2016-03-314-35/+68
| | | | | | | | | | | | | | | | | | | Summary: There are too many instructions to exhaustively test so addiu and lwc2 are used as representative examples. It should be noted that many memory instructions that should have simm16 range checking do not because it is also necessary to support the macro of the same name which accepts simm32. The range checks for these occur in the macro expansion. Reviewers: vkalintiris Subscribers: dsanders, llvm-commits Differential Revision: http://reviews.llvm.org/D18437 llvm-svn: 265019
* [mips] Range check simm11 and mem_simm11.Daniel Sanders2016-03-312-6/+15
| | | | | | | | | | | | | | | | | | Summary: ldc2/sdc2 now emit slightly worse diagnostics for MIPS-I. The problem is that they don't trigger the custom parser because all the candidates are disabled by feature bits. On all other subtargets, the diagnostics are accurate but are subject to the usual issues of needing to report multiple ways to correct the code (e.g. smaller offset, enable a CPU feature) but only being able to report one error. Reviewers: vkalintiris Subscribers: dsanders, llvm-commits Differential Revision: http://reviews.llvm.org/D18436 llvm-svn: 265018
* [IFUNC] Introduce GlobalIndirectSymbol as a base class for alias and ifuncDmitry Polukhin2016-03-311-5/+15
| | | | | | | | | | | | This patch is a part of http://reviews.llvm.org/D15525 GlobalIndirectSymbol class contains common implementation for both aliases and ifuncs. This patch should be NFC change that just prepare common code for ifunc support. Differential Revision: http://reviews.llvm.org/D18433 llvm-svn: 265016
* [AMDGPU] Disassembler: support for DPPSam Kolton2016-03-312-7/+23
| | | | | Review: http://reviews.llvm.org/D18642 llvm-svn: 265015
* [mips] Split mem_msa into range checked mem_simm10 and mem_simm10_lsl[123]Daniel Sanders2016-03-315-65/+99
| | | | | | | | | | | | | | Summary: Also, made test_mi10.s formatting consistent with the majority of the MC tests. Reviewers: vkalintiris Subscribers: dsanders, llvm-commits Differential Revision: http://reviews.llvm.org/D18435 llvm-svn: 265014
* Prevent X86ISelLowering from merging volatile loadsNirav Dave2016-03-313-21/+16
| | | | | | | | | | | | | Change isConsecutiveLoads to check that loads are non-volatile as this is a requirement for any load merges. Propagate change to two callers. Reviewers: RKSimon Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D18546 llvm-svn: 265013
* [mips] Range check simm9 and fix a bug this revealed.Daniel Sanders2016-03-314-12/+21
| | | | | | | | | | | | | | Summary: The bug was that microMIPS's [ls]w[lr]e instructions claimed to support a 12-bit offset when it is only 9-bit. Reviewers: vkalintiris Subscribers: llvm-commits, dsanders Differential Revision: http://reviews.llvm.org/D18434 llvm-svn: 265010
* [mips][microMIPS] Implement MFC*, MFHC* and DMFC* instructionsZlatko Buljan2016-03-317-15/+101
| | | | | | Differential Revision: http://reviews.llvm.org/D17334 llvm-svn: 265002
* Indentation fix in SystemZInstrInfo.cppJonas Paulsson2016-03-311-2/+2
| | | | llvm-svn: 265000
* [InstCombine] Fix incorrect rule from rL236202Sanjoy Das2016-03-311-1/+2
| | | | | | | The rule for SMIN introduced in rL236202 doesn't work as advertised: the check for Pred == ICmpInst::ICMP_SGT was missing. llvm-svn: 264996
* Delete trailing whitespaceSanjoy Das2016-03-311-1/+1
| | | | llvm-svn: 264995
* [SCEV] Track NoWrap properties using MatchBinaryOp, NFCSanjoy Das2016-03-311-7/+16
| | | | | | | | | This way once we teach MatchBinaryOp to map more things into arithmetic, the non-wrapping add recurrence construction would understand it too. Right now MatchBinaryOp still only understands arithmetic, so this is solely a code-reorganization change. llvm-svn: 264994
* [SCEV] NFC code motion to simplify later changeSanjoy Das2016-03-311-77/+77
| | | | llvm-svn: 264993
* [X86] Use MVT instead of EVT in code called after legalization.Craig Topper2016-03-311-3/+3
| | | | llvm-svn: 264992
* [PowerPC] Load two floats directly instead of using one 64-bit integer loadHal Finkel2016-03-311-0/+105
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When dealing with complex<float>, and similar structures with two single-precision floating-point numbers, especially when such things are being passed around by value, we'll sometimes end up loading both float values by extracting them from one 64-bit integer load. It looks like this: t13: i64,ch = load<LD8[%ref.tmp]> t0, t6, undef:i64 t16: i64 = srl t13, Constant:i32<32> t17: i32 = truncate t16 t18: f32 = bitcast t17 t19: i32 = truncate t13 t20: f32 = bitcast t19 The problem, especially before the P8 where those bitcasts aren't legal (and get expanded via the stack), is that it would have been better to use two floating-point loads directly. Here we add a target-specific DAGCombine to do just that. In short, we turn: ld 3, 0(5) stw 3, -8(1) rldicl 3, 3, 32, 32 stw 3, -4(1) lfs 3, -4(1) lfs 0, -8(1) into: lfs 3, 4(5) lfs 0, 0(5) llvm-svn: 264988
* Introduce a @llvm.experimental.guard intrinsicSanjoy Das2016-03-315-5/+125
| | | | | | | | | | | | | | | | | | | | | | | Summary: As discussed on llvm-dev[1]. This change adds the basic boilerplate code around having this intrinsic in LLVM: - Changes in Intrinsics.td, and the IR Verifier - A lowering pass to lower @llvm.experimental.guard to normal control flow - Inliner support [1]: http://lists.llvm.org/pipermail/llvm-dev/2016-February/095523.html Reviewers: reames, atrick, chandlerc, rnk, JosephTremoulet, echristo Subscribers: mcrosier, llvm-commits Differential Revision: http://reviews.llvm.org/D18527 llvm-svn: 264976
* [X86] Enable call frame optimization ("mov to push") not only for optsize ↵Hans Wennborg2016-03-301-4/+0
| | | | | | | | | | (PR26325) The size savings are significant, and from what I can tell, both ICC and GCC do this. Differential Revision: http://reviews.llvm.org/D18573 llvm-svn: 264966
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