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* [Stackmaps] Update the stackmap format to use 64-bit relocations for the ↵Juergen Ributzka2014-03-311-20/+36
| | | | | | | | | | | | function address and properly align all entries. This commit updates the stackmap format to version 1 to indicate the reorganizaion of several fields. This was done in order to align stackmap entries to their natural alignment and to minimize padding. Fixes <rdar://problem/16005902> llvm-svn: 205254
* [X86] Adjust cost of FP_TO_UINT v4f64->v4i32 as wellAdam Nemet2014-03-311-0/+1
| | | | | | | | | Pretty obvious follow-on to r205159 to also handle conversion from double besides float. Fixes <rdar://problem/16373208> llvm-svn: 205253
* R600/SI: Remove leftover pattern splitting 64-bit ors.Matt Arsenault2014-03-311-8/+0
| | | | | | | It's now matched to the scalar 64-bit or and split later if necessary.' llvm-svn: 205252
* Register allocator: set CSRFirstUseCost to 5 for ARM64.Manman Ren2014-03-311-0/+7
| | | | | | | | | | | | A value of 5 means if we have a split or spill option that has a really low cost (1 << 14 is the entry frequency), we will choose to spill or split the really cold path before using a callee-saved register. This gives us the performance benefit on SPECInt2k and is also conservative. rdar://16162005 llvm-svn: 205248
* Change shouldSplitVectorElementType to better match the description.Matt Arsenault2014-03-315-7/+7
| | | | | | Pass the entire vector type, and not just the element. llvm-svn: 205247
* R600/SI: Implement shouldConvertConstantLoadToIntImmMatt Arsenault2014-03-314-18/+37
| | | | llvm-svn: 205244
* Add an optional ability to expand larger BUILD_VECTORs with shufflesHal Finkel2014-03-311-20/+117
| | | | | | | | | | | | | | | | | | | | | | | This adds the ability to expand large (meaning with more than two unique defined values) BUILD_VECTOR nodes in terms of SCALAR_TO_VECTOR and (legal) vector shuffles. There is now no limit of the size we are capable of expanding this way, although we don't currently do this for vectors with many unique values because of the default implementation of TLI's shouldExpandBuildVectorWithShuffles function. There is currently no functional change to any existing targets because the new capabilities are not used unless some target overrides the TLI shouldExpandBuildVectorWithShuffles function. As a result, I've not included a test case for the new functionality in this commit, but regression tests will (at least) be added soon when I commit support for the PPC QPX vector instruction set. The benefit of committing this now is that it makes the shouldExpandBuildVectorWithShuffles callback, which had to be added for other reasons regardless, fully functional. I suspect that other targets will also benefit from tuning the heuristic. llvm-svn: 205243
* R600: Compute masked bits for min and maxMatt Arsenault2014-03-311-0/+44
| | | | llvm-svn: 205242
* Don't relocate with sections if there might be a paired relocation.Rafael Espindola2014-03-311-2/+18
| | | | llvm-svn: 205240
* Revert: [mips] Rewrite MipsAsmParser and MipsOperand.' due to buildbot ↵Daniel Sanders2014-03-318-864/+1017
| | | | | | | | errors in lld tests. It's currently unable to parse 'sym + imm' without surrounding parenthesis. llvm-svn: 205237
* R600: Add BFE, BFI, and BFM intrinsics to help with writing tests.Matt Arsenault2014-03-313-1/+33
| | | | llvm-svn: 205236
* R600: Add target nodes for BFM and BFIMatt Arsenault2014-03-315-3/+14
| | | | llvm-svn: 205235
* ARM: fix typoSaleem Abdulrasool2014-03-311-1/+1
| | | | llvm-svn: 205233
* [PowerPC] Don't ever expand BUILD_VECTOR of v2i64 with shufflesHal Finkel2014-03-312-0/+14
| | | | | | | If we have two unique values for a v2i64 build vector, this will always result in two vector loads if we expand using shuffles. Only one is necessary. llvm-svn: 205231
* Add a TLI hook to control when BUILD_VECTOR might be expanded using shufflesHal Finkel2014-03-311-1/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There are two general methods for expanding a BUILD_VECTOR node: 1. Use SCALAR_TO_VECTOR on the defined scalar values and then shuffle them together. 2. Build the vector on the stack and then load it. Currently, we use a fixed heuristic: If there are only one or two unique defined values, then we attempt an expansion in terms of SCALAR_TO_VECTOR and vector shuffles (provided that the required shuffle mask is legal). Otherwise, always expand via the stack. Even when SCALAR_TO_VECTOR is not legal, this can still be a good idea depending on what tricks the target can play when lowering the resulting shuffle. If the target can't do anything special, however, and if SCALAR_TO_VECTOR is expanded via the stack, this heuristic leads to sub-optimal code (two stack loads instead of one). Because only the target knows whether the SCALAR_TO_VECTORs and shuffles for a build vector of a particular type are likely to be optimial, this adds a new TLI function: shouldExpandBuildVectorWithShuffles which takes the vector type and the count of unique defined values. If this function returns true, then method (1) will be used, subject to the constraint that all of the necessary shuffles are legal (as determined by isShuffleMaskLegal). If this function returns false, then method (2) is always used. This commit does not enhance the current code to support expanding a build_vector with more than two unique values using shuffles, but I'll commit an implementation of the more-general case shortly. llvm-svn: 205230
* [mips] Rewrite MipsAsmParser and MipsOperand.Daniel Sanders2014-03-318-1017/+864
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: Highlights: - Registers are resolved much later (by the render method). Prior to that point, GPR32's/GPR64's are GPR's regardless of register size. Similarly FGR32's/FGR64's/AFGR64's are FGR's regardless of register size or FR mode. Numeric registers can be anything. - All registers are parsed the same way everywhere (even when handling symbol aliasing) - One consequence is that all registers can be specified numerically almost anywhere (e.g. $fccX, $wX). The exception is symbol aliasing but that can be easily resolved. - Removes the need for the hasConsumedDollar hack - Parenthesis and Bracket suffixes are handled generically - Micromips instructions are parsed directly instead of going through the standard encodings first. - rdhwr accepts all 32 registers, and the following instructions that previously xfailed now work: ddiv, ddivu, div, divu, cvt.l.[ds], se[bh], wsbh, floor.w.[ds], c.ngl.d, c.sf.s, dsbh, dshd, madd.s, msub.s, nmadd.s, nmsub.s, swxc1 - Diagnostics involving registers point at the correct character (the $) - There's only one kind of immediate in MipsOperand. LSA immediates are handled by the predicate and renderer. Lowlights: - Hardcoded '$zero' in the div patterns is handled with a hack. MipsOperand::isReg() will return true for a k_RegisterIndex token with Index == 0 and getReg() will return ZERO for this case. Note that it doesn't return ZERO_64 on isGP64() targets. - I haven't cleaned up all of the now-unused functions. Some more of the generic parser could be removed too (integers and relocs for example). - insve.df needed a custom decoder to handle the implicit fourth operand that was needed to make it parse correctly. The difficulty was that the matcher expected a Token<'0'> but gets an Imm<0>. Adding an implicit zero solved this. Reviewers: matheusalmeida, vmedic Reviewed By: matheusalmeida Differential Revision: http://llvm-reviews.chandlerc.com/D3222 llvm-svn: 205229
* Disable each MachineFunctionPass for 'optnone' functions, unless thatPaul Robinson2014-03-3114-0/+42
| | | | | | | pass normally runs at optimization level None, or is part of the register allocation pipeline. llvm-svn: 205228
* [PowerPC] Correct P7 dispatch unit allocation for vector instructionsHal Finkel2014-03-311-16/+8
| | | | llvm-svn: 205222
* This patch fixes LTO's RecordStreamer so that it records symbols in the MCExprTom Roeder2014-03-311-0/+1
| | | | | | | | | | | part of an asm .symver directive as being used. This prevents referenced functions from being internalized and deleted. Without the patch to LTOModule.cpp, the test case will produce the error: LLVM ERROR: A @@ version cannot be undefined. llvm-svn: 205221
* Support: generalise object type handling for WindowsSaleem Abdulrasool2014-03-311-7/+15
| | | | | | | | | This generalises the object file type parsing to all Windows environments. This is used by cygwin as well as MSVC environments for MCJIT. This also makes the triple more similar to Chandler's suggestion of a separate field for the object file format. llvm-svn: 205219
* PR19099 - revert r203483Eli Bendersky2014-03-312-48/+16
| | | | | | | Now that r205212 was committed, r203483 is no longer necessary; it was a temporary workaround that only handled a small number of the problematic cases. llvm-svn: 205216
* ARM: change parameter names of the ELFARMAsmBackend constructorChristian Pirker2014-03-311-2/+2
| | | | | | | I removed the underscore at the beginning of the parameter name, because of a comment from Tim. llvm-svn: 205215
* Test commit.Robert Khasanov2014-03-311-2/+2
| | | | llvm-svn: 205214
* [mips] Fix use of uninitialized value reported by the ↵Daniel Sanders2014-03-311-0/+2
| | | | | | sanitizer-x86_64-linux-bootstrap buildbot llvm-svn: 205213
* Fix for PR19099 - NVPTX produces invalid symbol names.Eli Bendersky2014-03-314-0/+89
| | | | | | | | This is a more thorough fix for the issue than r203483. An IR pass will run before NVPTX codegen to make sure there are no invalid symbol names that can't be consumed by the ptxas assembler. llvm-svn: 205212
* ARM64: add extra patterns for scalar shiftsTim Northover2014-03-311-6/+12
| | | | llvm-svn: 205209
* ARM64: add extra scalar neg pattern & tests.Tim Northover2014-03-311-1/+2
| | | | llvm-svn: 205208
* ARM64: add patterns for scalar sqdmlal & sqdmlsl.Tim Northover2014-03-311-0/+9
| | | | llvm-svn: 205207
* ARM64: add more patterns for commuted fmsub operations.Tim Northover2014-03-311-0/+8
| | | | llvm-svn: 205206
* ARM64: shuffle patterns around for fmin/fmax & add tests.Tim Northover2014-03-311-8/+8
| | | | llvm-svn: 205205
* ARM64: add more scalar patterns for usqadd & suqadd.Tim Northover2014-03-311-7/+11
| | | | llvm-svn: 205204
* ARM64: add more scalar patterns for reciprocal ops.Tim Northover2014-03-311-0/+15
| | | | llvm-svn: 205203
* ARM64: add i64 scalar pattern for @llvm.arm64.absTim Northover2014-03-312-7/+3
| | | | | | This will be used by the Clang front-end code for vabsd_s64. llvm-svn: 205202
* [mips] Implement missing relocations in the integrated assembler.Daniel Sanders2014-03-311-0/+8
| | | | | | | | | | %got_hi, %got_lo, %call_hi, %call_lo, %higher, and %highest are now recognised by MipsAsmParser::getVariantKind(). To prevent future issues with missing entries in this StringSwitch, I've added an assertion to the default case. llvm-svn: 205200
* Revert r205194 - [mips] Removed R_MIPS_GOT. It's identical to R_MIPS_GOT16.Daniel Sanders2014-03-311-0/+1
| | | | | | There's a couple additional bits I missed. llvm-svn: 205195
* [mips] Removed R_MIPS_GOT. It's identical to R_MIPS_GOT16.Daniel Sanders2014-03-311-1/+0
| | | | llvm-svn: 205194
* Capitalize the D in parseDirectiveGpDWord.Rafael Espindola2014-03-311-4/+4
| | | | | | | | DWord seems to be the canonical way to camel case dword in llvm. Thanks to Daniel Sander for noticing. llvm-svn: 205191
* R600/SI: Implement SIInstrInfo::isTriviallyRematerializable()Tom Stellard2014-03-312-0/+15
| | | | llvm-svn: 205188
* R600/SI: Lower i64 SELECT by bitcasting to a vector typeTom Stellard2014-03-312-7/+10
| | | | | | | This allows allows us to replace ISD::EXTRACT_ELEMENT, which is lowered using shifts, with ISD::EXTRACT_VECTOR_ELT, which is a no-op. llvm-svn: 205187
* R600/SI: Return the correct index for VGPRs in getHWRegIndex()Tom Stellard2014-03-311-1/+1
| | | | | | The register index is stored in the low 8-bits of the encoding. llvm-svn: 205186
* Fixed issue with microMIPS JAL instruction.Zoran Jovanovic2014-03-314-15/+4
| | | | | | Differential Revision: http://llvm-reviews.chandlerc.com/D3200 llvm-svn: 205185
* Look at shuffles of build_vectors in DAGCombiner::visitEXTRACT_VECTOR_ELTHal Finkel2014-03-311-7/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | When the loop vectorizer vectorizes code that uses the loop induction variable, we often end up with IR like this: %b1 = insertelement <2 x i32> undef, i32 %v, i32 0 %b2 = shufflevector <2 x i32> %b1, <2 x i32> undef, <2 x i32> zeroinitializer %i = add <2 x i32> %b2, <i32 2, i32 3> If the add in this example is not legal (as is the case on PPC with VSX), it will be scalarized, and we'll end up with a number of extract_vector_elt nodes with the vector shuffle as the input operand, and that vector shuffle is fed by one or more build_vector nodes. By the time that vector operations are expanded, visitEXTRACT_VECTOR_ELT will not create new extract_vector_elt by looking through the vector shuffle (to make sure that no illegal operations are created), and so the extract_vector_elt -> vector shuffle -> build_vector is never simplified to an operand of the build vector. By looking at build_vectors through a shuffle we fix this particular situation, preventing a vector from being built, only to be deconstructed again (for the scalarized add) -- an expensive proposition when this all needs to be done via the stack. We probably want a more comprehensive fix here where we look back recursively through any shuffles to any build_vectors or scalar_to_vectors, etc. but that can come later. llvm-svn: 205179
* ARM64: fix a couple of signed/unsigned comparison warnings.Tim Northover2014-03-312-3/+2
| | | | llvm-svn: 205174
* [yaml2obj] Add support for ELF e_flags.Daniel Sanders2014-03-311-0/+43
| | | | | | | | | | | | | | | | Summary: The FileHeader mapping now accepts an optional Flags sequence that accepts the EF_<arch>_<flag> constants. When not given, Flags defaults to zero. Reviewers: atanasyan Reviewed By: atanasyan CC: llvm-commits Differential Revision: http://llvm-reviews.chandlerc.com/D3213 llvm-svn: 205173
* Try to fix MSan bootstrap bot: make ARM64Disassembler::getInstruction() ↵Alexey Samsonov2014-03-311-2/+2
| | | | | | always initialize Size argument. llvm-svn: 205171
* Correct OS conditionals following r204977 and r204978.Yaron Keren2014-03-311-5/+3
| | | | | | | | | | | | | | | | | | | | | | Previously, MinGW OS was Triple::MinGW and Cygwin was Triple::Cygwin and now it is Triple::Win32 with Environment being GNU or Cygwin. So, TheTriple.getOS() == Triple::Win32 is replaced by TheTriple.isWindowsMSVCEnvironment() and (TheTriple.getOS() == Triple::MinGW32 || TheTriple.getOS() == Triple::Cygwin) is replaced by TheTriple.isOSCygMing() llvm-svn: 205170
* [C++11] Mark more classes in the X86 target as 'final'.Craig Topper2014-03-316-8/+8
| | | | llvm-svn: 205166
* Mark a couple of the X86 target classes as final. Allows the compiler to ↵Craig Topper2014-03-312-2/+2
| | | | | | de-virtualize some internal calls. llvm-svn: 205165
* ARM64CollectLOH.cpp: Tweak \param. [-Wdocumentation]NAKAMURA Takumi2014-03-311-1/+1
| | | | llvm-svn: 205162
* [ARM64] Fix materialization of an fp128 zero immediate. There currentlyChandler Carruth2014-03-311-2/+3
| | | | | | | | | is not a pattern to lower this with clever instructions that zero the register, so restrict the zero immediate legality special case to f64 and f32 (the only two sizes which fmov seems to directly support). Fixes backend errors when building code such as libxml. llvm-svn: 205161
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