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* Added the missing bit definition for the 4th bit of the STR (post reg) ↵Silviu Baranga2012-05-112-0/+5
| | | | | | instruction. It is now set to 0. The patch also sets the unpredictable mask for SEL and SXTB-type instructions. llvm-svn: 156609
* Fixed the LLVM ARM v7 assembler and instruction printer for 8-bit immediate ↵Silviu Baranga2012-05-112-3/+9
| | | | | | offset addressing. The assembler and instruction printer were not properly handeling the #-0 immediate. llvm-svn: 156608
* Fix a misleading comment.Akira Hatanaka2012-05-111-1/+1
| | | | llvm-svn: 156603
* Tidy up. Trailing whitespace.Jim Grosbach2012-05-1112-35/+35
| | | | llvm-svn: 156602
* Fix a minor logic mistake transforming compares in instcombine. PR12514.Eli Friedman2012-05-111-1/+1
| | | | llvm-svn: 156600
* ARM: peephole optimization to remove cmp instructionManman Ren2012-05-112-27/+128
| | | | | | | | | | | | | | | | | This patch will optimize the following cases: sub r1, r3 | sub r1, imm cmp r3, r1 or cmp r1, r3 | cmp r1, imm bge L1 TO subs r1, r3 bge L1 or ble L1 If the branch instruction can use flag from "sub", then we can replace "sub" with "subs" and eliminate the "cmp" instruction. rdar: 10734411 llvm-svn: 156599
* Define a new intrinsic, @llvm.debugger. It will be similar to __builtin_trap(),Dan Gohman2012-05-113-0/+8
| | | | | | but it generates int3 on x86 instead of ud2. llvm-svn: 156593
* Allow unique_file to take a mode for file permissions, but defaultEric Christopher2012-05-112-5/+8
| | | | | | | | to user only read/write. Part of rdar://11325849 llvm-svn: 156591
* Fix intendation.Chad Rosier2012-05-101-1/+1
| | | | llvm-svn: 156589
* objectsize: add support for GEPs with non-constant indexesNuno Lopes2012-05-103-34/+34
| | | | | | add an additional parameter to InstCombiner::EmitGEPOffset() to force it to *not* emit operations with NUW flag llvm-svn: 156585
* Added X86 Atom latencies for instructions in X86InstrInfo.td.Preston Gurd2012-05-103-223/+426
| | | | llvm-svn: 156579
* Add support for the 'X' inline asm operand modifier.Eric Christopher2012-05-101-4/+16
| | | | | | Patch by Jack Carter. llvm-svn: 156577
* misched: Print machineinstrs with -debug-only=mischedAndrew Trick2012-05-101-0/+2
| | | | llvm-svn: 156576
* misched: tracing register pressure heuristics.Andrew Trick2012-05-101-6/+22
| | | | llvm-svn: 156575
* misched: Add register pressure backoff to ConvergingScheduler.Andrew Trick2012-05-101-38/+144
| | | | | | | | | | | Prioritize the instruction that comes closest to keeping pressure under the target's limit. Then prioritize instructions that avoid increasing the max pressure in the scheduled region. The max pressure heuristic is a tad aggressive. Later I'll fix it to consider the unscheduled pressure as well. WIP: This is mostly functional but untested and not likely to do much good yet. llvm-svn: 156574
* misched: Release only unscheduled nodes into ReadyQ.Andrew Trick2012-05-101-2/+8
| | | | llvm-svn: 156573
* misched: Added ReadyQ container wrapper for Top and Bottom Queues.Andrew Trick2012-05-101-11/+44
| | | | llvm-svn: 156572
* misched: Introducing Top and Bottom register pressure trackers during ↵Andrew Trick2012-05-103-39/+112
| | | | | | scheduling. llvm-svn: 156571
* Hexagon V5 Support - V5 td file.Sirish Pande2012-05-101-0/+626
| | | | llvm-svn: 156569
* Hexagon V5 FP Support.Sirish Pande2012-05-1014-194/+519
| | | | llvm-svn: 156568
* RegPressure: API for speculatively checking instruction pressure.Andrew Trick2012-05-102-1/+229
| | | | | | | | | Added getMaxExcessUpward/DownwardPressure. They somewhat abuse the tracker by speculatively handling an instruction out of order. But it is convenient for now. In the future, we will cache each instruction's pressure contribution to make this efficient. llvm-svn: 156561
* RegPressure: fix array index iteration style.Andrew Trick2012-05-101-8/+8
| | | | llvm-svn: 156560
* Teach DeadStoreElimination to eliminate exit-block stores with phi addresses.Dan Gohman2012-05-102-3/+50
| | | | llvm-svn: 156558
* Revert: 156550 "ARM: peephole optimization to remove cmp instruction"Manman Ren2012-05-102-127/+27
| | | | | | This commit broke an external linux bot and gave a compile-time warning. llvm-svn: 156556
* Rewrite ScalarEvolution::hasOperand to use an explicit worklist insteadDan Gohman2012-05-101-35/+50
| | | | | | of recursion, to avoid excessive stack usage on deep expressions. llvm-svn: 156554
* teach DSE and isInstructionTriviallyDead() about callocNuno Lopes2012-05-102-4/+17
| | | | llvm-svn: 156553
* ARM: peephole optimization to remove cmp instructionManman Ren2012-05-102-27/+127
| | | | | | | | | | | | | | | | | This patch will optimize the following cases: sub r1, r3 | sub r1, imm cmp r3, r1 or cmp r1, r3 | cmp r1, imm bge L1 TO subs r1, r3 bge L1 or ble L1 If the branch instruction can use flag from "sub", then we can replace "sub" with "subs" and eliminate the "cmp" instruction. rdar: 10734411 llvm-svn: 156550
* Fix a problem with incomplete equality testing of PHINodes in Joel Jones2012-05-101-1/+8
| | | | | | | | | | | | | | | | | | | | Instruction::IsIdenticalToWhenDefined. This manifested itself when inlining two calls to the same function. The inlined function had a switch statement that returned one of a set of global variables. Without this modification, the two phi instructions that chose values from the branches of the switch instruction inlined from the callee were considered equivalent and jump-threading replaced a load for the first switch value with a phi selecting from the second switch, thereby producing incorrect code. This patch has been tested with "make check-all", "lnt runteste nt", and llvm self-hosted, and on the original program that had this problem, wireshark. <rdar://problem/11025519> llvm-svn: 156548
* Fix merge-typo and cleanupNadav Rotem2012-05-101-5/+3
| | | | llvm-svn: 156541
* AVX2: Add an additional broadcast idiom.Nadav Rotem2012-05-101-2/+5
| | | | llvm-svn: 156540
* Generate AVX/AVX2 shuffles even when there is a memory op somewhere else in ↵Nadav Rotem2012-05-101-4/+0
| | | | | | | | | | the program. Starting r155461 we are able to select patterns for vbroadcast even when the load op is used by other users. Fix PR11900. llvm-svn: 156539
* ExecutionEngine: Check for NULL ErrorStr before using it.Jim Grosbach2012-05-101-2/+3
| | | | | | Patch by Yury Mikhaylov <yury.mikhaylov@gmail.com>. llvm-svn: 156523
* Fix the objc_storeStrong recognizer to stop before walking off theDan Gohman2012-05-091-1/+4
| | | | | | end of a basic block if there's no store. llvm-svn: 156520
* objectsize:Nuno Lopes2012-05-091-55/+96
| | | | | | | refactor code a bit to enable future changes to support run-time information add support to compute allocation sizes at run-time if penalty > 1 (e.g., malloc(x), calloc(x, y), and VLAs) llvm-svn: 156515
* Mark .opd @progbits, thus avoiding a warning from asm.Roman Divacky2012-05-091-1/+1
| | | | llvm-svn: 156494
* Set the default iOS version to 3.0.Chad Rosier2012-05-091-2/+4
| | | | llvm-svn: 156492
* Use the cpuid 64 bit flag to pick the default CPU name for an unknown model.Bob Wilson2012-05-091-1/+1
| | | | | | | | | | | For the Family 6 switch in sys::getHostCPUName, an unrecognized model was reported as "i686". That's a really bad default since it means that new CPUs will be treated as if they can only use 32-bit code. This just looks at the cpuid extended feature flag for 64 bit support, and if that is set, it uses a default x86-64 cpu. Similar logic is already used for the Family 15 code. <rdar://problem/11314502> llvm-svn: 156486
* Don't return true on a function with a void return type.Chad Rosier2012-05-091-1/+1
| | | | llvm-svn: 156484
* Add Triple::getiOSVersion.Chad Rosier2012-05-091-0/+21
| | | | | | | This new function provides a way to get the iOS version number from ios triples. Part of rdar://11409204 llvm-svn: 156483
* Introduce llvm-c function LLVMPrintModuleToFile.Hans Wennborg2012-05-091-0/+19
| | | | | | | | | This lets you save the textual representation of the LLVM IR to a file. Before this patch it could only be printed to STDERR from llvm-c. Patch by Carlo Kok! llvm-svn: 156479
* change the objectsize intrinsic signature: add a 3rd parameter to denote the ↵Nuno Lopes2012-05-091-1/+25
| | | | | | | | maximum runtime performance penalty that the user is willing to accept. This commit only adds the parameter. Code taking advantage of it will follow. llvm-svn: 156473
* Supply a C interface to the "LinkModules" method.Bill Wendling2012-05-091-0/+15
| | | | | | Patch by Andrew Wilkins! llvm-svn: 156469
* Remove unused variable to get rid of warning.Craig Topper2012-05-091-1/+1
| | | | llvm-svn: 156466
* Add another peephole pattern for conditional moves.Akira Hatanaka2012-05-091-0/+10
| | | | llvm-svn: 156460
* Use ptr_rc_tailcall instead of GR32_TC.Jakob Stoklund Olesen2012-05-093-6/+7
| | | | | | | | | The getPointerRegClass() hook will return GR32_TC, or whatever is appropriate for the current function. Patch by Yiannis Tsiouris! llvm-svn: 156459
* Make register FP allocatable if the compiled function does not have dynamicAkira Hatanaka2012-05-091-2/+8
| | | | | | allocas. llvm-svn: 156458
* Expand 64-bit shifts if target ABI is O32.Akira Hatanaka2012-05-092-3/+83
| | | | llvm-svn: 156457
* Remove unused variable to silence compiler warning.Richard Trieu2012-05-091-1/+0
| | | | llvm-svn: 156456
* Miscellaneous accumulated cleanups.Dan Gohman2012-05-081-104/+78
| | | | llvm-svn: 156445
* Fix it so llvm-objdump -arch does accept x86 and x86-64 as valid arch names.Kevin Enderby2012-05-081-0/+41
| | | | | | PR12731. Patch by Meador Inge! llvm-svn: 156444
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