summaryrefslogtreecommitdiffstats
path: root/llvm/lib
Commit message (Collapse)AuthorAgeFilesLines
...
* Rip out emission of the regIsInRegClass function for the asm printer.Benjamin Kramer2012-03-301-0/+1
| | | | | | It's slow, bloated and completely redundant with MCRegisterClass::contains. llvm-svn: 153782
* ARM fix encoding fixup resolution for ldrd and friends.Jim Grosbach2012-03-301-0/+2
| | | | | | | | | The 8-bit payload is not contiguous in the opcode. Move the upper nibble over 4 bits into the correct place. rdar://11158641 llvm-svn: 153780
* ARM assembler should prefer non-aliases encoding of cmp.Jim Grosbach2012-03-301-4/+6
| | | | | | | | When an immediate is both a value [t2_]so_imm and a [t2_]so_imm_neg, we want to use the non-negated form to make sure we prefer the normal encoding, not the aliased encoding via the negation of, e.g., 'cmp.w'. llvm-svn: 153770
* ARM encoding for VSWP got the second operand incorrect.Jim Grosbach2012-03-301-4/+4
| | | | | | | | | Make the non-tied register operand names line up with what the base class encoding handler expects. rdar://11157236 llvm-svn: 153766
* ARM can only use narrow encoding for low regs.Jim Grosbach2012-03-301-0/+1
| | | | llvm-svn: 153765
* ARM integrated assembler should encoding choice for add/sub imm.Jim Grosbach2012-03-301-0/+25
| | | | | | | | | For 'adds r2, r2, #56' outside of an IT block, the 16-bit encoding T2 can be used for this syntax. Prefer the narrow encoding when possible. rdar://11156277 llvm-svn: 153759
* Handle unreachable code in the dominates functions. This changes users whenRafael Espindola2012-03-301-4/+14
| | | | | | | needed for correctness, but still doesn't clean up code that now unnecessary checks for reachability. llvm-svn: 153755
* Re-factored RuntimeDyLd:Danil Malyshev2012-03-307-1046/+753
| | | | | | | | | | | | | | | 1. The main works will made in the RuntimeDyLdImpl with uses the ObjectFile class. RuntimeDyLdMachO and RuntimeDyLdELF now only parses relocations and resolve it. This is allows to make improvements of the RuntimeDyLd more easily. In addition the support for COFF can be easily added. 2. Added ARM relocations to RuntimeDyLdELF. 3. Added support for stub functions for the ARM, allowing to do a long branch. 4. Added support for external functions that are not loaded from the object files, but can be loaded from external libraries. Now MCJIT can correctly execute the code containing the printf, putc, and etc. 5. The sections emitted instead functions, thanks Jim Grosbach. MemoryManager.startFunctionBody() and MemoryManager.endFunctionBody() have been removed. 6. MCJITMemoryManager.allocateDataSection() and MCJITMemoryManager. allocateCodeSection() used JMM->allocateSpace() instead of JMM->allocateCodeSection() and JMM->allocateDataSection(), because I got an error: "Cannot allocate an allocated block!" with object file contains more than one code or data sections. llvm-svn: 153754
* ARM assembly parsing needs to be paranoid about negative immediates.Jim Grosbach2012-03-301-3/+3
| | | | | | | | Make sure to treat immediates as unsigned when doing relative comparisons. rdar://11153621 llvm-svn: 153753
* Add computeMaskedBitsLoad back, as it was the change to instsimplify thatRafael Espindola2012-03-301-0/+26
| | | | | | caused the slowdown last time. llvm-svn: 153747
* Add a note about a missed cmov -> sbb opportunity.Benjamin Kramer2012-03-301-0/+18
| | | | llvm-svn: 153741
* Ensure conditional BL instructions for ARM are given the fixup ↵James Molloy2012-03-305-10/+33
| | | | | | | | fixup_arm_condbranch. Patch by Tim Northover! llvm-svn: 153737
* ARM target should allow codegenprep to duplicate ret instructions to enable ↵Evan Cheng2012-03-301-1/+1
| | | | | | tailcall opt. rdar://11140249 llvm-svn: 153717
* If we have a VLA that has a "use" in a metadata node that's then usedBill Wendling2012-03-301-1/+12
| | | | | | | | | | | | | | | | here but it has no other uses, then we have a problem. E.g., int foo (const int *x) { char a[*x]; return 0; } If we assign 'a' a vreg and fast isel later on has to use the selection DAG isel, it will want to copy the value to the vreg. However, there are no uses, which goes counter to what selection DAG isel expects. <rdar://problem/11134152> llvm-svn: 153705
* Revert r153694. It was causing failures in the buildbots.Bill Wendling2012-03-297-753/+1046
| | | | llvm-svn: 153701
* Invalidate liveness in ARMConstantIslandPass.Jakob Stoklund Olesen2012-03-291-0/+4
| | | | | | | | | | This pass splits basic blocks to insert constant islands, and it doesn't recompute the live-in lists. No later passes depend on accurate liveness information. This fixes PR12410 where the machine code verifier was complaining. llvm-svn: 153700
* Prefer even-odd D-register pairs.Jakob Stoklund Olesen2012-03-291-1/+2
| | | | | | | | | | | We are sometimes allocatinog from the DPair register class which contains odd-even pairs in addition to the Q registers. Place the Q registers first in the DPair allocation order as they can be copied with a single instruction. The odd-even pairs should only be allocated as a last resort. llvm-svn: 153699
* Try using vmov.i32 to materialize FP32 constants that can't be materialized byLang Hames2012-03-291-23/+54
| | | | | | vmov.f32. llvm-svn: 153696
* Re-factored RuntimeDyld.Danil Malyshev2012-03-297-1046/+753
| | | | | | Added ExecutionEngine/MCJIT tests. llvm-svn: 153694
* Lowercase the tag name to match the rest of dwarf.Eric Christopher2012-03-293-4/+4
| | | | llvm-svn: 153691
* ARM assembly 'cmp lr, #0' should not encode using 'cmn'.Jim Grosbach2012-03-293-4/+8
| | | | | | | | | The CMP->CMN alias was matching for an immediate of zero when it should only match for negative values. rdar://11129224 llvm-svn: 153689
* Handle register copies for the new ARM register classes.Jakob Stoklund Olesen2012-03-291-19/+41
| | | | | | | | | | | | | ARM recently gained DPair, DTriple, and DQuad register classes. Update copyPhysReg() to handle copies in these register classes. No test case, it is difficult to make the register allocator emit the odd copies reliably. The missing DPair copy caused a failure on partialsums in the nightly test suite. <rdar://problem/11147997> llvm-svn: 153686
* Make x86 REP_MOV* and REP_STO instructions use the correct operand sizes in ↵Lang Hames2012-03-291-23/+56
| | | | | | 64-bit mode. llvm-svn: 153680
* Expand FREM.Akira Hatanaka2012-03-291-0/+2
| | | | llvm-svn: 153671
* Don't PRE compares.Jakob Stoklund Olesen2012-03-291-1/+8
| | | | | | | | | | | | CodeGenPrepare sinks compare instructions down to their uses to prevent live flags and predicate registers across basic blocks. PRE of a compare instruction prevents that, forcing the i1 compare result into a general purpose register. That is usually more expensive than the redundant compare PRE was trying to eliminate in the first place. llvm-svn: 153657
* Replace assert(0) with llvm_unreachable to avoid warnings about dropping off ↵Benjamin Kramer2012-03-291-6/+5
| | | | | | the end of a non-void function in Release builds. llvm-svn: 153643
* Add support for objc property decls according to the page at:Eric Christopher2012-03-294-3/+42
| | | | | | | | | | http://llvm.org/docs/SourceLevelDebugging.html#objcproperty including type and DECL. Expand the metadata needed accordingly. rdar://11144023 llvm-svn: 153639
* Only allow symbolic names for (v)cmpss/sd/ps/pd encodings 8-31 to be used ↵Craig Topper2012-03-291-12/+13
| | | | | | with 'v' version of instructions. llvm-svn: 153636
* For X86, change load/dec-or-inc/store into dec-or-inc, respectively.Joel Jones2012-03-291-34/+94
| | | | | | | | | | | | | | | | | This is a code change to add support for changing instruction sequences of the form: load inc/dec of 8/16/32/64 bits store into the appropriate X86 inc/dec through memory instruction: inc[qlwb] / dec[qlwb] The checks that were in X86DAGToDAGISel::Select(SDNode *Node)>>ISD::STORE have been extracted to isLoadIncOrDecStore and reworked to use the better named wrappers for getOperand(unsigned) (e.g. getOffset()) and replaced Chain.getNode() with LoadNode. The comments have also been expanded. llvm-svn: 153635
* Reverted to revision 153616 to unblock buildJoel Jones2012-03-291-94/+34
| | | | llvm-svn: 153623
* For X86, change load/dec-or-inc/store into dec-or-inc, respectively.Joel Jones2012-03-291-34/+94
| | | | | | | | | | | | | | | | | This is a code change to add support for changing instruction sequences of the form: load inc/dec of 8/16/32/64 bits store into the appropriate X86 inc/dec through memory instruction: inc[qlwb] / dec[qlwb] The checks that were in X86DAGToDAGISel::Select(SDNode *Node)>>ISD::STORE have been extracted to isLoadIncOrDecStore and reworked to use the better named wrappers for getOperand(unsigned) (e.g. getOffset()) and replaced Chain.getNode() with LoadNode. The comments have also been expanded. llvm-svn: 153617
* Enable machine code verification in the entire code generator.Jakob Stoklund Olesen2012-03-282-10/+5
| | | | | | | | | | Some targets still mess up the liveness information, but that isn't verified after MRI->invalidateLiveness(). The verifier can still check other useful things like register classes and CFG, so it should be enabled after all passes. llvm-svn: 153615
* Enable machine code verification after PreSched2 passes.Jakob Stoklund Olesen2012-03-282-2/+4
| | | | | | | | | | The late scheduler depends on accurate liveness information if it is breaking anti-dependencies, so we should be able to verify it. Relax the terminator checking in the machine code verifier so it can handle the basic blocks created by if conversion. llvm-svn: 153614
* Don't kill the base register when expanding strd.Jakob Stoklund Olesen2012-03-281-0/+4
| | | | | | | | | | | | | | When an strd instruction doesn't get the registers it wants, it can be expanded into two str instructions. Make sure the first str doesn't kill the base register in the case where the base and data registers are identical: t2STRi12 %R0<kill>, %R0, 4, pred:14, pred:%noreg t2STRi12 %R2<kill>, %R0, 8, pred:14, pred:%noreg <rdar://problem/11101911> llvm-svn: 153611
* Preserve implicit defs in ARMLoadStoreOptimizer.Jakob Stoklund Olesen2012-03-282-4/+23
| | | | | | | | | | | When a number of sub-register VLRDS instructions are combined into a VLDM, preserve any super-register implicit defs. This is required to keep the register scavenger and machine code verifier happy. Enable machine code verification after ARMLoadStoreOptimizer. ARM/2012-01-26-CopyPropKills.ll was failing because of this. llvm-svn: 153610
* Move getPointerToNamedFunction() from JIT/MCJIT to JITMemoryManager.Danil Malyshev2012-03-2810-332/+208
| | | | llvm-svn: 153607
* Handle intrinsics in GlobalsModRef. Fixes pr12351.Rafael Espindola2012-03-281-0/+6
| | | | llvm-svn: 153604
* Spill DPair registers, not just QPR.Jakob Stoklund Olesen2012-03-282-6/+6
| | | | | | | | | The arm_neon intrinsics can create virtual registers from the DPair register class which allows both even-odd and odd-even D-register pairs. This fixes PR12389. llvm-svn: 153603
* Also verify after ExpandPostRAPseudos.Jakob Stoklund Olesen2012-03-281-1/+1
| | | | llvm-svn: 153599
* Enable machine code verification after the late machine optimization passes.Jakob Stoklund Olesen2012-03-281-3/+3
| | | | | | | Branch folding invalidates liveness and disables liveness verification on some targets. llvm-svn: 153597
* Skip liveness verification when MRI->tracksLiveness() is false.Jakob Stoklund Olesen2012-03-281-105/+112
| | | | | | | | | Extract the liveness verification into its own method. This makes it possible to run the machine code verifier after liveness information is no longer required to be valid. llvm-svn: 153596
* Revert r153516: "Invalidate liveness in Thumb2ITBlockPass."Jakob Stoklund Olesen2012-03-282-8/+0
| | | | | | | | | | | | | | Revert r153519: "ARMLoadStoreOptimizer invalidates register liveness." These patches caused miscompilations in povray by turning off branch folding's updating of live-in lists. It turns out the the late scheduler depends on the live-in lists, even if it doesn't need correct kill flags. <rdar://problem/11139228> llvm-svn: 153593
* Allow removeLiveIn to be called with a register that isn't live-in.Jakob Stoklund Olesen2012-03-281-2/+2
| | | | | | | | | This avoids the silly double search: if (isLiveIn(Reg)) removeLiveIn(Reg); llvm-svn: 153592
* Revert r153521 as it's causing large regressions on the nightly testers.Chad Rosier2012-03-282-41/+0
| | | | | | | | Original commit message for r153521 (aka r153423): Use the new range metadata in computeMaskedBits and add a new optimization to instruction simplify that lets us remove an and when loding a boolean value. llvm-svn: 153587
* Fixed commuteInstructions bug where if its called pre-regalloc the subreg ↵Pete Cooper2012-03-281-6/+15
| | | | | | indices weren't commuted llvm-svn: 153579
* GlobalOpt: If we have an inbounds GEP from a ConstantAggregateZero global ↵Benjamin Kramer2012-03-281-0/+6
| | | | | | that we just determined to be constant, replace all loads from it with a zero value. llvm-svn: 153576
* Add another note about a missed compare with nsw arithmetic instcombine.Benjamin Kramer2012-03-281-0/+7
| | | | llvm-svn: 153574
* Fixup VST1.32 with writeback instruction. Also re-factor non-writeback version.Richard Barton2012-03-281-21/+13
| | | | llvm-svn: 153573
* Switch to WeakVHs in the value mapper, and aggressively prune dead basicChandler Carruth2012-03-281-3/+23
| | | | | | | | | blocks in the function cloner. This removes the last case of trivially dead code that I've been seeing in the wild getting inlined, analyzed, re-inlined, optimized, only to be deleted. Nukes a FIXME from the cleanup tests. llvm-svn: 153572
* More debug output.Eric Christopher2012-03-281-1/+2
| | | | llvm-svn: 153571
OpenPOWER on IntegriCloud