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* [DAG] Rewrite expression. NFC.Nirav Dave2017-08-101-2/+2
| | | | llvm-svn: 310608
* [X86] Keep dependencies when constructing loads in combineStoreNirav Dave2017-08-102-9/+12
| | | | | | | | | | | | | | | | Summary: Preserve chain dependecies between old and new loads constructed to prevent loads from reordering below later stores. Fixes PR34088. Reviewers: craig.topper, spatel, RKSimon, efriedma Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D36528 llvm-svn: 310604
* [Hexagon] Use isMetaInstruction instead of isDebugValueKrzysztof Parzyszek2017-08-103-3/+4
| | | | llvm-svn: 310601
* [sanitizer-coverage] Change cmp instrumentation to distinguish const operandsAlexander Potapenko2017-08-101-4/+40
| | | | | | | | | | | | | | | | | | | | | This implementation of SanitizerCoverage instrumentation inserts different callbacks depending on constantness of operands: 1. If both operands are non-const, then a usual __sanitizer_cov_trace_cmp[1248] call is inserted. 2. If exactly one operand is const, then a __sanitizer_cov_trace_const_cmp[1248] call is inserted. The first argument of the call is always the constant one. 3. If both operands are const, then no callback is inserted. This separation comes useful in fuzzing when tasks like "find one operand of the comparison in input arguments and replace it with the other one" have to be done. The new instrumentation allows us to not waste time on searching the constant operands in the input. Patch by Victor Chibotaru. llvm-svn: 310600
* [NewGVN] Add CL option to control the generation of phi-of-ops (disable by ↵Chad Rosier2017-08-101-0/+6
| | | | | | | | default). Differential Revision: https://reviews.llvm.org/D36478539 llvm-svn: 310594
* [SelectionDAG] Allow constant folding for implicitly truncating BUILD_VECTOR ↵Guy Blank2017-08-101-2/+16
| | | | | | | | | | | | | nodes. In FoldConstantArithmetic, handle BUILD_VECTOR nodes that do implicit truncation on the elements. This is similar to what is done in FoldConstantVectorArithmetic. Differential Revision: https://reviews.llvm.org/D36506 llvm-svn: 310593
* [libFuzzer] Update LibFuzzer w.r.t. the new comparisons instrumentation APIAlexander Potapenko2017-08-101-0/+35
| | | | | | | | | | Added the _sanitizer_cov_trace_const_cmp[1248] callbacks. For now they are implemented the same way as _sanitizer_cov_trace_cmp[1248]. For more details, please see https://reviews.llvm.org/D36465. Patch by Victor Chibotaru. llvm-svn: 310592
* [ValueTracking] Enabling ValueTracking patch by default (recommit). Part 2.Nikolai Bozhenov2017-08-101-9/+0
| | | | | | | | | | | | | | | The original patch was an improvement to IR ValueTracking on non-negative integers. It has been checked in to trunk (D18777, r284022). But was disabled by default due to performance regressions. Perf impact has improved. The patch would be enabled by default. Reviewers: reames, hfinkel Differential Revision: https://reviews.llvm.org/D34101 Patch by: Olga Chupina <olga.chupina@intel.com> llvm-svn: 310583
* [mips][microMIPS] Extending size reduction pass with XOR16Zoran Jovanovic2017-08-101-5/+43
| | | | | | | | | | Author: milena.vujosevic.janicic Reviewers: sdardis The patch extends size reduction pass for MicroMIPS. XOR instruction is transformed into 16-bit instruction XOR16, if possible. Differential Revision: https://reviews.llvm.org/D34239 llvm-svn: 310579
* [AArch64] Assembler support for v8.3 RCpcSam Parker2017-08-104-1/+28
| | | | | | | | | | Added assembler and disassembler support for the new Release Consistent processor consistent instructions, introduced with ARM v8.3-A for AArch64. Differential Revision: https://reviews.llvm.org/D36522 llvm-svn: 310575
* [ARM][AArch64] ARMv8.3-A enablementSam Parker2017-08-108-0/+35
| | | | | | | | | | | | | | | | | The beta ARMv8.3 ISA specifications have been released for AArch64 and AArch32, these can be found at: https://developer.arm.com/products/architecture/a-profile/exploration-tools An introduction to this architecture update can be found at: https://community.arm.com/processors/b/blog/posts/armv8-a-architecture-2016-additions This patch is the first in a series which will add ARM v8.3-A support in LLVM and Clang. It adds the necessary changes that create targets for both the ARM and AArch64 backends. Differential Revision: https://reviews.llvm.org/D36514 llvm-svn: 310561
* [SelectionDAG] When scalarizing vselect, don't assert onElad Cohen2017-08-102-2/+31
| | | | | | | | | | | | | | | | | | | | | | | a legal cond operand. When scalarizing the result of a vselect, the legalizer currently expects to already have scalarized the operands. While this is true for the true/false operands (which have the same type as the result), it is not case for the condition operand. On X86 AVX512, v1i1 is legal - this leads to operations such as '< N x type> vselect < N x i1> < N x type> < N x type>' where < N x type > is illegal to hit an assertion during the scalarization. The handling is similar to r205625. This also exposes the fact that (v1i1 extract_subvector) should be legal and selectable on AVX512 - We do this by custom lowering to vector_extract_elt. This still leaves us in some cases with redundant dag nodes which will be combined in a separate soon to come patch. This fixes pr33349. Differential revision: https://reviews.llvm.org/D36511 llvm-svn: 310552
* Revert part of r310296 to make it really NFC for instrumentation PGO.Dehao Chen2017-08-101-1/+1
| | | | | | | | | | | | | | Summary: Part of r310296 will disable PGOIndirectCallPromotion in ThinLTO backend if PGOOpt is None. However, as PGOOpt is not passed down to ThinLTO backend for instrumentation based PGO, that change would actually disable ICP entirely in ThinLTO backend, making it behave differently in instrumentation PGO mode. This change reverts that change, and only disable ICP there when it is SamplePGO. Reviewers: davidxl Reviewed By: davidxl Subscribers: sanjoy, mehdi_amini, eraman, llvm-commits Differential Revision: https://reviews.llvm.org/D36566 llvm-svn: 310550
* [LCG] Fix an assert in a on-scope-exit lambda that checked the contentsChandler Carruth2017-08-101-7/+9
| | | | | | | | | | of the returned value. Checking the returned value from inside of a scoped exit isn't actually valid. It happens to work when NRVO fires and the stars align, which they reliably do with Clang but don't, for example, on MSVC builds. llvm-svn: 310547
* [LVI] Fix LVI compile time regression around constantFoldUser()Hiroshi Yamauchi2017-08-101-14/+28
| | | | | | | | | | | | | | | | | | | Summary: Avoid checking each operand and calling getValueFromCondition() before calling constantFoldUser() when the instruction type isn't supported by constantFoldUser(). This fixes a large compile time regression in an internal build. Reviewers: sanjoy Reviewed By: sanjoy Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D36552 llvm-svn: 310545
* Linker: Create a function declaration when moving a non-prevailing alias of ↵Peter Collingbourne2017-08-101-0/+4
| | | | | | | | | | | | | | function type. We were previously creating a global variable of function type, which is invalid IR. This issue was exposed by r304690, in which we started asserting that global variables were of a valid type. Fixes PR33462. Differential Revision: https://reviews.llvm.org/D36438 llvm-svn: 310543
* [InstSimplify] Add test cases that show that simplifySelectWithICmpCond ↵Craig Topper2017-08-101-0/+1
| | | | | | doesn't work with non-canonical comparisons. llvm-svn: 310542
* [AMDGPU] Fix some Clang-tidy modernize-use-using and Include What You Use ↵Eugene Zelenko2017-08-1014-142/+227
| | | | | | warnings; other minor fixes (NFC). llvm-svn: 310541
* Fix thinlto cache key computation for cfi-icall.Evgeniy Stepanov2017-08-091-18/+55
| | | | | | | | | | | | | | | | | | Summary: Fixed PR33966. CFI code generation for users (not just callers) of a function depends on whether this function has a jumptable entry or not. This information needs to be encoded in of thinlto cache key. We filter the jumptable list against functions that are actually referenced in the current module. Subscribers: mehdi_amini, inglorion, eraman, hiraditya Differential Revision: https://reviews.llvm.org/D36346 llvm-svn: 310536
* ARM: Fix CMP_SWAP expansionMatthias Braun2017-08-092-32/+16
| | | | | | | | | | | | | | | | | | | | | | | Clean up after my misguided attempt in r304267 to "fix" CMP_SWAP returning an uninitialized status value. - I was always using tMOVi8 to zero the status register which cannot encode higher register numbers and llvm would silently miscompile) - Nobody was ever looking at that status value outside the expansion. ARMDAGToDAGISel::SelectCMP_SWAP() the only place creating CMP_SWAP instructions was not mapping anything to it. (The cmpxchg status value from llvm IR is lowered to a manual comparison after the CMP_SWAP) So this: - Renames the register from "status" to "temp" it make it obvious that it isn't used outside the expansion. - Remove the zeroing status/temp register. - Keep the live-in list improvements from r304267 Fixes http://llvm.org/PR34056 llvm-svn: 310534
* [Path] Sink predicate computations to their uses. NFCI.Benjamin Kramer2017-08-091-5/+4
| | | | llvm-svn: 310531
* [X86][Asm] Allow negative immediate to appear before bracketed expressionCoby Tayree2017-08-091-5/+0
| | | | | | | | | Currently, only non-negative immediate is allowed prior to a brac expression (memory reference). MASM / GAS does not have any problem cope with the left side of the real line, so we should be able to as well. Differntial Revision: https://reviews.llvm.org/D36229 llvm-svn: 310528
* [Hexagon] Ignore DBG_VALUEs when counting instructions in hexagon-early-ifKrzysztof Parzyszek2017-08-092-5/+8
| | | | llvm-svn: 310524
* [Linker] PR33527 - Linker::LinkOnlyNeeded should import AppendingLinkage globalsBenoit Belley2017-08-091-2/+12
| | | | | | | | | | | Linker::LinkOnlyNeeded should always import globals with AppendingLinkage. This resolves PR33527. Differential Revision: https://reviews.llvm.org/D34448 llvm-svn: 310522
* [RuntimeDyld][ORC] Add support for Thumb mode to RuntimeDyldMachOARM.Lang Hames2017-08-096-35/+200
| | | | | | | | | | | This patch adds support for thumb relocations to RuntimeDyldMachOARM, and adds a target-specific flags field to JITSymbolFlags (so that on ARM we can record whether each symbol is Thumb-mode code). RuntimeDyldImpl::emitSection is modified to ensure that stubs memory is correctly aligned based on the size returned by getStubAlignment(). llvm-svn: 310517
* AMDGPU: Fix assert on n inline asm constraintMatt Arsenault2017-08-091-6/+15
| | | | llvm-svn: 310515
* [Hexagon] Tie implicit uses to defs in predicated instructionsKrzysztof Parzyszek2017-08-091-6/+22
| | | | llvm-svn: 310514
* [InstCombine] narrow rotate left/right patterns to eliminate zext/trunc ↵Sanjay Patel2017-08-092-1/+73
| | | | | | | | | | | | | | | | | | | | | | | (PR34046) I couldn't find any smaller folds to help the cases in: https://bugs.llvm.org/show_bug.cgi?id=34046 after: rL310141 The truncated rotate-by-variable patterns elude all of the existing transforms because of multiple uses and knowledge about demanded bits and knownbits that doesn't exist without the whole pattern. So we need an unfortunately large pattern match. But by simplifying this pattern in IR, the backend is already able to generate rolb/rolw/rorb/rorw for x86 using its existing rotate matching logic (although there is a likely extraneous 'and' of the rotate amount). Note that rotate-by-constant doesn't have this problem - smaller folds should already produce the narrow IR ops. Differential Revision: https://reviews.llvm.org/D36395 llvm-svn: 310509
* Reduce variable scope by moving declaration into if clauseDavid Blaikie2017-08-091-8/+8
| | | | llvm-svn: 310506
* [asan] Fix instruction emission ordering with dynamic shadow.Matt Morehouse2017-08-091-3/+8
| | | | | | | | | | | | | | | | Summary: Instrumentation to copy byval arguments is now correctly inserted after the dynamic shadow base is loaded. Reviewers: vitalybuka, eugenis Reviewed By: vitalybuka Subscribers: hiraditya, llvm-commits Differential Revision: https://reviews.llvm.org/D36533 llvm-svn: 310503
* [X86][AVX512] Choose correct registers in vpbroadcastb/wGuy Blank2017-08-091-12/+43
| | | | | | | | | | | | Fixes the vpbroadcastb/w instructions which use GPRs as source operands, to use the correct registers. The full GPR should be used, and not the subregister, as it happens before the patch. Fixes pr33795 Differential Revision: https://reviews.llvm.org/D36479 llvm-svn: 310498
* [AMDGPU][MC][GFX9] Added 16-bit renamed and "_legacy" VALU opcodesDmitry Preobrazhensky2017-08-096-16/+79
| | | | | | | | | | See Bug 33629: https://bugs.llvm.org//show_bug.cgi?id=33629 Reviewers: vpykhtin, SamWot, arsenm Differential Revision: https://reviews.llvm.org/D36322 llvm-svn: 310497
* CFLAA: return MustAlias when pointers p, q are equal, i.e.,Nuno Lopes2017-08-091-1/+1
| | | | | | | | | | | must-alias(p, sz_p, p, sz_q) irrespective of access sizes sz_p, sz_q As discussed a couple of weeks ago on the ML. This makes the behavior consistent with that of BasicAA. AA clients already check the obj size themselves and may not require the obj size to match exactly the access size (e.g., in case of store forwarding) llvm-svn: 310495
* [ValueTracking] Turn a test into an assertion.Davide Italiano2017-08-091-3/+1
| | | | | | | As discussed with Chad, this should never happen, but this assertion is basically free, so, keep it around just in case. llvm-svn: 310493
* [ARM] Emit error when ARM exec mode is not available.Florian Hahn2017-08-092-2/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: A similar error message has been removed from the ARMTargetMachineBase constructor in r306939. With this patch, we generate an error message for the example below, compiled with -mcpu=cortex-m0, which does not have ARM execution mode. __attribute__((target("arm"))) int foo(int a, int b) { return a + b % a; } __attribute__((target("thumb"))) int bar(int a, int b) { return a + b % a; } By adding this error message to ARMBaseTargetMachine::getSubtargetImpl, we can deal with functions that set -thumb-mode in target-features. At the moment it seems like Clang does not have access to target-feature specific information, so adding the error message to the frontend will be harder. Reviewers: echristo, richard.barton.arm, t.p.northover, rengolin, efriedma Reviewed By: echristo, efriedma Subscribers: efriedma, aemerson, javed.absar, kristof.beyls Differential Revision: https://reviews.llvm.org/D35627 llvm-svn: 310486
* [X86][Asm]Allow far jmp/call to be picked when using explicit FWORD size ↵Coby Tayree2017-08-091-2/+2
| | | | | | | | | | | specifier Currently, far jmp/call which utilizes a 48bit memory operand would have been invoked via the 'lcall/ljmp' mnemonic (intel style). This patch align those variants to formal intel spec Differential Revision: https://reviews.llvm.org/D35846 llvm-svn: 310485
* [ValueTracking] Honour recursion limit.Davide Italiano2017-08-091-0/+4
| | | | | | | | | | | The recently improved support for `icmp` in ValueTracking (r307304) exposes the fact that `isImplied` condition doesn't really bail out if we hit the recursion limit (and calls `computeKnownBits` which increases the depth and asserts). Differential Revision: https://reviews.llvm.org/D36512 llvm-svn: 310481
* [AArch64] Assembler support for the ARMv8.2a dot product instructionsSjoerd Meijer2017-08-095-0/+39
| | | | | | | | | | | Dot product is an optional ARMv8.2a extension, see also the public architecture specification here: https://developer.arm.com/products/architecture/a-profile/exploration-tools. This patch adds AArch64 assembler support for these dot product instructions. Differential Revision: https://reviews.llvm.org/D36515 llvm-svn: 310480
* [ARM] Remove FeatureNoARM implies ModeThumb.Florian Hahn2017-08-091-3/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: By removing FeatureNoARM implies ModeThumb, we can detect cases where a function's target-features contain -thumb-mode (enables ARM codegen for the function), but the architecture does not support ARM mode. Previously, the implication caused the FeatureNoARM bit to be cleared for functions with -thumb-mode, making the assertion in ARMSubtarget::ARMSubtarget [1] pointless for such functions. This assertion is the only guard against generating ARM code for architectures without ARM codegen support. Is there a place where we could easily generate error messages for the user? At the moment, we would generate ARM code for Thumb-only architectures. X86 has the same behavior as ARM, as in it only has an assertion and no error message, but I think for ARM an error message would be helpful. What do you think? For the example below, `llc -mtriple=armv7m-eabi test.ll -o -` will generate ARM assembler (or fail with an assertion error with this patch). Note that if we run the resulting assembler through llvm-mc, we get an appropriate error message, but not when codegen is handled through clang. ``` define void @bar() #0 { entry: ret void } attributes #0 = { "target-features"="-thumb-mode" } ``` [1] https://github.com/llvm-mirror/llvm/blob/c1f7b54cef62e9c8aa745d40bea146a167bf844e/lib/Target/ARM/ARMSubtarget.cpp#L147 Reviewers: t.p.northover, rengolin, peter.smith, aadg, silviu.baranga, richard.barton.arm, echristo Reviewed By: rengolin, echristo Subscribers: efriedma, aemerson, javed.absar, kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D35569 llvm-svn: 310476
* [DAG] Explicitly cleanup merged load values during store merge. NFCI.Nirav Dave2017-08-091-2/+8
| | | | llvm-svn: 310474
* Fix -Wpessimizing-move warning.Haojian Wu2017-08-091-2/+2
| | | | llvm-svn: 310469
* [AsmParser][AVX512]Enhance OpMask/Zero/Merge syntax check rubostnessCoby Tayree2017-08-091-4/+8
| | | | | | | | Adopt a more strict approach regarding what marks should/can appear after a destination register, when operating upon an AVX512 platform. Differential Revision: https://reviews.llvm.org/D35785 llvm-svn: 310467
* [LSR / TTI / SystemZ] Eliminate TargetTransformInfo::isFoldableMemAccess()Jonas Paulsson2017-08-094-23/+18
| | | | | | | | | | | | | | | | | isLegalAddressingMode() has recently gained the extra optional Instruction* parameter, and therefore it can now do the job that previously only isFoldableMemAccess() could do. The SystemZ implementation of isLegalAddressingMode() has gained the functionality of checking for offsets, which used to be done with isFoldableMemAccess(). The isFoldableMemAccess() hook has been removed everywhere. Review: Quentin Colombet, Ulrich Weigand https://reviews.llvm.org/D35933 llvm-svn: 310463
* [LoopStrengthReduce] Don't neglect the Fixup.Offset in isAMCompletelyFolded().Jonas Paulsson2017-08-091-2/+2
| | | | | | | | In the recursive call to isAMCompletelyFolded(), the passed offset should be the sum of F.BaseOffset and Fixup.Offset. Review: Quentin Colombet. llvm-svn: 310462
* [mips] PR34083 - Wimplicit-fallthrough warning in MipsAsmParser.cppSimon Dardis2017-08-091-6/+7
| | | | | | | | | | | | Assert that a binary expression is actually a binary expression, rather than potientially incorrectly attempting to handle it as a unary expression. This resolves PR34083. Thanks to Simonn Pilgrim for reporting the issue! llvm-svn: 310460
* Suppress a warning. NFC.Gabor Horvath2017-08-091-1/+1
| | | | llvm-svn: 310459
* [AsmParser] Hash is not a comment on some targetsOliver Stannard2017-08-092-18/+0
| | | | | | | | | | | | The '#' token is not a comment for all targets (on ARM and AArch64 it marks an immediate operand), so we shouldn't treat it as such. Comments are already converted to AsmToken::EndOfStatement by AsmLexer::LexLineComment, so this check was unnecessary. Differential Revision: https://reviews.llvm.org/D36405 llvm-svn: 310457
* [LCG] Completely remove the map-based association of post-order numbersChandler Carruth2017-08-091-35/+34
| | | | | | | | | | | | | | | | | | | | | | | to Nodes when removing ref edges from a RefSCC. This map based association turns out to be pretty expensive for large RefSCCs and pointless as we already have embedded data members inside nodes that we use to track the DFS state. We can reuse one of those and the map becomes unnecessary. This also fuses the update of those numbers into the scan across the pending stack of nodes so that we don't walk the nodes twice during the DFS. With this I expect the new PM to be faster than the old PM for the test case I have been optimizing. That said, it also seems simpler and more direct in many ways. The side storage was always pretty awkward. The last remaining hot-spot in the profile of the LCG once this is done will be the edge iterator walk in the DFS. I'll take a look at improving that next. llvm-svn: 310456
* [GlobalOpt] Switch an explicit loop to llvm::all_of(). NFCI.Davide Italiano2017-08-091-5/+2
| | | | llvm-svn: 310453
* [LCG] Special case when removing a ref edge from a RefSCC leavesChandler Carruth2017-08-091-12/+29
| | | | | | | | | | | | | | | that RefSCC still connected. This is common and can be handled much more efficiently. As soon as we know we've covered every node in the RefSCC with the DFS, we can simply reset our state and return. This avoids numerous data structure updates and other complexity. On top of other changes, this appears to get new PM back to parity with the old PM for a large protocol buffer message source code. The dense map updates are very hot in this function. llvm-svn: 310451
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