| Commit message (Collapse) | Author | Age | Files | Lines | ||
|---|---|---|---|---|---|---|
| ... | ||||||
| * | When TCO is turned on, it is possible to end up with aliasing FrameIndex's. ↵ | Owen Anderson | 2010-09-20 | 1 | -2/+13 | |
| | | | | | | | | | | | | | Therefore, CombinerAA cannot assume that different FrameIndex's never alias, but can instead use MachineFrameInfo to get the actual offsets of these slots and check for actual aliasing. This fixes CodeGen/X86/2010-02-19-TailCallRetAddrBug.ll and CodeGen/X86/tailcallstack64.ll when CombinerAA is enabled, modulo a different register allocation sequence. llvm-svn: 114348 | |||||
| * | Simplify ARM callee-saved register handling by removing the distinction | Jim Grosbach | 2010-09-20 | 3 | -167/+59 | |
| | | | | | | | | | | | | | | | | | | | | between the high and low registers for prologue/epilogue code. This was a Darwin-only thing that wasn't providing a realistic benefit anymore. Combining the save areas simplifies the compiler code and results in better ARM/Thumb2 codegen. For example, previously we would generate code like: push {r4, r5, r6, r7, lr} add r7, sp, #12 stmdb sp!, {r8, r10, r11} With this change, we combine the register saves and generate: push {r4, r5, r6, r7, r8, r10, r11, lr} add r7, sp, #12 rdar://8445635 llvm-svn: 114340 | |||||
| * | Produce a R_X86_64_32 when the value is >=0. | Rafael Espindola | 2010-09-20 | 1 | -2/+5 | |
| | | | | | llvm-svn: 114339 | |||||
| * | Avoid splitting critical edge twice for a set of PHI uses. | Evan Cheng | 2010-09-20 | 1 | -17/+23 | |
| | | | | | llvm-svn: 114338 | |||||
| * | Fix the "unable to rename temporary" lit test failing on Windows. rename is ↵ | Francois Pichet | 2010-09-20 | 1 | -4/+11 | |
| | | | | | | | now copy + delete on Windows. Problem to be revisited for a permanent and clean solution. llvm-svn: 114320 | |||||
| * | Revert r114312 while I sort out some issues. | Owen Anderson | 2010-09-19 | 1 | -1/+1 | |
| | | | | | llvm-svn: 114313 | |||||
| * | Tentatively enabled DAGCombiner Alias Analysis by default. As far as I know, | Owen Anderson | 2010-09-19 | 1 | -1/+1 | |
| | | | | | | | | r114268 fixed the last of the blockers to enabling it. I will be monitoring for failures. llvm-svn: 114312 | |||||
| * | Add one more Core i7 model number. | Jakob Stoklund Olesen | 2010-09-19 | 1 | -0/+2 | |
| | | | | | llvm-svn: 114310 | |||||
| * | idiom recognition should catch this. | Chris Lattner | 2010-09-19 | 1 | -0/+32 | |
| | | | | | llvm-svn: 114304 | |||||
| * | add a readme. | Chris Lattner | 2010-09-19 | 1 | -0/+25 | |
| | | | | | llvm-svn: 114303 | |||||
| * | add corei7, the laptop version. | Chris Lattner | 2010-09-19 | 1 | -0/+1 | |
| | | | | | llvm-svn: 114302 | |||||
| * | X86Subtarget.h: Fix Cygwin's TD. | NAKAMURA Takumi | 2010-09-18 | 1 | -1/+1 | |
| | | | | | llvm-svn: 114297 | |||||
| * | Add the exit instruction to the PTX target. | Eric Christopher | 2010-09-18 | 22 | -16/+705 | |
| | | | | | | | Patch by Che-Liang Chiou <clchiou@gmail.com>! llvm-svn: 114294 | |||||
| * | Fix build. | Michael J. Spencer | 2010-09-18 | 1 | -0/+1 | |
| | | | | | llvm-svn: 114292 | |||||
| * | Make sure the STT_FILE symbol is the first one in the symbol table. | Rafael Espindola | 2010-09-18 | 1 | -0/+13 | |
| | | | | | llvm-svn: 114285 | |||||
| * | Unbreak msvc build. | Benjamin Kramer | 2010-09-18 | 1 | -1/+1 | |
| | | | | | llvm-svn: 114284 | |||||
| * | do not rely on the implicit-dereference semantics of dyn_cast_or_null | Gabor Greif | 2010-09-18 | 1 | -1/+1 | |
| | | | | | llvm-svn: 114278 | |||||
| * | do not rely on the implicit-dereference semantics of dyn_cast_or_null | Gabor Greif | 2010-09-18 | 1 | -4/+4 | |
| | | | | | llvm-svn: 114277 | |||||
| * | Fixed non-const iterator error. | Lang Hames | 2010-09-18 | 1 | -1/+1 | |
| | | | | | llvm-svn: 114273 | |||||
| * | Added a separate class (PBQPBuilder) for PBQP Problem construction. This ↵ | Lang Hames | 2010-09-18 | 7 | -2300/+309 | |
| | | | | | | | | | | | | | class can be extended to support custom constraints. For now the allocator still uses the old (internal) construction mechanism by default. This will be phased out soon assuming no issues with the builder system come up. To invoke the new construction mechanism just pass '-regalloc=pbqp -pbqp-builder' to llc. To provide custom constraints a Target just needs to extend PBQPBuilder and pass an instance of their derived builder to the RegAllocPBQP constructor. llvm-svn: 114272 | |||||
| * | Fix code that break critical edges for PHI uses. Watch out for multiple PHIs ↵ | Evan Cheng | 2010-09-18 | 1 | -71/+66 | |
| | | | | | | | in different blocks. llvm-svn: 114270 | |||||
| * | Invert the logic of reachesChainWithoutSideEffects(). What we want to check ↵ | Owen Anderson | 2010-09-18 | 1 | -7/+7 | |
| | | | | | | | | | | | is that there is NO path to the destination containing side effects, not that SOME path contains no side effects. In practice, this only manifests with CombinerAA enabled, because otherwise the chain has little to no branching, so "any" is effectively equivalent to "all". llvm-svn: 114268 | |||||
| * | Thumb opcodes for thumb calls. | Eric Christopher | 2010-09-18 | 1 | -1/+5 | |
| | | | | | llvm-svn: 114263 | |||||
| * | Add addrmode5 fp load support. Swap float/thumb operand adding to handle | Eric Christopher | 2010-09-18 | 1 | -5/+21 | |
| | | | | | | | thumb with floating point. llvm-svn: 114256 | |||||
| * | Floating point stores have a 3rd addressing mode type. | Eric Christopher | 2010-09-18 | 1 | -1/+9 | |
| | | | | | llvm-svn: 114254 | |||||
| * | factor out a simple helper function to create a label for PC-relative | Jim Grosbach | 2010-09-18 | 1 | -19/+17 | |
| | | | | | | | instructions (PICADD, PICLDR, et.al.) llvm-svn: 114243 | |||||
| * | PC-relative pseudo instructions are lowered and printed directly. Any encounter | Jim Grosbach | 2010-09-18 | 1 | -3/+2 | |
| | | | | | | | with one in the generic printing code is an error. llvm-svn: 114242 | |||||
| * | Fix vmov.f64 disassembly on targets where sizeof(long) != 8. | Benjamin Kramer | 2010-09-17 | 1 | -2/+2 | |
| | | | | | llvm-svn: 114240 | |||||
| * | Add MC-inst handling for tPICADD | Jim Grosbach | 2010-09-17 | 1 | -0/+26 | |
| | | | | | llvm-svn: 114237 | |||||
| * | Add target-specific DAG combiner for BUILD_VECTOR and VMOVRRD. An i64 | Bob Wilson | 2010-09-17 | 1 | -0/+27 | |
| | | | | | | | | | value should be in GPRs when it's going to be used as a scalar, and we use VMOVRRD to make that happen, but if the value is converted back to a vector we need to fold to a simple bit_convert. Radar 8407927. llvm-svn: 114233 | |||||
| * | Teach the (non-MC) instruction printer to use the cannonical names for push/pop, | Jim Grosbach | 2010-09-17 | 2 | -4/+72 | |
| | | | | | | | and shift instructions on ARM. Update the tests to match. llvm-svn: 114230 | |||||
| * | Avoid relocations in a common case. | Rafael Espindola | 2010-09-17 | 1 | -1/+10 | |
| | | | | | llvm-svn: 114229 | |||||
| * | Teach machine sink to | Evan Cheng | 2010-09-17 | 1 | -68/+218 | |
| | | | | | | | | | | | 1) Do forward copy propagation. This makes it easier to estimate the cost of the instruction being sunk. 2) Break critical edges on demand, including cases where the value is used by PHI nodes. Critical edge splitting is not yet enabled by default. llvm-svn: 114227 | |||||
| * | Rework arm fast isel branch and compare code. | Eric Christopher | 2010-09-17 | 1 | -8/+70 | |
| | | | | | llvm-svn: 114226 | |||||
| * | Machine CSE was forgetting to clear some data structures. | Evan Cheng | 2010-09-17 | 1 | -0/+7 | |
| | | | | | llvm-svn: 114222 | |||||
| * | Fix a potential bug that can cause miscomparison with and without debug info. | Evan Cheng | 2010-09-17 | 1 | -1/+1 | |
| | | | | | llvm-svn: 114220 | |||||
| * | Don't include <fenv.h> now that we have llvm/System/FEnv.h. | Jakob Stoklund Olesen | 2010-09-17 | 1 | -1/+0 | |
| | | | | | llvm-svn: 114219 | |||||
| * | Hook up verbose asm comment printing for SOImm operands in MC printer | Jim Grosbach | 2010-09-17 | 3 | -8/+6 | |
| | | | | | llvm-svn: 114215 | |||||
| * | trailing whitespace | Jim Grosbach | 2010-09-17 | 1 | -8/+8 | |
| | | | | | llvm-svn: 114212 | |||||
| * | Avoid emitting a PIC base register if no PIC addresses are needed. | Dan Gohman | 2010-09-17 | 1 | -2/+8 | |
| | | | | | | | This fixes rdar://8396318. llvm-svn: 114201 | |||||
| * | Attempt to support platforms which don't have fenv.h. | Dan Gohman | 2010-09-17 | 1 | -12/+7 | |
| | | | | | llvm-svn: 114196 | |||||
| * | Add skeleton infrastructure for the ARMMCCodeEmitter class. Patch by Jason Kim! | Jim Grosbach | 2010-09-17 | 3 | -0/+120 | |
| | | | | | llvm-svn: 114195 | |||||
| * | handle the upper16/lower16 target operand flags on symbol references for MC | Jim Grosbach | 2010-09-17 | 5 | -23/+60 | |
| | | | | | | | instruction lowering. llvm-svn: 114191 | |||||
| * | fix rdar://8444631 - encoder crash on 'enter' | Chris Lattner | 2010-09-17 | 4 | -4/+18 | |
| | | | | | | | What a weird instruction. llvm-svn: 114190 | |||||
| * | Fix an MSVC warning. | Daniel Dunbar | 2010-09-17 | 1 | -0/+3 | |
| | | | | | llvm-svn: 114184 | |||||
| * | expand PICLDR MC lowering to handle other PICLDR and PICSTR versions. | Jim Grosbach | 2010-09-17 | 1 | -11/+31 | |
| | | | | | llvm-svn: 114183 | |||||
| * | MC/Mach-O/i386: Fix a crash in relocation handling. | Daniel Dunbar | 2010-09-17 | 1 | -1/+2 | |
| | | | | | llvm-svn: 114176 | |||||
| * | Move the declaration SetInformationJobObject() outside of namespace. | NAKAMURA Takumi | 2010-09-17 | 1 | -9/+9 | |
| | | | | | | | It is also workaround for PR7927. llvm-svn: 114175 | |||||
| * | AlphaSchedule.td: 7bit-ize. | NAKAMURA Takumi | 2010-09-17 | 1 | -1/+1 | |
| | | | | | llvm-svn: 114173 | |||||
| * | System: Don't reexport ___eprintf when building with Clang; this symbol isn't | Daniel Dunbar | 2010-09-17 | 1 | -0/+7 | |
| | | | | | | | | used on Darwin anymore, and Clang might not always link with the library it is currently found in. llvm-svn: 114165 | |||||

