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llvm-svn: 150536
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Pretend that regmask interference ends at the 'dead' slot, even when
there is other interference ending at the 'reg' slot of the same
instruction.
llvm-svn: 150531
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Perform all comparisons at instruction granularity, and make sure
register masks on uses count in both gaps.
llvm-svn: 150530
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Only accept register masks when looking for an 'overlapping' def. When
Overlap is not set, the function searches for a proper definition of
Reg.
This means MI->modifiesRegister() considers register masks, but
MI->definesRegister() doesn't.
llvm-svn: 150529
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When a physreg is live in to a basic block, look for any instruction in
the block that clobbers the physreg.
The instruction doesn't have to properly redefine the register, any
overlapping clobber is OK.
This slightly changes live ranges when compiling with register masks.
llvm-svn: 150528
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The old DenseMap hashed order was very confusing.
llvm-svn: 150527
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llvm-svn: 150525
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llvm-svn: 150520
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all return type warnings.
llvm-svn: 150512
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Patch by Matt Johnson
llvm-svn: 150508
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The MachO back-end needs to emit the garbage collection flags specified in the
module flags. This is a WIP, so the front-end hasn't been modified to emit these
flags just yet. Documentation and front-end switching to occur soon.
llvm-svn: 150507
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llvm-svn: 150496
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only be live in to a block if it is the function entry point or a landing pad.
llvm-svn: 150494
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that are greater than the vector element type. For example BUILD_VECTOR
of type <1 x i1> with a constant i8 operand.
This patch fixes the assertion.
llvm-svn: 150477
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llvm-svn: 150471
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llvm-svn: 150466
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vector_shuffles shouldn't reach isel.
llvm-svn: 150462
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consistency with setExceptionPointerRegister(...).
llvm-svn: 150460
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llvm-svn: 150457
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llvm-svn: 150449
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llvm-svn: 150447
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llvm-svn: 150444
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This folds a simple loop tail into a loop latch. It covers the common (in fortran) case of postincrement loops. It's a "free" way to expose this type of loop to downstream loop optimizations that bail out on non-canonical loops (getLoopLatch is a heavily used check).
llvm-svn: 150439
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llvm-svn: 150438
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marking them as "live-in" into a BB ruins some invariants that the back-end
tries to maintain.
llvm-svn: 150437
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llvm-svn: 150436
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llvm-svn: 150433
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The scheduler will sometimes check the implicit-def list on instructions
to properly handle pre-colored DAG edges.
Also check any register mask operands for physreg clobbers.
llvm-svn: 150428
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llvm-svn: 150425
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(but not of) a block pointer do not cause the block pointer to
escape. This fixes rdar://10803830.
llvm-svn: 150424
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Clang patch (flags) will follow shortly.
The run-time library will also follow, but not immediately.
llvm-svn: 150423
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llvm-svn: 150411
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llvm-svn: 150404
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generate a shuffle node from two vectors of different types.
llvm-svn: 150383
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copy/paste fiasco.
llvm-svn: 150369
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llvm-svn: 150365
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- Use unsigned literals when the desired result is unsigned. This mostly allows unsigned/signed mismatch warnings to be less noisy even if they aren't on by default.
- Remove misplaced llvm_unreachable.
- Add static to a declaration of a function on MSVC x86 only.
- Change some instances of calling a static function through a variable to simply calling that function while removing the unused variable.
llvm-svn: 150364
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specific nodes when they get to isel.
llvm-svn: 150363
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llvm-svn: 150362
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have one use. Matches DAGCombiner and prevents vector_shuffles from reaching isel.
llvm-svn: 150360
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It caused 3 failures on pre-penryn and non-x86(generic) hosts.
llvm-svn: 150357
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If the DEC node had more than one user, it was doing this lowering but
leaving the original DEC node around and so decrementing twice.
Fixes PR11964.
llvm-svn: 150356
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v8i8 -> v8i32 on AVX machines. The codegen often scalarizes ANY_EXTEND nodes.
The DAGCombiner has two optimizations that can mitigate the problem. First,
if all of the operands of a BUILD_VECTOR node are extracted from an ZEXT/ANYEXT
nodes, then it is possible to create a new simplified BUILD_VECTOR which uses
UNDEFS/ZERO values to eliminate the scalar ZEXT/ANYEXT nodes.
Second, another dag combine optimization lowers BUILD_VECTOR into a shuffle
vector instruction.
In the case of zext v8i8->v8i32 on AVX, a value in an XMM register is to be
shuffled into a wide YMM register.
This patch modifes the second optimization and allows the creation of
shuffle vectors even when the newly generated vector and the original vector
from which we extract the values are of different types.
llvm-svn: 150340
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llvm-svn: 150332
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the process. Some of these are still a bit gross.
Still, this cuts 80 some lines out of this ridiculous file. ;]
llvm-svn: 150331
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llvm-svn: 150328
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to what's done for MachO and COFF. This allows advanced uses of the class to
be implemented outside the Object library. In particular, the DyldELFObject
subclass is now moved into its logical home - ExecutionEngine/RuntimeDyld.
This patch was reviewed by Michael Spencer.
llvm-svn: 150327
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that no optz'ns have run yet to convert invokes to calls.
llvm-svn: 150326
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llvm-svn: 150324
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to TargetLibraryInfo and use one of them in GlobalOpt.
llvm-svn: 150323
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