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* unnecessary includeAndrew Trick2012-02-101-1/+0
| | | | llvm-svn: 150228
* PTX no longer needs to provide its own backend.Andrew Trick2012-02-102-255/+21
| | | | llvm-svn: 150227
* RegAlloc superpass: includes phi elimination, coalescing, and scheduling.Andrew Trick2012-02-1015-109/+147
| | | | | | | | | | | | | | | | Creates a configurable regalloc pipeline. Ensure specific llc options do what they say and nothing more: -reglloc=... has no effect other than selecting the allocator pass itself. This patch introduces a new umbrella flag, "-optimize-regalloc", to enable/disable the optimizing regalloc "superpass". This allows for example testing coalscing and scheduling under -O0 or vice-versa. When a CodeGen pass requires the MachineFunction to have a particular property, we need to explicitly define that property so it can be directly queried rather than naming a specific Pass. For example, to check for SSA, use MRI->isSSA, not addRequired<PHIElimination>. CodeGen transformation passes are never "required" as an analysis ProcessImplicitDefs does not require LiveVariables. We have a plan to massively simplify some of the early passes within the regalloc superpass. llvm-svn: 150226
* whitespaceAndrew Trick2012-02-101-11/+11
| | | | llvm-svn: 150225
* Remove unused 'isAlias' parameter.Lang Hames2012-02-101-8/+3
| | | | llvm-svn: 150224
* ARM on darwin, v6 implies the presence of VFP for the assembler.Jim Grosbach2012-02-101-3/+11
| | | | | | rdar://10838899 llvm-svn: 150222
* Constrain the regmask search space for local live ranges.Jakob Stoklund Olesen2012-02-101-3/+13
| | | | | | | When checking a local live range for interference, restrict the binary search to the single block. llvm-svn: 150220
* Cache basic block boundaries for faster RegMaskSlots access.Jakob Stoklund Olesen2012-02-101-0/+9
| | | | | | | Provide API to get a list of register mask slots and bits in a basic block. llvm-svn: 150219
* Optimize LiveIntervals::intervalIsInOneMBB().Jakob Stoklund Olesen2012-02-101-17/+22
| | | | | | | | No looping and binary searches necessary. Return a pointer to the containing block instead of just a bool. llvm-svn: 150218
* Cache iterators. Some of these are expensive to create.Benjamin Kramer2012-02-101-14/+16
| | | | llvm-svn: 150214
* Change default error_code ctor to a 'named ctor' so it's more self-documenting.David Blaikie2012-02-096-59/+54
| | | | | | | | | | | Unify default construction of error_code uses on this idiom so that users don't feel compelled to make static globals for naming convenience. (unfortunately I couldn't make the original ctor private as some APIs don't return their result, instead using an out parameter (that makes sense to default construct) - which is a bit of a pity. I did, however, find/fix some cases of unnecessary default construction of error_code before I hit the unfixable cases) llvm-svn: 150197
* Add register mask support to RAGreedy.Jakob Stoklund Olesen2012-02-091-2/+25
| | | | | | | | This only adds the interference checks required for correctness. We still need to take advantage of register masks for the interference driven live range splitting. llvm-svn: 150191
* Tweak comment readability and grammar.Benjamin Kramer2012-02-091-2/+2
| | | | llvm-svn: 150183
* Test for commit access.Sirish Pande2012-02-091-2/+2
| | | | llvm-svn: 150178
* GlobalOpt: Be more aggressive about elminating side-effect free static dtors.Benjamin Kramer2012-02-091-4/+5
| | | | | | | | | GlobalOpt runs early in the pipeline (before inlining) and complex class hierarchies often introduce bitcasts or GEPs which weren't optimized away. Teach it to ignore side-effect free instructions instead of depending on other passes to remove them. llvm-svn: 150174
* Teach the MC and disassembler about SoftFail, and hook it up to ↵James Molloy2012-02-092-0/+9
| | | | | | UNPREDICTABLE on ARM. Wire this to tBLX in order to provide test coverage. llvm-svn: 150169
* More tweaks to get the size of the X86 disassembler tables down.Craig Topper2012-02-092-0/+7
| | | | llvm-svn: 150167
* Flatten some of the arrays in the X86 disassembler tables to reduce space ↵Craig Topper2012-02-093-7/+6
| | | | | | needed to store pointers on 64-bit hosts and reduce relocations needed at startup. Part of PR11953. llvm-svn: 150161
* Preserve physreg kills in MachineBasicBlock::SplitCriticalEdge.Lang Hames2012-02-091-4/+7
| | | | | | | Failure to preserve kills was causing LiveIntervals to miss some EFLAGS live ranges. Unfortunately I've been unable to reduce a good test case yet. llvm-svn: 150152
* Fix kill flags when moving instructions using LiveIntervals::moveInstr(...).Lang Hames2012-02-091-6/+23
| | | | llvm-svn: 150150
* Remove assertion. Not all use operands are reads.Lang Hames2012-02-091-3/+0
| | | | llvm-svn: 150149
* Improve TargetPassConfig. No intended functionality.Andrew Trick2012-02-091-98/+149
| | | | | | | Split CodeGen into stages. Distinguish between optimization and correctness. llvm-svn: 150122
* commentAndrew Trick2012-02-091-1/+1
| | | | llvm-svn: 150121
* Remove static initializer from DataStream.cppDavid Blaikie2012-02-091-12/+11
| | | | | | | | | | | If someone would prefer a clear name for the 'success' error_value we could come up with one - potentially just a 'named constructor' style 'error_value::success()' to make this expression more self-documenting. If I see this come up in other cases I'll certainly consider it. One step along the way to resolving PR11944. llvm-svn: 150120
* Erase dead copies that are clobbered by a call.Jakob Stoklund Olesen2012-02-091-5/+17
| | | | | | This does make a difference, at least when using RABasic. llvm-svn: 150118
* Handle register masks when searching for EFLAGS clobbers.Jakob Stoklund Olesen2012-02-091-0/+6
| | | | | | | Calls clobber the flags, but when using register masks there is no EFLAGS<imp-def> operand. llvm-svn: 150117
* Never delete instructions that define reserved registers.Jakob Stoklund Olesen2012-02-091-6/+10
| | | | | | | | | | | I think this was already the intention, but DeadMachineInstructionElim was accidentally tracking the liveness of reserved registers. Now, instructions with reserved defs are never deleted. This prevents the call stack adjustment instructions from getting deleted when enabling register masks. llvm-svn: 150116
* Handle register masks in MachineCopyPropagation.Jakob Stoklund Olesen2012-02-081-0/+17
| | | | | | | | For simplicity, treat calls with register masks as basic block boundaries. This means we can't copy propagate callee-saved registers across calls, but I don't think that is a big deal. llvm-svn: 150108
* [asan] unpoison the stack before every noreturn call. Fixes asan issue 37. ↵Kostya Serebryany2012-02-081-2/+17
| | | | | | llvm part llvm-svn: 150102
* Codegen pass definition cleanup. No functionality.Andrew Trick2012-02-0825-177/+106
| | | | | | | | | | | | | Moving toward a uniform style of pass definition to allow easier target configuration. Globally declare Pass ID. Globally declare pass initializer. Use INITIALIZE_PASS consistently. Add a call to the initializer from CodeGen.cpp. Remove redundant "createPass" functions and "getPassName" methods. While cleaning up declarations, cleaned up comments (sorry for large diff). llvm-svn: 150100
* Move pass configuration out of pass constructors: MachineLICM.Andrew Trick2012-02-082-5/+6
| | | | llvm-svn: 150099
* whitespaceAndrew Trick2012-02-081-11/+11
| | | | llvm-svn: 150098
* Move pass configuration out of pass constructors: StackSlotColoring.Andrew Trick2012-02-083-4/+4
| | | | llvm-svn: 150097
* Move pass configuration out of pass constructors: PostRAScheduler.Andrew Trick2012-02-083-8/+10
| | | | llvm-svn: 150096
* Move pass configuration out of pass constructors: BranchFolderPassAndrew Trick2012-02-085-20/+28
| | | | llvm-svn: 150095
* whitespaceAndrew Trick2012-02-088-80/+80
| | | | llvm-svn: 150094
* Added TargetPassConfig::setOptAndrew Trick2012-02-083-1/+14
| | | | llvm-svn: 150093
* Added Pass::createPass(ID) to handle pass configuration by IDAndrew Trick2012-02-082-2/+13
| | | | llvm-svn: 150092
* Move pass configuration out of pass constructors: TailDuplicate::PreRegAllocAndrew Trick2012-02-083-10/+11
| | | | llvm-svn: 150091
* Add Register mask support to RABasic.Jakob Stoklund Olesen2012-02-081-0/+14
| | | | | | | When a virtual register is live across a call, limit the search space to call-preserved registers. llvm-svn: 150081
* Use TSFlag bit to describe instruction properties.Brendon Cahoon2012-02-086-314/+208
| | | | | | | | Creating the isPredicated TSFlag enables the code to use the property defined in the instruction format instead of using a large switch statement. llvm-svn: 150078
* Keep track of register masks in LiveIntervalAnalysis.Jakob Stoklund Olesen2012-02-081-0/+62
| | | | | | | | | | | | | Build an ordered vector of register mask operands (i.e., calls) when computing live intervals. Provide a checkRegMaskInterference() function that computes a bit mask of usable registers for a live range. This is a quick way of determining of a live range crosses any calls, and restricting it to the callee saved registers if it does. Previously, we had to discover call clobbers for each candidate register independently. llvm-svn: 150077
* Use Use::set rather than finding the operand number of the useDuncan Sands2012-02-081-6/+3
| | | | | | and setting that. llvm-svn: 150074
* PathV2: Remove static StringRef ctors.Benjamin Kramer2012-02-081-4/+4
| | | | llvm-svn: 150071
* Fixed a bug in printing "cmp" pseudo ops.Elena Demikhovsky2012-02-084-41/+115
| | | | | | | | | | | | | | | | | | | | | | > This IR code > %res = call <8 x float> @llvm.x86.avx.cmp.ps.256(<8 x float> %a0, <8 x float> %a1, i8 14) > fails with assertion: > > llc: X86ATTInstPrinter.cpp:62: void llvm::X86ATTInstPrinter::printSSECC(const llvm::MCInst*, unsigned int, llvm::raw_ostream&): Assertion `0 && "Invalid ssecc argument!"' failed. > 0 llc 0x0000000001355803 > 1 llc 0x0000000001355dc9 > 2 libpthread.so.0 0x00007f79a30575d0 > 3 libc.so.6 0x00007f79a23a1945 gsignal + 53 > 4 libc.so.6 0x00007f79a23a2f21 abort + 385 > 5 libc.so.6 0x00007f79a239a810 __assert_fail + 240 > 6 llc 0x00000000011858d5 llvm::X86ATTInstPrinter::printSSECC(llvm::MCInst const*, unsigned int, llvm::raw_ostream&) + 119 I added the full testing for all possible pseudo-ops of cmp. I extended X86AsmPrinter.cpp and X86IntelInstPrinter.cpp. You'l also see lines alignments (unrelated to this fix) in X86IselLowering.cpp from my previous check-in. llvm-svn: 150068
* Remove a couple unneeded intrinsic patternsCraig Topper2012-02-081-6/+0
| | | | llvm-svn: 150067
* Remove GCC builtins for vpermilp* intrinsics as clang no longer needs them. ↵Craig Topper2012-02-082-32/+15
| | | | | | Custom lower the intrinsics to the vpermilp target specific node and remove intrinsic patterns. llvm-svn: 150060
* [fast-isel] Add support for SUBs with non-legal types.Chad Rosier2012-02-081-0/+5
| | | | llvm-svn: 150047
* [fast-isel] Add support for ORs with non-legal types.Chad Rosier2012-02-081-2/+13
| | | | llvm-svn: 150045
* Added MachineInstr::isBundled() to check if an instruction is part of a bundle.Andrew Trick2012-02-082-1/+11
| | | | llvm-svn: 150044
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