| Commit message (Collapse) | Author | Age | Files | Lines |
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DAG.UpdateNodeOperands() is called before (not after) the call to
TLI.LowerOperation().
llvm-svn: 50461
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targets.
llvm-svn: 50451
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that I don't make the same mistake in the future.
llvm-svn: 50446
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applied because
we were checking for it in the wrong order. This caused a miscompilation because the
return slot optimization assumes that the call it is dealing with is NOT a memcpy.
llvm-svn: 50444
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llvm-svn: 50442
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case fixes. Most
of this was suggested by Chris.
llvm-svn: 50441
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llvm-svn: 50437
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llvm-svn: 50436
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ModulePass :)
llvm-svn: 50433
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This fixes the second half of PR2262
llvm-svn: 50430
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llvm-svn: 50428
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This removes the existing bottleneck related to the removal of elements from
the middle of the queue.
Also fixes a subtle bug in ScheduleDAGRRList::CapturePred:
It was updating the state of the SUnit before removing it. As a result, the
comparison operators were working incorrectly and this SUnit could not be removed
from the queue properly.
Reviewed by Evan and Dan. Approved by Dan.
llvm-svn: 50412
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generalizes the previous code to handle the case when the string is not
an immediate to the strlen call (for example, crazy stuff like
strlen(c ? "foo" : "bart"+1) -> 3). This implements
gcc.c-torture/execute/builtins/strlen-2.c. I will generalize other
cases in simplifylibcalls to use the same routine later.
llvm-svn: 50408
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llvm-svn: 50406
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llvm-svn: 50390
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We now compile test2/test3 to:
_test2:
## InlineAsm Start
set %xmm0, %xmm1
## InlineAsm End
addps %xmm1, %xmm0
ret
_test3:
## InlineAsm Start
set %xmm0, %xmm1
## InlineAsm End
paddd %xmm1, %xmm0
ret
as expected.
llvm-svn: 50389
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towards PR2094. It now compiles the attached .ll file to:
_sad16_sse2:
movslq %ecx, %rax
## InlineAsm Start
%ecx %rdx %rax %rax %r8d %rdx %rsi
## InlineAsm End
## InlineAsm Start
set %eax
## InlineAsm End
ret
which is pretty decent for a 3 output, 4 input asm.
llvm-svn: 50386
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e.g.
vr1024<2> extract_subreg vr1025, 2
If vr1024 do not have the same register class as vr1025, it's not safe to coalesce this away. For example, vr1024 might be a GPR32 while vr1025 might be a GPR64.
llvm-svn: 50385
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llvm-svn: 50384
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llvm-svn: 50383
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the trip count.
llvm-svn: 50382
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units. If it's creating multiple CopyToReg nodes that are "flagged" together, it should not create a TokenFactor for it's chain outputs:
c1, f1 = CopyToReg
c2, f2 = CopyToReg
c3 = TokenFactor c1, c2
...
= user c3, ..., f2
Now that the two CopyToReg's and the user are "flagged" together. They effectively forms a single scheduling unit. The TokenFactor is now both an operand and a successor of the Flagged nodes.
llvm-svn: 50376
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be truncated to 32 bits. This fixes the recent Benchmarks/McCat/09-vor
regression on x86-64, among other things.
llvm-svn: 50372
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llvm-svn: 50370
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if the zext is not legal.
llvm-svn: 50368
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llvm-svn: 50367
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aggregate types.
llvm-svn: 50366
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reorder some of the members for clarity.
llvm-svn: 50365
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alignment. "Bump" of the pointer for the next allocated object to be of the specified alignment.
llvm-svn: 50362
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llvm-svn: 50361
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Patch by Anders Johnsen!
llvm-svn: 50360
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memcpy/memset expansion. It was a bug for the SVOffset value
to be used in the actual address calculations.
llvm-svn: 50359
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ComputeMaskedBits knows about cttz, ctlz, and ctpop. Teach
SelectionDAG's ComputeMaskedBits what InstCombine's knows
about SRem. And teach them both some things about high bits
in Mul, UDiv, URem, and Sub. This allows instcombine and
dagcombine to eliminate sign-extension operations in
several new cases.
llvm-svn: 50358
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sign-bit of x is known to be zero.
llvm-svn: 50357
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llvm-svn: 50355
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llvm-svn: 50342
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llvm-svn: 50341
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conversion open the door for many nasty implicit conversion issues, and
can be easily solved by initializing with (V.begin(), V.end()) when
needed.
This patch includes many small cleanups for sdisel also.
llvm-svn: 50340
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heap thrash on tiny (usually single-element) vectors.
llvm-svn: 50335
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multiple return values.
Bill, please pull this into Tak.
llvm-svn: 50332
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llvm-svn: 50330
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llvm-svn: 50329
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llvm-svn: 50328
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llvm-svn: 50325
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llvm-svn: 50324
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llvm-svn: 50316
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When choosing between constraints with multiple options,
like "ir", test to see if we can use the 'i' constraint and
go with that if possible. This produces more optimal ASM in
all cases (sparing a register and an instruction to load it),
and fixes inline asm like this:
void test () {
asm volatile (" %c0 %1 " : : "imr" (42), "imr"(14));
}
Previously we would dump "42" into a memory location (which
is ok for the 'm' constraint) which would cause a problem
because the 'c' modifier is not valid on memory operands.
Isn't it great how inline asm turns 'missed optimization'
into 'compile failed'??
Incidentally, this was the todo in
PowerPC/2007-04-24-InlineAsm-I-Modifier.ll
Please do NOT pull this into Tak.
llvm-svn: 50315
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llvm-svn: 50314
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llvm-svn: 50313
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- Make targetlowering.h fit in 80 cols.
- Make LowerAsmOperandForConstraint const.
- Make lowerXConstraint -> LowerXConstraint
- Make LowerXConstraint return a const char* instead of taking a string byref.
llvm-svn: 50312
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