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* transform obscured FP sign bit ops into a fabs/fneg using TLI hookSanjay Patel2016-06-024-28/+54
| | | | | | | | | | | | | | | | | | | This is effectively a revert of: http://reviews.llvm.org/rL249702 - [InstCombine] transform masking off of an FP sign bit into a fabs() intrinsic call (PR24886) and: http://reviews.llvm.org/rL249701 - [ValueTracking] teach computeKnownBits that a fabs() clears sign bits and a reimplementation as a DAG combine for targets that have IEEE754-compliant fabs/fneg instructions. This is intended to resolve the objections raised on the dev list: http://lists.llvm.org/pipermail/llvm-dev/2016-April/098154.html and: https://llvm.org/bugs/show_bug.cgi?id=24886#c4 In the interest of patch minimalism, I've only partly enabled AArch64. PowerPC, MIPS, x86 and others can enable later. Differential Revision: http://reviews.llvm.org/D19391 llvm-svn: 271573
* AMDGPU: Cleanup load testsMatt Arsenault2016-06-021-0/+14
| | | | | | | | | There are a lot of different kinds of loads to test for, and these were scattered around inconsistently with some redundancy. Try to comprehensively test all loads in a consistent way. llvm-svn: 271571
* [codeview] Fix a nasty use after free.Zachary Turner2016-06-021-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | StreamRef was designed to be a thin wrapper over an abstract stream interface that could itself be treated the same as any other stream interface. For this reason, it inherited publicly from StreamInterface, and stored a StreamInterface* internally. But StreamRef was also designed to be lightweight and easily copyable, similar to ArrayRef. This led to two misuses of the classes. 1) When creating a StreamRef A from another StreamRef B, it was possible to end up with A storing a pointer to B, even when B was a temporary object, leading to use after free. 2) The above situation could be repeated ad nauseum, so that A stores a pointer to B, which itself stores a pointer to another StreamRef C, and so on and so on, creating an unnecessarily level of nesting depth. This patch removes the public inheritance relationship between StreamRef and StreamInterface, making it so that we can never accidentally convert a StreamRef to a StreamInterface. llvm-svn: 271570
* AMDGPU: Temporary fix for broken store combineMatt Arsenault2016-06-021-0/+2
| | | | llvm-svn: 271567
* [CodeView] Use None instead of Void if there is no subprogramDavid Majnemer2016-06-022-3/+3
| | | | llvm-svn: 271566
* Fix the use of sys::MemoryFence after including WindowsSupport.h thatChandler Carruth2016-06-021-0/+5
| | | | | | r271558 introduced. llvm-svn: 271563
* Use false for bool instead of 0Matt Arsenault2016-06-021-1/+1
| | | | llvm-svn: 271562
* AMDGPU: Fix crashes on unknown processor nameMatt Arsenault2016-06-024-7/+9
| | | | | | | | | | | | | | If the processor name failed to parse for amdgcn, the resulting output would have R600 ISA in it. If the processor name was missing or invalid for R600, the wavefront size would not be set and there would be crashes from missing itinerary data. Fixes crashes in future commit caused by dividing by the unset/0 wavefront size. llvm-svn: 271561
* [X86] Define segment MI operands as regs instead of i8imm.Ahmed Bougacha2016-06-022-11/+12
| | | | | | | | | | | | | | | | | | | We've been pretending that segments are i8imm since the initial support (r68645), predating the addition of the SEGMENT_REG class (r81895). That happens to works, but is wrong, and inconsistent with how we print (e.g., X86ATTInstPrinter::printMemReference) and parse them (e.g., X86Operand::addMemOperands). This change shouldn't affect any tool users, but is visible to library users or out-of-tree tablegen backends: this causes MCOperandInfo for the segment op to have an RC instead of "unknown", and TII::getRegClass to actually return something. As the registers are reserved and no vregs of the class ever created, that shouldn't change anything. No test change; no suspicious getRegClass() in X86 and CodeGen. llvm-svn: 271559
* This is yet another attempt to re-instate r220932 as discussed inChandler Carruth2016-06-022-4/+39
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | D19271. Previous attempt was broken by NetBSD, so in this version I've made the fallback path generic rather than Windows specific and sent both Windows and NetBSD to it. I've also re-formatted the code some, and used an exact clone of the code in PassSupport.h for doing manual call-once using our atomics rather than rolling a new one. If this sticks, we can replace the fallback path for Windows with a Windows-specific implementation that is more reliable. Original commit message: This patch adds an llvm_call_once which is a wrapper around std::call_once on platforms where it is available and devoid of bugs. The patch also migrates the ManagedStatic mutex to be allocated using llvm_call_once. These changes are philosophically equivalent to the changes added in r219638, which were reverted due to a hang on Win32 which was the result of a bug in the Windows implementation of std::call_once. Differential Revision: http://reviews.llvm.org/D5922 llvm-svn: 271558
* pdbdump: print out COFF section headers.Rui Ueyama2016-06-021-1/+27
| | | | | | | | | | | | Unlike other sections that can grow to any size, the COFF section header stream has maximum length because each record is fixed size and the COFF file format limits the maximum number of sections. So I decided to not create a specific stream class for it. Instead, I added a member function to DbiStream class which returns a vector of COFF headers. Differential Revision: http://reviews.llvm.org/D20717 llvm-svn: 271557
* AArch64: Do not test for CPUs, use SubtargetFeaturesMatthias Braun2016-06-0210-115/+224
| | | | | | | | | | | | | | | | | | | | | | | | | | Testing for specific CPUs has a number of problems, better use subtarget features: - When some tweak is added for a specific CPU it is often desirable for the next version of that CPU as well, yet we often forget to add it. - It is hard to keep track of checks scattered around the target code; Declaring all target specifics together with the CPU in the tablegen file is a clear representation. - Subtarget features can be tweaked from the command line. To discourage people from using CPU checks in the future I removed the isCortexXX(), isCyclone(), ... functions. I added an getProcFamily() function for exceptional circumstances but made it clear in the comment that usage is discouraged. Reformat feature list in AArch64.td to have 1 feature per line in alphabetical order to simplify merging and sorting for out of tree tweaks. No functional change intended. Differential Revision: http://reviews.llvm.org/D20762 llvm-svn: 271555
* [InstCombine] remove guard for generating a vector selectSanjay Patel2016-06-021-15/+11
| | | | | | | | | | | | | | | | | This is effectively NFC because we already do this transform after r175380: http://reviews.llvm.org/rL175380 and also via foldBoolSextMaskToSelect(). This change should just make it a bit more efficient to match the pattern. The original guard was added in r95058: http://reviews.llvm.org/rL95058 A sampling of codegen for current in-tree targets shows no problems. This makes sense given that we're already producing the vector selects via the other transforms. llvm-svn: 271554
* [codeview] Fix crash when handling qualified void typesReid Kleckner2016-06-021-2/+1
| | | | | | | | | | The DIType* for void is the null pointer. A null DIType can never be a qualified type, so we can just exit the loop at this point and go to getTypeIndex(BaseTy). Fixes PR27984 llvm-svn: 271550
* Only attempt to detect AVG if SSE2 is availableDimitry Andric2016-06-021-0/+2
| | | | | | | | | | | | | | | | | | | | Summary: In PR29973 Sanjay Patel reported an assertion failure when a certain loop was optimized, for a target without SSE2 support. It turned out this was because of the AVG pattern detection introduced in rL253952. Prevent the assertion failure by bailing out early in `detectAVGPattern()`, if the target does not support SSE2. Also add a minimized test case. Reviewers: congh, eli.friedman, spatel Subscribers: emaste, llvm-commits Differential Revision: http://reviews.llvm.org/D20905 llvm-svn: 271548
* [esan|cfrag] Create the cfrag struct array for the runtimeQin Zhao2016-06-021-5/+115
| | | | | | | | | | | | | | Summary: Fills the cfrag struct variable with an array of struct information variables. Reviewers: aizatsky, bruening Subscribers: bruening, kcc, vitalybuka, eugenis, llvm-commits, zhaoqin Differential Revision: http://reviews.llvm.org/D20661 llvm-svn: 271547
* Ignore Lexing errors in macro body definitionsNirav Dave2016-06-023-23/+36
| | | | | | | | | | | | | | | | | | | | Do not issue lexing errors found during the parsing of macro body definitions and parseIdentifier function in AsmParser. This changes the Parser to not issue a lexing error when we reach an error, but rather when it is consumed allowing us time to examine and recover from an error. As a result, of this, we stop issuing a both lexing error and a parsing error in floating-literals test. Minor tweak to parseDirectiveRealValue to favor more meaningful lexing error over less helpful parse error. Reviewers: rnk, majnemer Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D20535 llvm-svn: 271542
* [CodeView] Implement function-type indicesDavid Majnemer2016-06-022-23/+47
| | | | | | | | | We still need to do something about member functions and calling conventions. Differential Revision: http://reviews.llvm.org/D20900 llvm-svn: 271541
* Remove all of the legacy home-grown atomic operations LLVM providedChandler Carruth2016-06-021-59/+0
| | | | | | | | | | | | | | | | | | | | | | | except for CompareAndSwap. That is the only one still being used anywhere now that statistics have been moved onto std::atomic. Also, add a warning to the header that we shouldn't introduce more uses of these old style atomics and instead should be using C++11's std::atomic facilities. Really hoping that we can hammer out the last couple of users here and replace them with something more localized and/or principled, but figured this was a pretty good start. =] Note that this patch will need to be reverted if r271504 needs to be reverted as that removes the last user of these. However, the biggest risk for that patch was MSVC 2013 and at least one bot has already passed where it would have failed there. I've tested MSVC 2015 using their web interfaces and other platforms seem fine, so I'm optimistic. Differential Revision: http://reviews.llvm.org/D20901 llvm-svn: 271540
* [COFF] Expose the PE debug data directory and dump itReid Kleckner2016-06-022-3/+71
| | | | | | | | | | | | This directory is used to find if there is a PDB associated with an executable. I plan to use this functionality to teach llvm-symbolizer whether it should use DIA or DWARF to symbolize a given DLL. Reviewers: majnemer Differential Revision: http://reviews.llvm.org/D20885 llvm-svn: 271539
* [profile] value profiling bug fix -- missing icall targets in profile-useXinliang David Li2016-06-021-1/+7
| | | | | | | | | | | | | | | | | Inline virtual functions has linkeonceodr linkage (emitted in comdat on supporting targets). If the vtable for the class is not emitted in the defining module, function won't be address taken thus its address is not recorded. At the mercy of the linker, if the per-func prf_data from this module (in comdat) is picked at link time, we will lose mapping from function address to its hash val. This leads to missing icall promotion. The second test case (currently disabled) in compiler_rt (r271528): instrprof-icall-prom.test demostrates the bug. The first profile-use subtest is fine due to linker order difference. With this change, no missing icall targets is found in instrumented clang's raw profile. llvm-svn: 271532
* [PEI, AArch64] Use empty spaces in stack area for local stack slot allocation.Geoff Berry2016-06-024-8/+147
| | | | | | | | | | | | | | | | | Summary: If the target requests it, use emptry spaces in the fixed and callee-save stack area to allocate local stack objects. AArch64: Change last callee-save reg stack object alignment instead of size to leave a gap to take advantage of above change. Reviewers: t.p.northover, qcolombet, MatzeB Subscribers: rengolin, mcrosier, llvm-commits, aemerson Differential Revision: http://reviews.llvm.org/D20220 llvm-svn: 271527
* [DAG] use getBitcast() to reduce codeSanjay Patel2016-06-021-33/+25
| | | | | | | | | | Although this was intended to be NFC, the test case wiggle shows a change in code scheduling/RA caused by a difference in the SDLoc() generation. Depending on how you look at it, this is the (dis)advantage of exact checking in regression tests. llvm-svn: 271526
* [Hexagon] Expand COPY pseudo-instructionKrzysztof Parzyszek2016-06-021-6/+11
| | | | | | | | Handle it locally instead of having the target-independent pass deal with it. The generic pass does not preserve implicit uses, which may be necessary. llvm-svn: 271520
* [RDF] Ignore implicit defs when resetting <kill> flagsKrzysztof Parzyszek2016-06-021-1/+5
| | | | llvm-svn: 271519
* [X86][SSE] Replace (V)CVTTPS2DQ and VCVTTPD2DQ truncating (round to zero) ↵Simon Pilgrim2016-06-022-23/+16
| | | | | | | | | | | | f32/f64 to i32 with generic IR (llvm) This patch removes the llvm intrinsics (V)CVTTPS2DQ and VCVTTPD2DQ truncation (round to zero) conversions and auto-upgrades to FP_TO_SINT calls instead. Note: I looked at updating CVTTPD2DQ as well but this still requires a lot more work to correctly lower. Differential Revision: http://reviews.llvm.org/D20860 llvm-svn: 271510
* This adds support for Cortex-A73 as an available target.Sjoerd Meijer2016-06-023-2/+12
| | | | | | Differential Revision: http://reviews.llvm.org/D20865 llvm-svn: 271508
* [CodeView] Use the right type index for long longDavid Majnemer2016-06-021-12/+17
| | | | | | We used T_INT8 instead of T_QUAD. llvm-svn: 271497
* [CodeView] Remove superfluous bitmathDavid Majnemer2016-06-021-1/+1
| | | | llvm-svn: 271495
* [codeview] Return type indices for typedefsDavid Majnemer2016-06-022-0/+13
| | | | | | | Use the type index of the underlying type unless we have a typedef from long to HRESULT; HRESULT typedefs are translated to T_HRESULT. llvm-svn: 271494
* [LibFuzzer] Disable compiling and running the LibFuzzer dataflow sanitizer ↵Dan Liew2016-06-024-1/+19
| | | | | | | | | | | tests on Apple platforms. This fixes a broken part of the build on OSX as the dataflow sanitizer is not supported on OSX yet. Differential Revision: http://reviews.llvm.org/D20894 llvm-svn: 271492
* [LibFuzzer] Reimplement how the optional user functions are called.Dan Liew2016-06-029-20/+171
| | | | | | | | | | | | | | | | | | | | | | | | | | The motivation for this change is to fix linking issues on OSX. However this only partially fixes linking issues (the uninstrumented tests and a few others won't succesfully link yet). This change introduces a struct of function pointers (``fuzzer::ExternalFuntions``) which when initialised will point to the optional functions if they are available. Currently these ``LLVMFuzzerInitialize`` and ``LLVMFuzzerCustomMutator`` functions. Two implementations of ``fuzzer::ExternalFunctions`` constructor are provided one for Linux and one for OSX. The OSX implementation uses ``dlsym()`` because the prior implementation using weak symbols does not work unless the additional flags are passed to the linker. The Linux implementation continues to use weak symbols because the ``dlsym()`` approach does not work unless additional flags are passed to the linker. Differential Revision: http://reviews.llvm.org/D20741 llvm-svn: 271491
* [pdb] Parse and dump section map and section contribsZachary Turner2016-06-027-276/+485
| | | | | | | Differential Revision: http://reviews.llvm.org/D20876 Reviewed By: rnk, ruiu llvm-svn: 271488
* [AVX512] Add 512-bit load/stores to fast isel.Craig Topper2016-06-021-0/+46
| | | | llvm-svn: 271486
* [X86] No need to use 256-bit VMOVNTPS for integer types when only AVX1 is ↵Craig Topper2016-06-021-15/+1
| | | | | | | | supported. VMOVNTDQ is available with AVX1. We were getting this right for v4i64 but not the other integer types. llvm-svn: 271482
* [X86] Add AVX 256-bit load and stores to fast isel.Craig Topper2016-06-021-9/+52
| | | | | | | | I'm not sure why this was missing for so long. This also exposed that we were picking floating point 256-bit VMOVNTPS for some integer types in normal isel for AVX1 even though VMOVNTDQ is available. In practice it doesn't matter due to the execution dependency fix pass, but it required extra isel patterns. Fixing that in a follow up commit. llvm-svn: 271481
* [X86] Use uint16_t for a couple arrays of instruction opcodes. NFCCraig Topper2016-06-021-2/+2
| | | | llvm-svn: 271480
* [AVX512] Remove LOADA/LOADU/STOREA/STOREU intrinsic types now that they are ↵Craig Topper2016-06-022-52/+3
| | | | | | unused. llvm-svn: 271479
* [AVX512] Remove masked load intrinsics. Clang now emits generic masked load ↵Craig Topper2016-06-022-32/+62
| | | | | | | | intrinsics instead. The intrinsics will be autoupgraded to the same generic masked loads. llvm-svn: 271478
* make icall pass name consistent /NFCXinliang David Li2016-06-021-3/+3
| | | | llvm-svn: 271467
* [libFuzzer] use __sanitizer_print_memory_profile to print the memory profile ↵Kostya Serebryany2016-06-022-1/+5
| | | | | | on OOM llvm-svn: 271465
* Inline isDereferenceableFromAttribute; NFCSanjoy Das2016-06-021-19/+8
| | | | | | | | Now that `Value::getPointerDereferenceableBytes` looks beyond just attributes, the name `isDereferenceableFromAttribute` is misleading. Just inline the function, since it is small and only used once. llvm-svn: 271456
* Remove Value::isPointerDereferenceable; NFCISanjoy Das2016-06-022-35/+19
| | | | | | | | ... and merge into `Value::getPointerDereferenceableBytes`. This was suggested by Artur Pilipenko in D20764 -- since we no longer allow loads of unsized types, there is no need anymore to have this special logic. llvm-svn: 271455
* [asan] Rename *UAR* into *UseAfterReturn*Vitaly Buka2016-06-021-7/+7
| | | | | | | | | | | | | | | Summary: To improve readability. PR27453 Reviewers: kcc, eugenis, aizatsky Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D20761 llvm-svn: 271447
* AMDGPU: Fix incorrectly setting kill flag when copying register tuplesMatt Arsenault2016-06-021-1/+1
| | | | | | | This fixes some verifier errors when trackLivenessAfterRegAlloc is enabled. llvm-svn: 271446
* Make MachineCopyPropagation preserve CFGMatt Arsenault2016-06-021-0/+5
| | | | | | This doesn't touch it as far as I can tell. llvm-svn: 271445
* AMDGPU: SIDebuggerInsertNops preserves CFGMatt Arsenault2016-06-022-0/+6
| | | | | | | This saves an additional run of the DominatorTree and MachineLoopInfo llvm-svn: 271444
* Avoid a load for local functions.Rafael Espindola2016-06-011-2/+7
| | | | llvm-svn: 271437
* [MemorySSA] Port to new pass managerGeoff Berry2016-06-014-67/+60
| | | | | | | | | | | | | | | | | Add support for the new pass manager to MemorySSA pass. Change MemorySSA to be computed eagerly upon construction. Change MemorySSAWalker to be owned by the MemorySSA object that creates it. Reviewers: dberlin, george.burgess.iv Subscribers: mcrosier, llvm-commits Differential Revision: http://reviews.llvm.org/D19664 llvm-svn: 271432
* SDAG: Drop a redundant replace and move the dead node removal closer. NFCJustin Bogner2016-06-011-6/+4
| | | | llvm-svn: 271429
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