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* [PartialInine]: add triaging optionsXinliang David Li2017-04-231-0/+24
| | | | | | | There are more bugs (runtime failures) triggered when partial inlining is turned on. Add options to help triaging problems. llvm-svn: 301148
* [SCEV] Move towards a verifier without false positivesSanjoy Das2017-04-231-68/+59
| | | | | | | | | | | | | | | This change reboots SCEV's current (off by default) verification logic to avoid false failures. Instead of stringifying trip counts, it maps old and new trip counts to the same ScalarEvolution "universe" and asks ScalarEvolution to compute the difference between them. If the difference comes out to be a non-zero constant, then (barring some corner cases) we *know* we messed up. I've not yet enabled this by default since it hits an exponential time issue in SCEV, but once I fix that, I'll flip it on by default in EXPENSIVE_CHECKS builds. llvm-svn: 301146
* [InstCombine] add/move folds for [not]-xorSanjay Patel2017-04-231-38/+67
| | | | | | | | | | | | We handled all of the commuted variants for plain xor already, although they were scattered around and sometimes folded less efficiently using distributive laws. We had no folds for not-xor. Handling all of these patterns consistently is part of trying to reinstate: https://reviews.llvm.org/rL300977 llvm-svn: 301144
* [PartialInlining] Add optimization remark supportXinliang David Li2017-04-231-4/+20
| | | | | | Differential Revision: http://reviews.llvm.org/D32387 llvm-svn: 301143
* [X86][SSE] Add scheduler class support for SSE42 (PCMPGT) instructionsSimon Pilgrim2017-04-231-6/+10
| | | | llvm-svn: 301142
* [JumpThread] We want to fold (not thread) when all predecessor go to single ↵Xin Tong2017-04-231-0/+30
| | | | | | | | | | | | | | | | | | | | | BB's successor. Summary: In case all predecessor go to a single successor of current BB. We want to fold (not thread). I failed to update the phi nodes properly in the last patch https://reviews.llvm.org/rL300657. Phi nodes values are per predecessor in LLVM. Reviewers: sanjoy Reviewed By: sanjoy Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D32400 llvm-svn: 301139
* Correct grammar. NFCXin Tong2017-04-231-1/+1
| | | | llvm-svn: 301135
* [APInt] In sext single word case, use SignExtend64 and let the APInt ↵Craig Topper2017-04-231-5/+2
| | | | | | | | constructor mask off any excess bits. The current code is trying to be clever with shifts to avoid needing to clear unused bits. But it looks like the compiler is unable to optimize out the unused bit handling in the APInt constructor. Given this its better to just use SignExtend64 and have more readable code. llvm-svn: 301133
* [InstCombine] add pattern matches for commuted variants of xor-to-xorSanjay Patel2017-04-231-34/+55
| | | | | | | | | There's probably some better way to write this that eliminates the code duplication without hurting readability, but at least this eliminates the logic holes and is hopefully slightly more efficient than creating new instructions. llvm-svn: 301129
* Revert "[APInt] Fix a few places that use APInt::getRawData to operate ↵Renato Golin2017-04-2313-34/+37
| | | | | | | | | | | | | | | | within the normal API." This reverts commit r301105, 4, 3 and 1, as a follow up of the previous revert, which broke even more bots. For reference: Revert "[APInt] Use operator<<= where possible. NFC" Revert "[APInt] Use operator<<= instead of shl where possible. NFC" Revert "[APInt] Use ashInPlace where possible." PR32754. llvm-svn: 301111
* Revert "[APInt] Add ashrInPlace method and implement ashr using it. Also fix ↵Renato Golin2017-04-231-26/+73
| | | | | | | | | | a bug in the shift by BitWidth handling." This reverts commit r301094, as it broke all ARM self-hosting bots. PR32754. llvm-svn: 301110
* [X86][MPX] Add load & store instructions of bnd values to ↵Ayman Musa2017-04-231-22/+30
| | | | | | | | | | getLoadStoreRegOpcode function. This is needed for a follow up patch that generates the memory folding tables. Differential Revision: https://reviews.llvm.org/D32232 llvm-svn: 301109
* [ARM] ScheduleDAGRRList::DelayForLiveRegsBottomUp must consider OptionalDefsArtyom Skrobov2017-04-231-0/+12
| | | | | | | | | | | | | | | | | Summary: D30400 has enabled tADC and tSBC instructions to be unglued, thereby allowing CPSR to remain live between Thumb1 scheduling units. Most Thumb1 instructions have an OptionalDef for CPSR; but the scheduler ignored the OptionalDefs, and could unwittingly insert a flag-setting instruction in between an ADDS and the corresponding ADC. Reviewers: javed.absar, atrick, MatzeB, t.p.northover, jmolloy, rengolin Reviewed By: javed.absar Subscribers: rogfer01, efriedma, aemerson, rengolin, llvm-commits, MatzeB Differential Revision: https://reviews.llvm.org/D31081 llvm-svn: 301106
* [APInt] Fix a few places that use APInt::getRawData to operate within the ↵Craig Topper2017-04-233-8/+5
| | | | | | | | | | normal API. getRawData exposes the internal type of the APInt class directly to its users. Ideally we wouldn't expose such an implementation detail. This patch fixes a few of the easy cases by using truncate, extract, or a rotate. llvm-svn: 301105
* [APInt] Use operator<<= where possible. NFCCraig Topper2017-04-233-5/+5
| | | | llvm-svn: 301104
* [APInt] Use operator<<= instead of shl where possible. NFCCraig Topper2017-04-238-20/+20
| | | | llvm-svn: 301103
* [ThinLTO/Summary] Rename anonymous globals as last action ...Davide Italiano2017-04-231-3/+6
| | | | | | | | | | | | | | ... in the per-TU -O0 pipeline. The problem is that there could be passes registered using `addExtensionsToPM()` introducing unnamed globals. Asan is an example, but there may be others. Building cppcheck with `-flto=thin` and `-fsanitize=address` triggers an assertion while we're reading bitcode (in lib/LTO), as the BitcodeReader assumes there are no unnamed globals (because the namer has run). Unfortunately I wasn't able to find an easy way to test this. I added a comment in the hope nobody moves this again. llvm-svn: 301102
* [APInt] Use ashInPlace where possible.Craig Topper2017-04-233-4/+4
| | | | llvm-svn: 301101
* Revert "Use DW_OP_stack_value when reconstructing variable values with ↵Adrian Prantl2017-04-231-32/+13
| | | | | | | | arithmetic." This reverts commit r301093 while investigating stage2 bot breakage. llvm-svn: 301099
* [APInt] Add ashrInPlace method and implement ashr using it. Also fix a bug ↵Craig Topper2017-04-221-73/+26
| | | | | | | | in the shift by BitWidth handling. For single word, shift by BitWidth was always returning 0, but for multiword it was based on original sign. Now single word matches multi word. llvm-svn: 301094
* Use DW_OP_stack_value when reconstructing variable values with arithmetic.Adrian Prantl2017-04-221-13/+32
| | | | | | | | | | | | | When the location description of a source variable involves arithmetic on the value itself, it needs to be marked with DW_OP_stack_value since it is not describing the variable's location, but rather its value. This is a follow-up to r297971 and fixes the source testcase quoted in the comment in debuginfo-dce.ll. rdar://problem/30725338 llvm-svn: 301093
* [APInt] Remove unnecessary min with BitWidth from countTrailingOnesSlowCase.Craig Topper2017-04-221-1/+2
| | | | | | The unused upper bits are guaranteed to be 0 so we don't need to worry about accidentally counting them. llvm-svn: 301091
* [PartialInlining] Using existing hasAddressTaken interface to legality check/NFCXinliang David Li2017-04-221-19/+3
| | | | llvm-svn: 301090
* [InstCombine] use 'match' to reduce code; NFCISanjay Patel2017-04-221-36/+31
| | | | | | | | | | | The later uses of dyn_castNotVal in this block are either incomplete (doesn't handle vector constants) or overstepping (shouldn't handle constants at all), but this first use is just unnecessary. 'I' is obviously not a constant, and it can't be a not-of-a-not because that would already be instsimplified. llvm-svn: 301088
* [globalisel][tablegen] Revise API for ComplexPattern operands to improve ↵Daniel Sanders2017-04-225-27/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | flexibility. Summary: Some targets need to be able to do more complex rendering than just adding an operand or two to an instruction. For example, it may need to insert an instruction to extract a subreg first, or it may need to perform an operation on the operand. In SelectionDAG, targets would create SDNode's to achieve the desired effect during the complex pattern predicate. This worked because SelectionDAG had a form of garbage collection that would take care of SDNode's that were created but not used due to a later predicate rejecting a match. This doesn't translate well to GlobalISel and the churn was wasteful. The API changes in this patch enable GlobalISel to accomplish the same thing without the waste. The API is now: InstructionSelector::OptionalComplexRendererFn selectArithImmed(MachineOperand &Root) const; where Root is the root of the match. The return value can be omitted to indicate that the predicate failed to match, or a function with the signature ComplexRendererFn can be returned. For example: return OptionalComplexRendererFn( [=](MachineInstrBuilder &MIB) { MIB.addImm(Immed).addImm(ShVal); }); adds two immediate operands to the rendered instruction. Immed and ShVal are captured from the predicate function. As an added bonus, this also reduces the amount of information we need to provide to GIComplexOperandMatcher. Depends on D31418 Reviewers: aditya_nandakumar, t.p.northover, qcolombet, rovka, ab, javed.absar Reviewed By: ab Subscribers: dberris, kristof.beyls, igorb, llvm-commits Differential Revision: https://reviews.llvm.org/D31761 llvm-svn: 301079
* Avoid using relocations for ref_addr in .dwo filesDavid Blaikie2017-04-223-13/+14
| | | | | | | | | | In dwo files the fixed offset can be used - if the dwos are linked into a dwp, the dwo consumer must use the dwp tables to find out where the original range of the debug_info was and resolve the "section relative" value relative to that original range - effectively avoiding/reimplementing the relocation handling. llvm-svn: 301072
* Fix for PR32740 - Invalid floating type, unreachable between r300969 and r301029Artur Pilipenko2017-04-221-2/+5
| | | | | | The bug was introduced by r301018 "[InstCombine] fadd double (sitofp x), y check that the promotion is valid". The patch didn't expect that fadd can be on vectors not necessarily scalars. Add vector support along with the test. llvm-svn: 301070
* [APInt] Add WORD_MAX constant and use it instead of UINT64_MAX. NFCCraig Topper2017-04-221-15/+15
| | | | llvm-svn: 301069
* Remove the unnecessary virtual dtor from the DIEUnit hierarchy (in favor of ↵David Blaikie2017-04-222-4/+4
| | | | | | | | | protected dtor in the base, final derived classes with public non-virtual dtors) These objects are never polymorphically owned/destroyed, so the virtual dtor was unnecessary. llvm-svn: 301068
* LowerSwitch: Fix producing invalid IR on unreachable codeMatt Arsenault2017-04-211-0/+8
| | | | | | | | If a switch was in an unreachable block that branched to a block with a phi, it would leave phis with missing predecessors. llvm-svn: 301064
* Move Split DWARF handling to an MC option/command line argument rather than ↵David Blaikie2017-04-211-15/+4
| | | | | | | | | | | | | | | | | | | using metadata Since Split DWARF needs to name the actual .dwo file that is generated, it can't be known at the time the llvm::Module is produced as it may be merged with other Modules before the object is generated and that object may be generated with any name. By passing the Split DWARF file name when LLVM is producing object code the .dwo file name in the object file can match correctly. The support for Split DWARF for implicit modules remains the same - using metadata to store the dwo name and dwo id so that potentially multiple skeleton CUs referring to different dwo files can be generated from one llvm::Module. llvm-svn: 301062
* Fixup for r301054: Use an explicit constructor.Kuba Mracek2017-04-211-1/+1
| | | | llvm-svn: 301061
* Remove a repeated comment line. NFC.Easwaran Raman2017-04-211-1/+0
| | | | llvm-svn: 301059
* Fixup for r301054: Only use __attribute__((no_sanitize("memory"))) when it's ↵Kuba Mracek2017-04-211-1/+5
| | | | | | available. llvm-svn: 301058
* AArch64FrameLowering: Check if the ExtraCSSpill register is actually unusedMatthias Braun2017-04-211-6/+6
| | | | | | | | | | | The code assumed that when saving an additional CSR register (ExtraCSSpill==true) we would have a free register throughout the function. This was not true if this CSR register is also used to pass values as in the swiftself case. rdar://31451816 llvm-svn: 301057
* [libFuzzer] Always build libFuzzer Kuba Mracek2017-04-211-34/+40
| | | | | | | | | | | | | | | There are two reasons why users might want to build libfuzzer: - To fuzz LLVM itself - To get the libFuzzer.a archive file, so that they can attach it to their code This change always builds libfuzzer, and supports the second use case if the specified flag is set. The point of this patch is to have something that can potentially be shipped with the compiler, and this also ensures that the version of libFuzzer is correct to use with that compiler. Patch by George Karpenkov. Differential Revision: https://reviews.llvm.org/D32096 llvm-svn: 301054
* [Object] Fix some Clang-tidy modernize and Include What You Use warnings; ↵Eugene Zelenko2017-04-213-114/+135
| | | | | | other minor fixes (NFC). llvm-svn: 301049
* Re-commit r301040 "X86: Don't emit zero-byte functions on Windows"Hans Wennborg2017-04-2116-35/+32
| | | | | | | | | In addition to the original commit, tighten the condition for when to pad empty functions to COFF Windows. This avoids running into problems when targeting e.g. Win32 AMDGPU, which caused test failures when this was committed initially. llvm-svn: 301047
* [Test commit] Remove extra newline.Frederich Munch2017-04-211-1/+0
| | | | llvm-svn: 301046
* InferAddressSpaces: Infer for just GEPsMatt Arsenault2017-04-211-3/+7
| | | | | | | | | | | Fixes leaving intermediate flat addressing computations where a GEP instruction's source is a constant expression. Still leaves behind a trivial addrspacecast + gep pair that instcombine is able to handle, which ideally could be folded here directly. llvm-svn: 301044
* [PartialInliner] Partial inliner needs to check use kind before transformationXinliang David Li2017-04-211-0/+19
| | | | | | Differential Revision: https://reviews.llvm.org/D32373 llvm-svn: 301042
* Revert r301040 "X86: Don't emit zero-byte functions on Windows"Hans Wennborg2017-04-2116-31/+35
| | | | | | This broke almost all bots. Reverting while fixing. llvm-svn: 301041
* X86: Don't emit zero-byte functions on WindowsHans Wennborg2017-04-2116-35/+31
| | | | | | | | | | | | | | | | | | Empty functions can lead to duplicate entries in the Guard CF Function Table of a binary due to multiple functions sharing the same RVA, causing the kernel to refuse to load that binary. We had a terrific bug due to this in Chromium. It turns out we were already doing this for Mach-O in certain situations. This patch expands the code for that in AsmPrinter::EmitFunctionBody() and renames TargetInstrInfo::getNoopForMachoTarget() to simply getNoop() since it seems it was used for not just Mach-O anyway. Differential Revision: https://reviews.llvm.org/D32330 llvm-svn: 301040
* ARM: make sure we use all entries in a vector before forming a vpaddl.Tim Northover2017-04-211-5/+5
| | | | | | | | | Otherwise there's some mismatch, and we'll either form an illegal type or an illegal node. Thanks to Eli Friedman for pointing out the problem with my original solution. llvm-svn: 301036
* [InstCombine] revert r300977 and r301021Sanjay Patel2017-04-211-14/+4
| | | | | | This can cause an inf-loop. Investigating... llvm-svn: 301035
* typoAdrian Prantl2017-04-211-1/+1
| | | | llvm-svn: 301030
* AMDGPU/GFX9: Enable FastFMAF32Konstantin Zhuravlyov2017-04-211-1/+2
| | | | | | Differential Revision: https://reviews.llvm.org/D32363 llvm-svn: 301029
* AMDGPU: Temporarily disable packed inlinable literals (v2f16, v2i16)Konstantin Zhuravlyov2017-04-211-0/+9
| | | | | | Differential Revision: https://reviews.llvm.org/D32361 llvm-svn: 301028
* AMDGPU: Fix S_PACK_HH_B32_B16Konstantin Zhuravlyov2017-04-211-1/+1
| | | | | | | | - We really ought to zero out lower 16 bits Differential Revision: https://reviews.llvm.org/D32356 llvm-svn: 301026
* [AMDGPU] Handle SI_MASKED_UNREACHABLE in instruction emitterYaxun Liu2017-04-211-0/+6
| | | | | | | | | | | | SI_MASKED_UNREACHABLE does not have machine instruction encoding. It needs special handling in AMDGPUAsmPrinter::EmitInstruction like some other pseudo instructions. This patch fixes compilation failure of RadeonRays. Differential Revision: https://reviews.llvm.org/D32364 llvm-svn: 301025
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