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* AVX: Move the ZEXT/ANYEXT DAGCo optimizations to the lowering of these ↵Nadav Rotem2012-12-282-45/+71
| | | | | | optimizations. The old test cases still cover all of these lowering/optimizations. The single change that we have is that now anyext does not need to zero a register, because it does not use the exact code path as the zero_extend. llvm-svn: 171178
* Reverse the 'if' condition and reduce the indentation.Nadav Rotem2012-12-271-29/+28
| | | | llvm-svn: 171172
* Merge basic_sse12_fp_binop_p_int and basic_sse12_fp_binop_p_y_int multiclasses.Craig Topper2012-12-271-28/+28
| | | | llvm-svn: 171171
* AVX/AVX2: Move the SEXT lowering code from a target specific DAGco to a ↵Nadav Rotem2012-12-272-42/+53
| | | | | | lowering function. llvm-svn: 171170
* Merge basic_sse12_fp_binop_p and basic_sse12_fp_binop_p_y multiclasses.Craig Topper2012-12-271-49/+41
| | | | llvm-svn: 171166
* Make this parameter be named consistently with most otherChandler Carruth2012-12-271-2/+2
| | | | | | getAnalysisUsage implementations. llvm-svn: 171157
* [ASan] Fix lifetime intrinsics handling. Now for each intrinsic we check if ↵Alexey Samsonov2012-12-271-69/+91
| | | | | | it describes one of 'interesting' allocas. Assume that allocas can go through casts and phi-nodes before apperaring as llvm.lifetime arguments llvm-svn: 171153
* On AVX/AVX2 the type v8i1 is legalized to v8i16, which is an XMM sizedNadav Rotem2012-12-271-15/+106
| | | | | | | | | | register. In most cases we actually compare or select YMM-sized registers and mixing the two types creates horrible code. This commit optimizes some of the transition sequences. PR14657. llvm-svn: 171148
* AVX/AVX2: Move the code that lowers vector-trunc from a DAGCo-hook to custom ↵Nadav Rotem2012-12-271-106/+96
| | | | | | | | | | lowering hook. The vector truncs were scalarized during LegalizeVectorOps, later vectorized again by some DAGCombine optimization and finally, lowered by a dagcombing optimization. Now, they are properly lowered during LegalizeVectorOps. No new testcase because the original testcases still work. llvm-svn: 171146
* Add hasSideEffects=0 to some forms of ROUND, RCP, and RSQRT.Craig Topper2012-12-271-0/+3
| | | | llvm-svn: 171143
* Refactor DAGCombinerInfo. Change the different booleans that indicate if we ↵Nadav Rotem2012-12-272-3/+3
| | | | | | | | are before or after different runs of DAGCo, with the CombineLevel enum. Also, added a new API for checking if we are running before or after the LegalizeVectorOps phase. llvm-svn: 171142
* Move single letter 'P' prefix out of multiclass now that tablegen allows ↵Craig Topper2012-12-271-86/+85
| | | | | | defm to start with #NAME. This makes instruction names more searchable again. llvm-svn: 171141
* Update tablegen parser to allow defm names to start with #NAME.Craig Topper2012-12-271-1/+5
| | | | llvm-svn: 171140
* Add hasSideEffects=0 to some shift and rotate instructions. None of which ↵Craig Topper2012-12-271-1/+5
| | | | | | are currently used by code generation. llvm-svn: 171137
* Mark the divide instructions as hasSideEffects=0.Craig Topper2012-12-271-0/+2
| | | | llvm-svn: 171136
* For the dwarf5 split debug info code split out the string sectionEric Christopher2012-12-272-21/+53
| | | | | | per compile unit/skeleton compile unit. Update tests accordingly. llvm-svn: 171133
* Add hasSideEffects=0 to CMP*rr_REV.Craig Topper2012-12-271-0/+1
| | | | llvm-svn: 171130
* Add mayLoad, mayStore, and hasSideEffects tags to BT/BTS/BTR/BTC ↵Craig Topper2012-12-271-19/+43
| | | | | | instructions. Shouldn't change any functionality since they don't have patterns to select them. llvm-svn: 171128
* Right now all of the relocations are 32-bit dwarf, and the relocationEric Christopher2012-12-271-4/+3
| | | | | | | | information doesn't return an addend for Rel relocations. Go ahead and use this information to fix relocation handling inside dwarfdump for 32-bit ELF REL. llvm-svn: 171126
* If all of the write objects are identified then we can vectorize the loop ↵Nadav Rotem2012-12-261-1/+5
| | | | | | | | even if the read objects are unidentified. PR14719. llvm-svn: 171124
* Fix operands and encoding form for ARPL instruction. Register form had and ↵Craig Topper2012-12-261-2/+2
| | | | | | reversed. Memory form writes memory, but was marked as MRMSrcMem. llvm-svn: 171123
* Add hasSideEffects=0 to some atomic instructions.Craig Topper2012-12-261-1/+1
| | | | llvm-svn: 171122
* Mark the AL/AX/EAX forms of the basic arithmetic operations has never having ↵Craig Topper2012-12-261-43/+44
| | | | | | side effects. llvm-svn: 171121
* 80 columns. No functionality change.Nick Lewycky2012-12-261-1/+1
| | | | llvm-svn: 171120
* Remove mid-optimizer warning. This situation should be handled differently,Nick Lewycky2012-12-261-5/+2
| | | | | | | such as by a compiler warning, a check in clang -fsanitizer=undefined, being optimized to unreachable, or a combination of the above. PR14722. llvm-svn: 171119
* Mark all the _REV instructions as not having side effects. They aren't ↵Craig Topper2012-12-264-9/+10
| | | | | | really emitted by the backend, but it reduces the number of instructions in the output files with unmodelled side effects to make auditing easier. llvm-svn: 171118
* Remove a special conditional setting of neverHasSideEffects if the ↵Craig Topper2012-12-261-4/+3
| | | | | | instruction didn't have a pattern. This was leftover from when tablegen used to complain if things were already inferred from patterns. llvm-svn: 171117
* LoopVectorizer: Optimize the vectorization of consecutive memory access when ↵Nadav Rotem2012-12-262-23/+71
| | | | | | the iteration step is -1 llvm-svn: 171114
* [msan] Raise alignment of origin stores/loads when possible.Evgeniy Stepanov2012-12-261-5/+11
| | | | | | | Origin alignment is as high as the alignment of the corresponding application location, but never less than 4. llvm-svn: 171110
* [msan] Expand the file comment with track-origins info.Evgeniy Stepanov2012-12-261-5/+27
| | | | llvm-svn: 171109
* Merge still more SSE/AVX instruction definitions.Craig Topper2012-12-261-43/+15
| | | | llvm-svn: 171103
* Merge more SSE/AVX instruction definitions.Craig Topper2012-12-261-129/+49
| | | | llvm-svn: 171102
* Fix 80 column violation.Craig Topper2012-12-261-2/+2
| | | | llvm-svn: 171097
* Fix class name in comment.Craig Topper2012-12-261-1/+1
| | | | llvm-svn: 171096
* Merge SSE/AVX PCMPEQ/PCMPGT instruction definitions.Craig Topper2012-12-261-62/+12
| | | | llvm-svn: 171095
* Remove 'v' from mnemonic to fix asm matching failures.Craig Topper2012-12-261-1/+1
| | | | llvm-svn: 171093
* Use an additional multiclass to merge the 128/256-bit SSE/AVX instruction ↵Craig Topper2012-12-261-108/+42
| | | | | | definitions for a bunch of SSE2 integer arithmetic instructions. llvm-svn: 171092
* Reformat the docs.Nadav Rotem2012-12-261-20/+7
| | | | llvm-svn: 171091
* Use an additional multiclass to merge the 128/256-bit SSE/AVX instruction ↵Craig Topper2012-12-261-30/+18
| | | | | | definitions for PAND/POR/PXOR/PANDN llvm-svn: 171087
* Merge an AVX/SSE 256-bit and 128-bit multiclass.Craig Topper2012-12-261-26/+15
| | | | llvm-svn: 171086
* Mark VANDNPD/VANDNPDS as not commutable.Craig Topper2012-12-261-1/+2
| | | | llvm-svn: 171085
* Remove alignment from a bunch more VEX encoded operations in the folding tables.Craig Topper2012-12-261-47/+47
| | | | llvm-svn: 171082
* Remove alignment from folding table for VMOVUPD as an unaligned instruction ↵Craig Topper2012-12-261-1/+1
| | | | | | it shouldn't require alignment... llvm-svn: 171081
* Remove alignment requirements from (V)EXTRACTPS. This instruction does ↵Craig Topper2012-12-261-2/+2
| | | | | | 32-bit stores which aren't required to be aligned on SSE or AVX. llvm-svn: 171080
* BBVectorize: Use VTTI to compute costs for intrinsics vectorizationHal Finkel2012-12-261-12/+64
| | | | | | | | | | | | For the time being this includes only some dummy test cases. Once the generic implementation of the intrinsics cost function does something other than assuming scalarization in all cases, or some target specializes the interface, some real test cases can be added. Also, for consistency, I changed the type of IID from unsigned to Intrinsic::ID in a few other places. llvm-svn: 171079
* Remove alignment requirement from VCVTSS2SD in folding tables. Reverting ↵Craig Topper2012-12-261-2/+2
| | | | | | r171049. This instruction doesn't require alignment. llvm-svn: 171078
* LoopVectorize: Enable vectorization of the fmuladd intrinsicHal Finkel2012-12-251-0/+1
| | | | llvm-svn: 171076
* BBVectorize: Enable vectorization of the fmuladd intrinsicHal Finkel2012-12-251-0/+1
| | | | llvm-svn: 171075
* Expand PPC64 atomic load and storeHal Finkel2012-12-251-0/+2
| | | | | | | | Use of store or load with the atomic specifier on 64-bit types would cause instruction-selection failures. As with the 32-bit case, these can use the default expansion in terms of cmp-and-swap. llvm-svn: 171072
* [msan] Fix handling of vectors of pointers.Evgeniy Stepanov2012-12-251-2/+7
| | | | | | | VectorType::getInteger() can not be used with them, because pointer size depends on the target. llvm-svn: 171070
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