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* [libFuzzer] Disable afl tests on non-posix systems.Marcos Pividori2017-02-012-0/+4
| | | | | | | | AflDriver is not supported on non posix systems. Differential Revision: https://reviews.llvm.org/D29422 llvm-svn: 293830
* [libFuzzer] Disable equivalence tests on non posix systems.Marcos Pividori2017-02-011-0/+2
| | | | | | | | We can not run this test until we implement shared memory on Windows. Differential Revision: https://reviews.llvm.org/D29421 llvm-svn: 293829
* [libFuzzer] Isolate merge tests that require posix.Marcos Pividori2017-02-012-8/+23
| | | | | | Differential Revision: https://reviews.llvm.org/D29420 llvm-svn: 293828
* [libFuzzer] Add features `windows` and `posix` for lit tests.Marcos Pividori2017-02-013-0/+11
| | | | | | | | | | | | Add 2 features: posix and windows. Sometimes we want some specific tests only for posix and we use: REQUIRES: posix Sometimes we want some specific tests only for windows and we use: REQUIRES: windows Differential Revision: https://reviews.llvm.org/D29418 llvm-svn: 293827
* [libFuzzer] Accept different extensions.Marcos Pividori2017-02-011-1/+1
| | | | | | Differential Revision: https://reviews.llvm.org/D29417 llvm-svn: 293826
* [libFuzzer] Fix test because cmd prompt does not expand wildcard.Marcos Pividori2017-02-011-1/+1
| | | | | | | | | | Commands should expand the wildcards on Windows, the cmd prompt doesn't. Because of that sancov was not finding the needed file. To deal with this, we use ls and xargs from gnu win utils. Differential Revision: https://reviews.llvm.org/D29374 llvm-svn: 293825
* Revert r293820: Return Error instead of bool from mergeTypeStreams().Rui Ueyama2017-02-011-21/+17
| | | | | | It broke buildbots. llvm-svn: 293824
* [ValueTracking] remove a FIXME for something we don't want to do; NFCSanjay Patel2017-02-011-4/+0
| | | | | | | | The comment was added with: https://reviews.llvm.org/rL293773 ...but there would be a cost to implement this and possibly no payoff. llvm-svn: 293823
* Return Error instead of bool from mergeTypeStreams().Rui Ueyama2017-02-011-17/+21
| | | | | | | | | | Previously, mergeTypeStreams returns only true or false, so it was impossible to know the reason if it failed. This patch changes the function signature so that it returns an Error object. Differential Revision: https://reviews.llvm.org/D29362 llvm-svn: 293820
* Remove an assertion that doesn't hold when mixing -g and -gmlt throughPaul Robinson2017-02-011-1/+0
| | | | | | | | LTO. Part of PR31437. Differential Revision: http://reviews.llvm.org/D29310 llvm-svn: 293818
* [InstCombine] move folds for shift-shift pairs; NFCISanjay Patel2017-02-011-48/+34
| | | | | | | | | | | Although this is 'no-functional-change-intended', I'm adding tests for shl-shl and lshr-lshr pairs because there is no existing test coverage for those folds. It seems like we should be able to remove some code from foldShiftedShift() at this point because we're handling those patterns on the general path. llvm-svn: 293814
* Shut up another GCC warning about operator precedence. NFC.Michael Kuperstein2017-02-011-1/+1
| | | | llvm-svn: 293812
* AMDGPU: Allow clustering flat memory operationsMatt Arsenault2017-02-011-1/+2
| | | | llvm-svn: 293809
* [JumpThread] No need to erase BB from LoopHeaders. NFC.Jun Bum Lim2017-02-011-14/+1
| | | | | | | | | | | | | | Summary: No need to try to ease BB from LoopHeaders as we already know that BB is not in LoopHeaders. Reviewers: hsung, majnemer, mcrosier, haicheng, rengolin Reviewed By: rengolin Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D29232 llvm-svn: 293802
* [IPSCCP] Don't propagate return values of functions marked as noinline.Davide Italiano2017-02-011-1/+6
| | | | | | | | | | | | This tries to address what Hal defined (in the post-commit review of r293727) a long-standing problem with noinline, where we end up de facto inlining trivial functions e.g. __attribute__((noinline)) int patatino(void) { return 5; } because of return value propagation. llvm-svn: 293799
* [mips] Parse the 'bopt' and 'nobopt' directives in IAS.Simon Dardis2017-02-011-0/+8
| | | | | | | | | | | | | | | The GAS assembler supports the ".set bopt" directive but according to the sources it doesn't do anything. It's supposed to optimize branches by filling the delay slot of a branch with it's target. This patch teaches the MIPS asm parser to accept both and warn in the case of 'bopt' that the bopt directive is unsupported. This resolves PR/31841. Thanks to Sean Bruno for reporting the issue! llvm-svn: 293798
* [pdb] Add a new command for analyzing hash collisions.Zachary Turner2017-02-011-0/+4
| | | | | | | | | | This introduces the `analyze` subcommand. For now there is only one option, to analyze hash collisions in the type streams. In the future, however, we could add many more things here, such as performing size analyses, compacting, and statistics about the type of records etc. llvm-svn: 293795
* [libFuzzer] Do not use llvm-objdump for disassembling a DSO.Marcos Pividori2017-02-011-4/+1
| | | | | | | | | | | | | | | | | When disassembling a DSO, for calls to functions from the PLT, llvm-objdump only prints the offset from the PLT, like: <.plt+0x30>. While objdump and dumpbin print the function name, like: <__sanitizer_cov_trace_pc_guard@plt> When analyzing the coverage in libFuzzer we dissasemble and look for the calls to __sanitizer_cov_trace_pc_guard. So, this fails when using llvm-objdump on a DSO. Differential Revision: https://reviews.llvm.org/D29372 llvm-svn: 293791
* [libFuzzer] Properly check if we can use dumpbin.Marcos Pividori2017-02-011-1/+1
| | | | | | | | The flag "/sumary" is necessary, otherwise it returns a non-zero value. Differential Revision: https://reviews.llvm.org/D29371 llvm-svn: 293790
* [LV] Move interleaved access helper functions to VectorUtils (NFC)Matthew Simpson2017-02-014-127/+94
| | | | | | | | | | | | This patch moves some helper functions related to interleaved access vectorization out of LoopVectorize.cpp and into VectorUtils.cpp. We would like to use these functions in a follow-on patch that improves interleaved load and store lowering in (ARM/AArch64)ISelLowering.cpp. One of the functions was already duplicated there and has been removed. Differential Revision: https://reviews.llvm.org/D29398 llvm-svn: 293788
* [InstCombine] Allow InstCombine to merge adjacent guardsSanjoy Das2017-02-011-6/+14
| | | | | | | | | | | | | | | | | | | | Summary: If there are two adjacent guards with different conditions, we can remove one of them and include its condition into the condition of another one. This patch allows InstCombine to merge them by the following pattern: guard(a); guard(b) -> guard(a & b). Reviewers: reames, apilipenko, igor-laevsky, anna, sanjoy Reviewed By: sanjoy Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D29378 llvm-svn: 293778
* [X86][SSE] Remove unused argument. NFCI.Simon Pilgrim2017-02-011-9/+6
| | | | llvm-svn: 293777
* AMDGPU: Improve nsw/nuw/exact when promoting uniform i16 opsMatt Arsenault2017-02-011-18/+41
| | | | | | | | | | | | These were simply preserving the flags of the original operation, which was too conservative in most cases and incorrect for mul. nsw/nuw may be needed for some combines to cleanup messes when intermediate sext_inregs are introduced later. Tested valid combinations with alive. llvm-svn: 293776
* [ImplicitNullCheck] Extend canReorder scopeSanjoy Das2017-02-011-3/+4
| | | | | | | | | | | | | | | | | | Summary: This change allows a re-order of two intructions if their uses are overlapped. Patch by Serguei Katkov! Reviewers: reames, sanjoy Reviewed By: sanjoy Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D29120 llvm-svn: 293775
* [ValueTracking] avoid crashing from bad assumptions (PR31809)Sanjay Patel2017-02-011-0/+17
| | | | | | | | | | | | | A program may contain llvm.assume info that disagrees with other analysis. This may be caused by UB in the program, so we must not crash because of that. As noted in the code comments: https://llvm.org/bugs/show_bug.cgi?id=31809 ...we can do better, but this at least avoids the assert/crash in the bug report. Differential Revision: https://reviews.llvm.org/D29395 llvm-svn: 293773
* [mips] Fix an initialization issue with MipsABIInfo in MipsTargetELFStreamerSimon Dardis2017-02-011-0/+12
| | | | | | | | | | | | | | DebugInfoDWARFTests is the only user so far which initializes the MCObjectStreamer without initializing the ASMParser. The MIPS backend relies on the ASMParser to initialize the MipsABIInfo object and to update the target streamer with it. This should turn the mips buildbots green. Reviewers: atanasyan, zoran.jovanovic Differential Revision: https://reviews.llvm.org/D28025 llvm-svn: 293772
* [PowerPC] Fix sjlj pseduo instructions to use G8RC_NOX0 register classKit Barton2017-02-011-2/+3
| | | | | | | | | | | | | | The the following instructions: - LD/LWZ (expanded from sjLj pseudo-instructions) - LXVL/LXVLL vector loads - STXVL/STXVLL vector stores all require G8RC_NO0X class registers for RA. Differential Revision: https://reviews.llvm.org/D29289 Committed for Lei Huang llvm-svn: 293769
* [X86][SSE] Merge SSE2 PINSRW lowering with SSE41 PINSRB/PINSRW lowering. NFCI.Simon Pilgrim2017-02-011-32/+21
| | | | | | These are identical apart from the extra SSE41 guard for PINSRB. llvm-svn: 293766
* [legalizetypes] Push fp16 -> fp32 extension node to worklist. Florian Hahn2017-02-013-5/+7
| | | | | | | | | | | | | | | | | | | | | Summary: This way, the type legalization machinery will take care of registering the result of this node properly. This patches fixes all failing fp16 test cases with expensive checks. (CodeGen/ARM/fp16-promote.ll, CodeGen/ARM/fp16.ll, CodeGen/X86/cvt16.ll CodeGen/X86/soft-fp.ll) Reviewers: t.p.northover, baldrick, olista01, bogner, jmolloy, davidxl, ab, echristo, hfinkel Reviewed By: hfinkel Subscribers: mehdi_amini, hfinkel, davide, RKSimon, aemerson, llvm-commits Differential Revision: https://reviews.llvm.org/D28195 llvm-svn: 293765
* [LoopPredication] Add a new line to debug output in LoopPredication passArtur Pilipenko2017-02-011-1/+1
| | | | llvm-svn: 293762
* [ARM] Enable Cortex-M23 and Cortex-M33 support.Javed Absar2017-02-011-0/+10
| | | | | | | | | | | | | Add both cores to the target parser and TableGen. Test that eabi attributes are set correctly for both cores. Additionally, test the absence and presence of MOVT in Cortex-M23 and Cortex-M33, respectively. Committed on behalf of Sanne Wouda. Reviewers : rengolin, olista01. Differential Revision: https://reviews.llvm.org/D29073 llvm-svn: 293761
* [LoopUnroll] Use addClonedBlockToLoopInfo to add loop header to LI (NFC).Florian Hahn2017-02-011-11/+8
| | | | | | | | | | | | | | | | | | | | Summary: I have a similar patch up for review already (D29173). If you prefer I can squash them both together. Also I think there more potential for code sharing between LoopUnroll.cpp and LoopUnrollRuntime.cpp. Do you think patches for that would be worthwhile? Reviewers: mkuper, mzolotukhin Reviewed By: mkuper, mzolotukhin Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D29311 llvm-svn: 293758
* *MacroFusion.cpp: Suppress warnings to eliminate \param(s). [-Wdocumentation]NAKAMURA Takumi2017-02-012-3/+3
| | | | llvm-svn: 293744
* [X86] For AVX1/AVX2 isel, don't use FP move instructions for 128-bit ↵Craig Topper2017-02-011-78/+74
| | | | | | | | | | loads/stores of integer types. For SSE we use fp because of the smaller encoding, but that doesn't apply to AVX. So just do the natural thing so we don't have to explain why we aren't. We can't do this for 256-bit loads/stores since integer loads and stores aren't available in AVX1 so we need fallback patterns since the integer types are legal. This doesn't affect any tests because execution domain fixing freely converts the instructions anyway. Honestly, we could probably rely on it for the SSE size optimization too. llvm-svn: 293743
* [AArch64] Add new target feature to fuse literal generationEvandro Menezes2017-02-014-0/+46
| | | | | | | | | This feature enables the fusion of such operations on Cortex A57, as recommended in its Software Optimisation Guide, sections 4.14 and 4.15. Differential revision: https://reviews.llvm.org/D28698 llvm-svn: 293739
* [AArch64] Add new subtarget feature to fuse AES crypto operationsEvandro Menezes2017-02-015-2/+26
| | | | | | | | | | This feature enables the fusion of such operations on Cortex A57, as recommended in its Software Optimisation Guide, section 4.13, and on Exynos M1. Differential revision: https://reviews.llvm.org/D28491 llvm-svn: 293738
* [CodeGen] Move MacroFusion to the targetEvandro Menezes2017-02-0113-323/+536
| | | | | | | | | | | | | This patch moves the class for scheduling adjacent instructions, MacroFusion, to the target. In AArch64, it also expands the fusion to all instructions pairs in a scheduling block, beyond just among the predecessors of the branch at the end. Differential revision: https://reviews.llvm.org/D28489 llvm-svn: 293737
* [ImplicitNullCheck] NFC isSuitableMemoryOp cleanupSanjoy Das2017-02-011-13/+23
| | | | | | | | | | | | | | | | | | | | | | | | | Summary: isSuitableMemoryOp method is repsonsible for verification that instruction is a candidate to use in implicit null check. Additionally it checks that base register is not re-defined before. In case base has been re-defined it just returns false and lookup is continued while any suitable instruction will not succeed this check as well. This results in redundant further operations. So when we found that base register has been re-defined we just stop. Patch by Serguei Katkov! Reviewers: reames, sanjoy Reviewed By: sanjoy Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D29119 llvm-svn: 293736
* SanitizerCoverage: Support sanitizer guard section on darwinJustin Bogner2017-02-011-13/+30
| | | | | | | MachO's sections need a segment as well as a section name, and the section start and end symbols are spelled differently than on ELF. llvm-svn: 293733
* MCMacho: Allow __thread_ptr section after dwarf sectionsMatthias Braun2017-02-011-1/+2
| | | | | | Differential Revision: https://reviews.llvm.org/D29315 llvm-svn: 293730
* [Mips] Fix some Clang-tidy modernize and Include What You Use warnings; ↵Eugene Zelenko2017-02-0113-163/+227
| | | | | | other minor fixes (NFC). llvm-svn: 293729
* Fix regalloc assignment of overlapping registersStanislav Mekhanoshin2017-02-011-0/+21
| | | | | | | | | | | | | | | | SplitEditor::defFromParent() can create a register copy. If register is a tuple of other registers and not all lanes are used a copy will be done on a full tuple regardless. Later register unit for an unused lane will be considered free and another overlapping register tuple can be assigned to a different value even though first register is live at that point. That is because interference only look at liveness info, while full register copy clobbers all lanes, even unused. This patch fixes copy to only cover used lanes. Differential Revision: https://reviews.llvm.org/D29105 llvm-svn: 293728
* [IPSCCP] Teach how to not propagate return values of naked functions.Davide Italiano2017-02-011-1/+4
| | | | | | Differential Revision: https://reviews.llvm.org/D29360 llvm-svn: 293727
* AMDGPU: Cleanup fmin/fmax legacy functionMatt Arsenault2017-02-014-13/+14
| | | | | | Use a more specific subtarget check and combine hasOneUse checks llvm-svn: 293726
* InferAddressSpaces: Handle selectMatt Arsenault2017-02-011-0/+8
| | | | | | | This fails to handle some cases where one of the inputs is a constant to be fixed in a later commit. llvm-svn: 293723
* [libFuzzer] increase the default size for shmemKostya Serebryany2017-02-014-12/+12
| | | | llvm-svn: 293722
* [XRay] Define the InstrumentationMap typeDean Michael Berris2017-02-012-0/+197
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: This change implements the instrumentation map loading library which can understand both YAML-defined instrumentation maps, and ELF 64-bit object files that have the XRay instrumentation map section. We break it out into a library on its own to allow for other applications to deal with the XRay instrumentation map defined in XRay-instrumented binaries. This type provides both raw access to the logical representation of the instrumentation map entries as well as higher level functions for converting a function ID into a function address. At this point we only support ELF64 binaries and YAML-defined XRay instrumentation maps. Future changes should extend this to support 32-bit ELF binaries, as well as other binary formats (like MachO). As part of this change we also migrate all uses of the extraction logic that used to be defined in tools/llvm-xray/ to use this new type and interface for loading from files. We also remove the flag from the `llvm-xray` tool that required users to specify the type of the instrumentation map file being provided to instead make the library auto-detect the file type. Reviewers: dblaikie Subscribers: mgorny, varno, llvm-commits Differential Revision: https://reviews.llvm.org/D29319 llvm-svn: 293721
* InferAddressSpaces: Remove dead declarationMatt Arsenault2017-01-311-1/+0
| | | | llvm-svn: 293720
* InferAddressSpaces: Avoid double map lookupMatt Arsenault2017-01-311-6/+4
| | | | llvm-svn: 293719
* InferAddressSpaces: Fix broken casting of constantsMatt Arsenault2017-01-311-2/+7
| | | | llvm-svn: 293718
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