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* Add parentheses to silence warning.Richard Trieu2016-04-061-1/+2
| | | | llvm-svn: 265516
* [IRVerifier] Don't crash on invalid DIFile inside DISubprogram.Davide Italiano2016-04-061-0/+2
| | | | llvm-svn: 265515
* [IRVerifier] Avoid crashing on an invalid compile unit.Davide Italiano2016-04-061-7/+8
| | | | llvm-svn: 265514
* AArch64: Fix compile errorMatthias Braun2016-04-061-1/+1
| | | | | | | Fixed to adapt a use of enterBasicBlock() in my last commit (because I had follow on patches in my repository that change the code). llvm-svn: 265513
* RegisterScavenger: Take a reference as enterBasicBlock() argument.Matthias Braun2016-04-069-17/+14
| | | | | | | Make it obvious that the argument cannot be nullptr. Remove an unnecessary nullptr check in initRegState. llvm-svn: 265511
* LivePhysRegs: Remove redundant checkMatthias Braun2016-04-061-1/+1
| | | | llvm-svn: 265509
* ValueMapper: Fix delayed blockaddress handling after r265273Duncan P. N. Exon Smith2016-04-061-3/+3
| | | | | | | | | r265273 added Mapper::mapBlockAddress, which delays mapping a blockaddress value until the function has a body. The condition was backwards, and should be checking Function::empty instead of GlobalValue::isDeclaration. llvm-svn: 265508
* AsmParser: Don't crash on unresolved !tbaaDuncan P. N. Exon Smith2016-04-061-4/+5
| | | | | | | | Instead of crashing, give a nice error. As a drive-by, fix the location associated with the errors for unresolved metadata (the location was off by one token). llvm-svn: 265507
* [ppc64] Enable sibling call optimization on ppc64 ELFv1/ELFv2 abiChuang-Yu Cheng2016-04-062-7/+228
| | | | | | | | | | | | | | | | | This patch enable sibling call optimization on ppc64 ELFv1/ELFv2 abi, and add a couple of test cases. This patch also passed llvm/clang bootstrap test, and spec2006 build/run/result validation. Original issue: https://llvm.org/bugs/show_bug.cgi?id=25617 Great thanks to Tom's (tjablin) help, he contributed a lot to this patch. Thanks Hal and Kit's invaluable opinions! Reviewers: hfinkel kbarton http://reviews.llvm.org/D16315 llvm-svn: 265506
* [Power9] Implement add-pc, multiply-add, modulo, extend-sign-shift, random ↵Chuang-Yu Cheng2016-04-067-0/+269
| | | | | | | | | | | | | | | | | | | | | number, set bool, and dfp test significance This patch implement the following instructions: - addpcis subpcis - maddhd maddhdu maddld - modsw moduw modsd modud - darn - extswsli extswsli. - setb - dtstsfi dtstsfiq Total 15 instructions Reviewers: nemanjai hfinkel tjablin amehsan kbarton http://reviews.llvm.org/D17885 llvm-svn: 265505
* [Power9] Implement copy-paste, msgsync, slb, and stop instructionsChuang-Yu Cheng2016-04-066-0/+109
| | | | | | | | | | | | | This patch implements the following BookII and Book III instructions: - copy copy_first cp_abort paste paste. paste_last - msgsync - slbieg slbsync - stop Total 10 instructions Reviewers: nemanjai hfinkel tjablin amehsan kbarton llvm-svn: 265504
* [RS4GC] Add a commentSanjoy Das2016-04-061-0/+4
| | | | llvm-svn: 265503
* Lower @llvm.experimental.deoptimize as a noreturn callSanjoy Das2016-04-063-7/+35
| | | | | | | | | | | | | | | | | | | | | | | While preserving the return value for @llvm.experimental.deoptimize at the IR level is useful during mid-level optimization, doing so at the machine instruction level requires generating some extra code and a return that is non-ideal. This change has LLVM lower ``` %val = call @llvm.experimental.deoptimize ret %val ``` to effectively ``` call @__llvm_deoptimize() unreachable ``` instead. llvm-svn: 265502
* AArch64CodeGen: Make AArch64RegisterBankInfo.cpp optional along ↵NAKAMURA Takumi2016-04-061-1/+13
| | | | | | LLVM_BUILD_GLOBAL_ISEL. llvm-svn: 265499
* [SLPVectorizer] Vectorize libcalls of sqrtDavid Majnemer2016-04-061-0/+4
| | | | | | | We didn't realize that we could transform the libcall into a vectorized intrinsic. llvm-svn: 265493
* [AArch64] Initial implementation of the targeting of the register bank ↵Quentin Colombet2016-04-053-0/+115
| | | | | | information. llvm-svn: 265489
* [RegisterBankInfo] Simplify the API for build a register bank.Quentin Colombet2016-04-051-5/+4
| | | | | | | | | As part of the TRI argument of addRegBankCoverage we already have access to the TargetRegisterClass through the ID of that register class. Therefore, there is no point in needing a TargetRegisterClass instance, the ID is enough to get to it. llvm-svn: 265487
* [RS4GC] NFC cleanup of the DeferredReplacement classSanjoy Das2016-04-051-5/+18
| | | | | | Instead of constructors use clearly named factory methods. llvm-svn: 265486
* [RS4GC] Better codegen for deoptimize callsSanjoy Das2016-04-051-16/+52
| | | | | | | | | Don't emit a gc.result for a statepoint lowered from @llvm.experimental.deoptimize since the call into __llvm_deoptimize is effectively noreturn. Instead follow the corresponding gc.statepoint with an "unreachable". llvm-svn: 265485
* Swift Calling Convention: swiftcc for ARM.Manman Ren2016-04-052-0/+3
| | | | | | Differential Revision: http://reviews.llvm.org/D18769 llvm-svn: 265482
* Faster stack-protector for Android/AArch64.Evgeniy Stepanov2016-04-055-27/+42
| | | | | | | Bionic has a defined thread-local location for the stack protector cookie. Emit a direct load instead of going through __stack_chk_guard. llvm-svn: 265481
* Swift Calling Convention: add swiftcc.Manman Ren2016-04-056-0/+27
| | | | | | Differential Revision: http://reviews.llvm.org/D17863 llvm-svn: 265480
* [RegisterBank] Implement the verify method to check for the obvious mistakes.Quentin Colombet2016-04-051-4/+27
| | | | llvm-svn: 265479
* [RegisterBankInfo] Add debug print to check how the initialization is going.Quentin Colombet2016-04-051-0/+11
| | | | llvm-svn: 265475
* [CFLAA] Fix PR27213; incorrect tagging of args/globalsGeorge Burgess IV2016-04-051-1/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | Prior to this patch, CFLAA wouldn't tag arguments/globals properly if it didn't find any "interesting" edges on them. This means that, if all you do is store constants to a global or argument, we would never actually treat it as a global/argument. Test case: define void @foo(i32* %A, i32* %B) #0 { entry: store i32 0, i32* %A, align 4 store i32 0, i32* %B, align 4 ret void } CFLAA would say that %A can't alias %B, because neither pointer was used in an interesting way. This patch makes us note whether something is an argument, global, ... regardless of how interesting CFLAA thinks its uses are. (For the record, using a value in an interesting way means loading from it, using it in a GEP, ...) llvm-svn: 265474
* [RegisterBank] Add printable capabilities for future debugging.Quentin Colombet2016-04-051-0/+34
| | | | llvm-svn: 265473
* Try harder to appease MSVC after r265456Duncan P. N. Exon Smith2016-04-051-3/+12
| | | | | | r265465 wasn't good enough. I need to spell out all the moves. llvm-svn: 265470
* [RegisterBankInfo] Make addRegBankCoverage more capable to easeQuentin Colombet2016-04-051-4/+67
| | | | | | | | targeting jobs. Now, addRegBankCoverage also adds the subreg-classes not just the sub-classes of the given register class. llvm-svn: 265469
* Minor code cleanups. NFC.Junmo Park2016-04-051-2/+2
| | | | llvm-svn: 265468
* IR: Introduce ConstantAggregate, NFCDuncan P. N. Exon Smith2016-04-056-46/+31
| | | | | | | | | | | | Add a common parent class for ConstantArray, ConstantVector, and ConstantStruct called ConstantAggregate. These are the aggregate subclasses of Constant that take operands. This is mainly a cleanup, adding common `isa` target and removing duplicated code. However, it also simplifies caching which constants point transitively at `GlobalValue` (a possible future direction). llvm-svn: 265466
* Try to appease MSVC after r265456Duncan P. N. Exon Smith2016-04-051-0/+4
| | | | | | | I can't remember if adding `= default` will make MSVC happy, or if I have to spell this out. Let's try the cleaner version first. llvm-svn: 265465
* [RegisterBankInfo] Implement the methods to create register banks.Quentin Colombet2016-04-051-4/+77
| | | | llvm-svn: 265464
* IR: Add missing assertion for ConstantVector::ConstantVectorDuncan P. N. Exon Smith2016-04-051-0/+2
| | | | | | | Use the same assertion as ConstantArray. Vectors should have the right number of elements. llvm-svn: 265463
* [RegisterBank] Provide a way to check if a register bank is valid.Quentin Colombet2016-04-051-1/+12
| | | | | | | | Change the default constructor to create invalid object. The target will have to properly initialize the register banks before using them. llvm-svn: 265460
* Revert "Fix Clang-tidy modernize-deprecated-headers warnings in remaining ↵Duncan P. N. Exon Smith2016-04-0516-287/+184
| | | | | | | | | | files; other minor fixes." This reverts commit r265454 since it broke the build. E.g.: http://lab.llvm.org:8080/green/job/clang-stage1-cmake-RA-incremental_build/22413/ llvm-svn: 265459
* ValueMapper: Rewrite Mapper::mapMetadata without recursionDuncan P. N. Exon Smith2016-04-051-108/+329
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit completely rewrites Mapper::mapMetadata (the implementation of llvm::MapMetadata) using an iterative algorithm. The guts of the new algorithm are in MDNodeMapper::map, the entry function in a new class. Previously, Mapper::mapMetadata performed a recursive exploration of the graph with eager "just in case there's a reason" malloc traffic. The new algorithm has these benefits: - New nodes and temporaries are not created eagerly. - Uniquing cycles are not duplicated (see new unit test). - No recursion. Given a node to map, it does this: 1. Use a worklist to perform a post-order traversal of the transitively referenced unmapped nodes. 2. Track which nodes will change operands, and which will have new addresses in the mapped scheme. Propagate the changes through the POT until fixed point, to pick up uniquing cycles that need to change. 3. Map all the distinct nodes without touching their operands. If RF_MoveDistinctMetadata, they get mapped to themselves; otherwise, they get mapped to clones. 4. Map the uniqued nodes (bottom-up), lazily creating temporaries for forward references as needed. 5. Remap the operands of the distinct nodes. Mehdi helped me out by profiling this with -flto=thin. On his workload (importing/etc. for opt.cpp), MapMetadata sped up by 15%, contributed about 50% less to persistent memory, and made about 100x fewer calls to malloc. The speedup is less than I'd hoped. The profile mainly blames DenseMap lookups; perhaps there's a way to reduce them (e.g., by disallowing remapping of MDString). It would be nice to break the strange remaining recursion on the Value side: MapValue => materializeInitFor => RemapInstruction => MapValue. I think we could do this by having materializeInitFor return a worklist of things to be remapped. llvm-svn: 265456
* Fix Clang-tidy modernize-deprecated-headers warnings in remaining files; ↵Eugene Zelenko2016-04-0516-184/+287
| | | | | | | | | | | | other minor fixes. Some Include What You Use suggestions were used too. Use anonymous namespaces in source files. Differential revision: http://reviews.llvm.org/D18778 llvm-svn: 265454
* [X86] Reuse EFLAGS and form LOCKed ops when only user is SETCC.Ahmed Bougacha2016-04-051-15/+76
| | | | | | | | | | | | | | | | | | | | We only generate LOCKed versions of add/sub when the result is unused. It often happens that the result is used, but only by a comparison. We can optimize those out by reusing EFLAGS, which lets us use the proper instructions, instead of having to fallback to LXADD. Instead of doing this as an MI peephole (as we do for the other non-LOCKed (really, non-MR) forms), do it in ISel. It becomes quite tricky later. This also makes it eventually possible to stop expanding and/or/xor if the only user is an icmp (also see D18141). This uses the LOCK ISD opcodes added by r262244. Differential Revision: http://reviews.llvm.org/D17633 llvm-svn: 265450
* [GlobalISel] Add the RegisterBankInfo class for the handling of register banks.Quentin Colombet2016-04-052-0/+29
| | | | llvm-svn: 265449
* [X86] Simplify early-exit check. NFC.Ahmed Bougacha2016-04-051-4/+4
| | | | llvm-svn: 265447
* [GlobalISel] Add a class, RegisterBank, to represent register banks.Quentin Colombet2016-04-052-0/+40
| | | | llvm-svn: 265445
* fix typo; NFCSanjay Patel2016-04-051-1/+1
| | | | llvm-svn: 265442
* [GlobalISel] Add the skeleton of the RegBankSelect pass.Quentin Colombet2016-04-053-0/+34
| | | | | | | This pass is reponsible for assigning the generic virtual registers to register banks. llvm-svn: 265440
* fix documentation comments; NFCSanjay Patel2016-04-051-39/+34
| | | | llvm-svn: 265434
* Swift Calling Convention: swifterror target-independent change.Manman Ren2016-04-055-4/+353
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | At IR level, the swifterror argument is an input argument with type ErrorObject**. For targets that support swifterror, we want to optimize it to behave as an inout value with type ErrorObject*; it will be passed in a fixed physical register. The main idea is to track the virtual registers for each swifterror value. We define swifterror values as AllocaInsts with swifterror attribute or a function argument with swifterror attribute. In SelectionDAGISel.cpp, we set up swifterror values (SwiftErrorVals) before handling the basic blocks. When iterating over all basic blocks in RPO, before actually visiting the basic block, we call mergeIncomingSwiftErrors to merge incoming swifterror values when there are multiple predecessors or to simply propagate them. There, we create a virtual register for each swifterror value in the entry block. For predecessors that are not yet visited, we create virtual registers to hold the swifterror values at the end of the predecessor. The assignments are saved in SwiftErrorWorklist and will be materialized at the end of visiting the basic block. When visiting a load from a swifterror value, we copy from the current virtual register assignment. When visiting a store to a swifterror value, we create a virtual register to hold the swifterror value and update SwiftErrorMap to track the current virtual register assignment. Differential Revision: http://reviews.llvm.org/D18108 llvm-svn: 265433
* [lanai] LanaiSetflagAluCombiner more conservativeJacques Pienaar2016-04-051-5/+7
| | | | | | | | | | | | Summary: LanaiSetflagAluCombiner could previously combine instructions across basic building blocks even when not legal. Make the LanaiSetflagAluCombiner more conservative to avoid this. Reviewers: eliben Subscribers: joker.eph, llvm-commits Differential Revision: http://reviews.llvm.org/D18746 llvm-svn: 265411
* [ARM] Cleanup of smul and smla instruction descriptionsSam Parker2016-04-051-12/+12
| | | | | | | | | Removed the SDNode argument passed to the AI_smul and AI_smla multiclass definitions as they are always mul. Differential Revision: http://reviews.llvm.org/D18791 llvm-svn: 265409
* [AMDGPU] Emit linkonce and linkonce_odr symbolsKonstantin Zhuravlyov2016-04-051-0/+2
| | | | | | Differential Revision: http://reviews.llvm.org/D18726 llvm-svn: 265408
* [BlockPlacement] Remove an unnecessary continueHaicheng Wu2016-04-051-1/+0
| | | | | | NFC. llvm-svn: 265407
* Don't delete empty preheaders in CodeGenPrepare if it would create a ↵Chuang-Yu Cheng2016-04-051-0/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | critical edge Presently, CodeGenPrepare deletes all nearly empty (only phi and branch) basic blocks. This pass can delete loop preheaders which frequently creates critical edges. A preheader can be a convenient place to spill registers to the stack. If the entrance to a loop body is a critical edge, then spills may occur in the loop body rather than immediately before it. This patch protects loop preheaders from deletion in CodeGenPrepare even if they are nearly empty. Since the patch alters the CFG, it affects a large number of test cases. In most cases, the changes are merely cosmetic (basic blocks have different names or instruction orders change slightly). I am somewhat concerned about the test/CodeGen/Mips/brdelayslot.ll test case. If the loop preheader is not deleted, then the MIPS backend does not take advantage of a branch delay slot. Consequently, I would like some close review by a MIPS expert. The patch also partially subsumes D16893 from George Burgess IV. George correctly notes that CodeGenPrepare does not actually preserve the dominator tree. I think the dominator tree was usually not valid when CodeGenPrepare ran, but I am using LoopInfo to mark preheaders, so the dominator tree is now always valid before CodeGenPrepare. Author: Tom Jablin (tjablin) Reviewers: hfinkel george.burgess.iv vkalintiris dsanders kbarton cycheng http://reviews.llvm.org/D16984 llvm-svn: 265397
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