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* Add some support for dealing with an object pointer on arguments.Eric Christopher2012-09-124-0/+40
| | | | | | Part of rdar://9797999 llvm-svn: 163667
* Rename the isMemory() function to isMem(). No functional change intended.Chad Rosier2012-09-111-22/+22
| | | | llvm-svn: 163654
* Release build: guard dump functions withManman Ren2012-09-1120-27/+27
| | | | | | | | "#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)" No functional change. Update r163339. llvm-svn: 163653
* StringSwitchify.Chad Rosier2012-09-111-8/+10
| | | | llvm-svn: 163649
* Simplify logic. No functional change intended.Chad Rosier2012-09-111-9/+8
| | | | llvm-svn: 163648
* [ms-inline asm] Split the parsing of IR asm strings into GCC and MS variants.Chad Rosier2012-09-111-67/+158
| | | | | | Add support in the EmitMSInlineAsmStr() function for handling integer consts. llvm-svn: 163645
* SimplifyCFG: preserve branch-weight metadata when creating a new switch fromManman Ren2012-09-111-81/+45
| | | | | | | | | | | | | a pair of switch/branch where both depend on the value of the same variable and the default case of the first switch/branch goes to the second switch/branch. Code clean up and fixed a few issues: 1> handling the case where some cases of the 2nd switch are invalidated 2> correctly calculate the weight for the 2nd switch when it is a conditional eq Testing case is modified from Alastair's original patch. llvm-svn: 163635
* Add TRI::getSubRegIndexLaneMask().Jakob Stoklund Olesen2012-09-111-2/+4
| | | | | | | | | | | | | | | | | Sub-register lane masks are bitmasks that can be used to determine if two sub-registers of a virtual register will overlap. For example, ARM's ssub0 and ssub1 sub-register indices don't overlap each other, but both overlap dsub0 and qsub0. The lane masks will be accurate on most targets, but on targets that use sub-register indexes in an irregular way, the masks may conservatively report that two sub-register indices overlap when the eventually allocated physregs don't. Irregular register banks also mean that the bits in a lane mask can't be mapped onto register units, but the concept is similar. llvm-svn: 163630
* Add MCRI::getNumSubRegIndices() and start checking SubRegIndex ranges.Jakob Stoklund Olesen2012-09-111-0/+3
| | | | | | | | Apparently, NumSubRegIndices was completely unused before. Adjust it by one to include the null subreg index, just like getNumRegs() includes the null register. llvm-svn: 163628
* Dragonegg selfhost exposed additional cases where alloca usage moved outside ↵Nadav Rotem2012-09-111-1/+1
| | | | | | of lifetime markers. Disabling the pass for now. llvm-svn: 163623
* Enable stack coloring.Nadav Rotem2012-09-111-1/+1
| | | | llvm-svn: 163617
* Stack Coloring: Dont crash on dbg values which use stack frames.Nadav Rotem2012-09-111-3/+5
| | | | llvm-svn: 163616
* Make a bunch of lowering helper functions static instead of member ↵Craig Topper2012-09-112-82/+56
| | | | | | functions. No functional change. llvm-svn: 163596
* Change unsigned to a uint16_t in static disassembler tables to reduce the ↵Craig Topper2012-09-112-2/+2
| | | | | | table size. llvm-svn: 163594
* llvm/lib/Transforms/Utils/CMakeLists.txt: Update.NAKAMURA Takumi2012-09-111-0/+1
| | | | llvm-svn: 163593
* Add a pass that renames everything with metasyntatic names. This works well ↵Alex Rosenberg2012-09-112-0/+133
| | | | | | after using bugpoint to reduce the confusion presented by the original names, which no longer mean what they used to. llvm-svn: 163592
* Teach DAG combiner to constant fold FABS of a BUILD_VECTOR of ConstantFPs. ↵Craig Topper2012-09-111-22/+47
| | | | | | Factor similar code out of FNEG DAG combiner. llvm-svn: 163587
* Add support for finding cacheflush on OpenBSD/mips64 platforms.Chandler Carruth2012-09-112-4/+8
| | | | | | Patch by Brad Smith! llvm-svn: 163584
* Reorganize MachineScheduler interfaces and publish them in the header.Andrew Trick2012-09-113-766/+118
| | | | | | | | | | | | | | The Hexagon target decided to use a lot of functionality from the target-independent scheduler. That's fine, and other targets should be able to do the same. This reorg and API update makes that easy. For the record, ScheduleDAGMI was not meant to be subclassed. Instead, new scheduling algorithms should be able to implement MachineSchedStrategy and be done. But if need be, it's nice to be able to extend ScheduleDAGMI, so I also made that easier. The target scheduler is somewhat more apt to break that way though. llvm-svn: 163580
* Revert r160148 it seems to cause more problems than it shouldEric Christopher2012-09-101-1/+1
| | | | | | right now. We'll fix PR13303 a different way. llvm-svn: 163570
* 80-col fixup.Eric Christopher2012-09-103-4/+6
| | | | llvm-svn: 163569
* 80-col fixup.Eric Christopher2012-09-101-1/+2
| | | | llvm-svn: 163568
* No reason to construct this twice.Eric Christopher2012-09-102-2/+2
| | | | llvm-svn: 163567
* Update function names to conform to guidelines. No functional change intended.Chad Rosier2012-09-107-14/+14
| | | | llvm-svn: 163561
* Revert r163556. Missed updates to tablegen files.Chad Rosier2012-09-102-4/+4
| | | | llvm-svn: 163557
* Update function names to conform to guidelines. No functional change intended.Chad Rosier2012-09-102-4/+4
| | | | llvm-svn: 163556
* [ms-inline asm] Properly emit the asm directives when the AsmPrinterVariantChad Rosier2012-09-101-1/+17
| | | | | | and InlineAsmVariant don't match. llvm-svn: 163550
* Remove redundant semicolons which are null statements.Dmitri Gribenko2012-09-106-7/+7
| | | | llvm-svn: 163547
* Disable stack coloring because it makes dragonegg fail bootstrapping.Nadav Rotem2012-09-101-1/+1
| | | | llvm-svn: 163545
* [ms-inline asm] Pass the correct AsmVariant to the PrintAsmOperand() functionChad Rosier2012-09-103-7/+10
| | | | | | and update the printOperand() function accordingly. llvm-svn: 163544
* [ms-inline asm] Add support for .att_syntax directive.Chad Rosier2012-09-101-1/+4
| | | | llvm-svn: 163542
* Enable stack coloring.Nadav Rotem2012-09-101-1/+1
| | | | llvm-svn: 163539
* Don't attempt to use flags from predicated instructions.Jakob Stoklund Olesen2012-09-101-2/+8
| | | | | | | | | | | | The ARM backend can eliminate cmp instructions by reusing flags from a nearby sub instruction with similar arguments. Don't do that if the sub is predicated - the flags are not written unconditionally. <rdar://problem/12263428> llvm-svn: 163535
* [Object] Extract Elf_Ehdr. Patch by Hemant Kulkarni!Michael J. Spencer2012-09-101-2/+1
| | | | llvm-svn: 163532
* Stack Coloring: Handle the case where END markers come before BEGIN markers ↵Nadav Rotem2012-09-101-0/+12
| | | | | | properly. llvm-svn: 163530
* Enhance PR11334 fix to support extload from v2f32/v4f32Michael Liao2012-09-103-7/+15
| | | | | | - Fix an remaining issue of PR11674 as well llvm-svn: 163528
* Add "blocked" heuristic to the Hexagon MI scheduler.Sergei Larin2012-09-102-177/+269
| | | | | | Improve AQ instruction selection in the Hexagon MI scheduler. llvm-svn: 163523
* Fold multiply by 0 or 1 when in UnsafeFPMath mode in SelectionDAG::getNode().Michael Ilseman2012-09-101-0/+18
| | | | | | This folding happens as early as possible for performance reasons, and to make sure it isn't foiled by other transforms (e.g. forming FMAs). llvm-svn: 163519
* whitespaceMichael Ilseman2012-09-101-10/+10
| | | | llvm-svn: 163518
* Add boolean simplification support from CMOVMichael Liao2012-09-101-12/+42
| | | | | | | | - If a boolean value is generated from CMOV and tested as boolean value, simplify the use of test result by referencing the original condition. RDRAND intrinisc is one of such cases. llvm-svn: 163516
* Fix an assertion failure when optimising a shufflevector incorrectly into ↵James Molloy2012-09-102-10/+12
| | | | | | concat_vectors, and a followup bug with SelectionDAG::getNode() creating nodes with invalid types. llvm-svn: 163511
* Minor cleanup. No functional change.Nadav Rotem2012-09-101-3/+3
| | | | llvm-svn: 163510
* Stack Coloring: Debug prints to print the slot number and not the array index.Nadav Rotem2012-09-101-1/+2
| | | | llvm-svn: 163509
* Stack Coloring: When searching for disjoint regions, do not compare ↵Nadav Rotem2012-09-101-1/+1
| | | | | | intervals twice or to theirself. llvm-svn: 163508
* Stack Coloring: Add support for multiple regions of the same slot, within a ↵Nadav Rotem2012-09-101-23/+33
| | | | | | single basic block. llvm-svn: 163507
* The VPSHUFB 256-bit instruction may be generated when one of input vector is ↵Elena Demikhovsky2012-09-101-4/+15
| | | | | | | | undefined or zeroinitializer. I've added the "zeroinitializer" case in this patch. llvm-svn: 163506
* Make helper function static.Benjamin Kramer2012-09-101-2/+1
| | | | llvm-svn: 163504
* Move bypassSlowDivision into the llvm namespace.Benjamin Kramer2012-09-101-4/+6
| | | | llvm-svn: 163503
* c bindings: revert LLVMConstInlineAsm to always use the default asm dialect.Benjamin Kramer2012-09-101-4/+2
| | | | | | | | - The C API should be stable - InlineAsm::AsmDialect is not exposed to C - The function didn't match the prototype so this was unreachable code llvm-svn: 163502
* Fix a typo in the comment.Nadav Rotem2012-09-101-2/+2
| | | | llvm-svn: 163496
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